1 /*
2  * Copyright 2017 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs <bskeggs@redhat.com>
23  */
24 #include "gf100.h"
25 #include "ctxgf100.h"
26 
27 #include <nvif/class.h>
28 
29 const struct gf100_gr_func
30 gp107_gr = {
31 	.oneinit_tiles = gm200_gr_oneinit_tiles,
32 	.oneinit_sm_id = gm200_gr_oneinit_sm_id,
33 	.init = gf100_gr_init,
34 	.init_gpc_mmu = gm200_gr_init_gpc_mmu,
35 	.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
36 	.init_zcull = gf117_gr_init_zcull,
37 	.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
38 	.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
39 	.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
40 	.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
41 	.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
42 	.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
43 	.init_419cc0 = gf100_gr_init_419cc0,
44 	.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
45 	.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
46 	.init_504430 = gm107_gr_init_504430,
47 	.init_shader_exceptions = gp100_gr_init_shader_exceptions,
48 	.init_rop_exceptions = gf100_gr_init_rop_exceptions,
49 	.init_exception2 = gf100_gr_init_exception2,
50 	.trap_mp = gf100_gr_trap_mp,
51 	.fecs.reset = gf100_gr_fecs_reset,
52 	.rops = gm200_gr_rops,
53 	.gpc_nr = 2,
54 	.tpc_nr = 3,
55 	.ppc_nr = 1,
56 	.grctx = &gp107_grctx,
57 	.zbc = &gp102_gr_zbc,
58 	.sclass = {
59 		{ -1, -1, FERMI_TWOD_A },
60 		{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
61 		{ -1, -1, PASCAL_B, &gf100_fermi },
62 		{ -1, -1, PASCAL_COMPUTE_B },
63 		{}
64 	}
65 };
66 
67 MODULE_FIRMWARE("nvidia/gp107/gr/fecs_bl.bin");
68 MODULE_FIRMWARE("nvidia/gp107/gr/fecs_inst.bin");
69 MODULE_FIRMWARE("nvidia/gp107/gr/fecs_data.bin");
70 MODULE_FIRMWARE("nvidia/gp107/gr/fecs_sig.bin");
71 MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_bl.bin");
72 MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_inst.bin");
73 MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_data.bin");
74 MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_sig.bin");
75 MODULE_FIRMWARE("nvidia/gp107/gr/sw_ctx.bin");
76 MODULE_FIRMWARE("nvidia/gp107/gr/sw_nonctx.bin");
77 MODULE_FIRMWARE("nvidia/gp107/gr/sw_bundle_init.bin");
78 MODULE_FIRMWARE("nvidia/gp107/gr/sw_method_init.bin");
79 
80 static const struct gf100_gr_fwif
81 gp107_gr_fwif[] = {
82 	{  0, gm200_gr_load, &gp107_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr },
83 	{ -1, gm200_gr_nofw },
84 	{}
85 };
86 
87 int
88 gp107_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
89 {
90 	return gf100_gr_new_(gp107_gr_fwif, device, type, inst, pgr);
91 }
92