1 /* 2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 #include "gk20a.h" 23 #include "ctxgf100.h" 24 25 #include <nvif/class.h> 26 #include <subdev/timer.h> 27 28 static struct nvkm_oclass 29 gm20b_gr_sclass[] = { 30 { FERMI_TWOD_A, &nvkm_object_ofuncs }, 31 { KEPLER_INLINE_TO_MEMORY_B, &nvkm_object_ofuncs }, 32 { MAXWELL_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, 33 { MAXWELL_COMPUTE_B, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, 34 {} 35 }; 36 37 static void 38 gm20b_gr_init_gpc_mmu(struct gf100_gr_priv *priv) 39 { 40 u32 val; 41 42 /* TODO this needs to be removed once secure boot works */ 43 if (1) { 44 nv_wr32(priv, 0x100ce4, 0xffffffff); 45 } 46 47 /* TODO update once secure boot works */ 48 val = nv_rd32(priv, 0x100c80); 49 val &= 0xf000087f; 50 nv_wr32(priv, 0x418880, val); 51 nv_wr32(priv, 0x418890, 0); 52 nv_wr32(priv, 0x418894, 0); 53 54 nv_wr32(priv, 0x4188b0, nv_rd32(priv, 0x100cc4)); 55 nv_wr32(priv, 0x4188b4, nv_rd32(priv, 0x100cc8)); 56 nv_wr32(priv, 0x4188b8, nv_rd32(priv, 0x100ccc)); 57 58 nv_wr32(priv, 0x4188ac, nv_rd32(priv, 0x100800)); 59 } 60 61 static void 62 gm20b_gr_set_hww_esr_report_mask(struct gf100_gr_priv *priv) 63 { 64 nv_wr32(priv, 0x419e44, 0xdffffe); 65 nv_wr32(priv, 0x419e4c, 0x5); 66 } 67 68 struct nvkm_oclass * 69 gm20b_gr_oclass = &(struct gk20a_gr_oclass) { 70 .gf100 = { 71 .base.handle = NV_ENGINE(GR, 0x2b), 72 .base.ofuncs = &(struct nvkm_ofuncs) { 73 .ctor = gk20a_gr_ctor, 74 .dtor = gf100_gr_dtor, 75 .init = gk20a_gr_init, 76 .fini = _nvkm_gr_fini, 77 }, 78 .cclass = &gm20b_grctx_oclass, 79 .sclass = gm20b_gr_sclass, 80 .ppc_nr = 1, 81 }, 82 .init_gpc_mmu = gm20b_gr_init_gpc_mmu, 83 .set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask, 84 }.gf100.base; 85