1 /* 2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 #include "gk20a.h" 23 #include "ctxgf100.h" 24 25 #include <nvif/class.h> 26 #include <subdev/timer.h> 27 28 static struct nvkm_oclass 29 gm20b_gr_sclass[] = { 30 { FERMI_TWOD_A, &nvkm_object_ofuncs }, 31 { KEPLER_INLINE_TO_MEMORY_B, &nvkm_object_ofuncs }, 32 { MAXWELL_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, 33 { MAXWELL_COMPUTE_B, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, 34 {} 35 }; 36 37 static void 38 gm20b_gr_init_gpc_mmu(struct gf100_gr *gr) 39 { 40 struct nvkm_device *device = gr->base.engine.subdev.device; 41 u32 val; 42 43 /* TODO this needs to be removed once secure boot works */ 44 if (1) { 45 nvkm_wr32(device, 0x100ce4, 0xffffffff); 46 } 47 48 /* TODO update once secure boot works */ 49 val = nvkm_rd32(device, 0x100c80); 50 val &= 0xf000087f; 51 nvkm_wr32(device, 0x418880, val); 52 nvkm_wr32(device, 0x418890, 0); 53 nvkm_wr32(device, 0x418894, 0); 54 55 nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); 56 nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8)); 57 nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc)); 58 59 nvkm_wr32(device, 0x4188ac, nvkm_rd32(device, 0x100800)); 60 } 61 62 static void 63 gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr) 64 { 65 struct nvkm_device *device = gr->base.engine.subdev.device; 66 nvkm_wr32(device, 0x419e44, 0xdffffe); 67 nvkm_wr32(device, 0x419e4c, 0x5); 68 } 69 70 struct nvkm_oclass * 71 gm20b_gr_oclass = &(struct gk20a_gr_oclass) { 72 .gf100 = { 73 .base.handle = NV_ENGINE(GR, 0x2b), 74 .base.ofuncs = &(struct nvkm_ofuncs) { 75 .ctor = gk20a_gr_ctor, 76 .dtor = gf100_gr_dtor, 77 .init = gk20a_gr_init, 78 .fini = _nvkm_gr_fini, 79 }, 80 .cclass = &gm20b_grctx_oclass, 81 .sclass = gm20b_gr_sclass, 82 .ppc_nr = 1, 83 }, 84 .init_gpc_mmu = gm20b_gr_init_gpc_mmu, 85 .set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask, 86 }.gf100.base; 87