1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "gf100.h" 25 #include "ctxgf100.h" 26 #include "fuc/os.h" 27 28 #include <core/client.h> 29 #include <core/handle.h> 30 #include <core/option.h> 31 #include <engine/fifo.h> 32 #include <subdev/fb.h> 33 #include <subdev/mc.h> 34 #include <subdev/timer.h> 35 36 #include <nvif/class.h> 37 #include <nvif/unpack.h> 38 39 /******************************************************************************* 40 * Zero Bandwidth Clear 41 ******************************************************************************/ 42 43 static void 44 gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) 45 { 46 struct nvkm_device *device = gr->base.engine.subdev.device; 47 if (gr->zbc_color[zbc].format) { 48 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); 49 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); 50 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); 51 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); 52 } 53 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); 54 nvkm_wr32(device, 0x405820, zbc); 55 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ 56 } 57 58 static int 59 gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, 60 const u32 ds[4], const u32 l2[4]) 61 { 62 struct nvkm_ltc *ltc = nvkm_ltc(gr); 63 int zbc = -ENOSPC, i; 64 65 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { 66 if (gr->zbc_color[i].format) { 67 if (gr->zbc_color[i].format != format) 68 continue; 69 if (memcmp(gr->zbc_color[i].ds, ds, sizeof( 70 gr->zbc_color[i].ds))) 71 continue; 72 if (memcmp(gr->zbc_color[i].l2, l2, sizeof( 73 gr->zbc_color[i].l2))) { 74 WARN_ON(1); 75 return -EINVAL; 76 } 77 return i; 78 } else { 79 zbc = (zbc < 0) ? i : zbc; 80 } 81 } 82 83 if (zbc < 0) 84 return zbc; 85 86 memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); 87 memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); 88 gr->zbc_color[zbc].format = format; 89 ltc->zbc_color_get(ltc, zbc, l2); 90 gf100_gr_zbc_clear_color(gr, zbc); 91 return zbc; 92 } 93 94 static void 95 gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) 96 { 97 struct nvkm_device *device = gr->base.engine.subdev.device; 98 if (gr->zbc_depth[zbc].format) 99 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); 100 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); 101 nvkm_wr32(device, 0x405820, zbc); 102 nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ 103 } 104 105 static int 106 gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, 107 const u32 ds, const u32 l2) 108 { 109 struct nvkm_ltc *ltc = nvkm_ltc(gr); 110 int zbc = -ENOSPC, i; 111 112 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { 113 if (gr->zbc_depth[i].format) { 114 if (gr->zbc_depth[i].format != format) 115 continue; 116 if (gr->zbc_depth[i].ds != ds) 117 continue; 118 if (gr->zbc_depth[i].l2 != l2) { 119 WARN_ON(1); 120 return -EINVAL; 121 } 122 return i; 123 } else { 124 zbc = (zbc < 0) ? i : zbc; 125 } 126 } 127 128 if (zbc < 0) 129 return zbc; 130 131 gr->zbc_depth[zbc].format = format; 132 gr->zbc_depth[zbc].ds = ds; 133 gr->zbc_depth[zbc].l2 = l2; 134 ltc->zbc_depth_get(ltc, zbc, l2); 135 gf100_gr_zbc_clear_depth(gr, zbc); 136 return zbc; 137 } 138 139 /******************************************************************************* 140 * Graphics object classes 141 ******************************************************************************/ 142 143 static int 144 gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) 145 { 146 struct gf100_gr *gr = (void *)object->engine; 147 union { 148 struct fermi_a_zbc_color_v0 v0; 149 } *args = data; 150 int ret; 151 152 if (nvif_unpack(args->v0, 0, 0, false)) { 153 switch (args->v0.format) { 154 case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: 155 case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: 156 case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32: 157 case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16: 158 case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16: 159 case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16: 160 case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16: 161 case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16: 162 case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8: 163 case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8: 164 case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10: 165 case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10: 166 case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8: 167 case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8: 168 case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8: 169 case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8: 170 case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: 171 case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: 172 case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: 173 ret = gf100_gr_zbc_color_get(gr, args->v0.format, 174 args->v0.ds, 175 args->v0.l2); 176 if (ret >= 0) { 177 args->v0.index = ret; 178 return 0; 179 } 180 break; 181 default: 182 return -EINVAL; 183 } 184 } 185 186 return ret; 187 } 188 189 static int 190 gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) 191 { 192 struct gf100_gr *gr = (void *)object->engine; 193 union { 194 struct fermi_a_zbc_depth_v0 v0; 195 } *args = data; 196 int ret; 197 198 if (nvif_unpack(args->v0, 0, 0, false)) { 199 switch (args->v0.format) { 200 case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: 201 ret = gf100_gr_zbc_depth_get(gr, args->v0.format, 202 args->v0.ds, 203 args->v0.l2); 204 return (ret >= 0) ? 0 : -ENOSPC; 205 default: 206 return -EINVAL; 207 } 208 } 209 210 return ret; 211 } 212 213 static int 214 gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) 215 { 216 switch (mthd) { 217 case FERMI_A_ZBC_COLOR: 218 return gf100_fermi_mthd_zbc_color(object, data, size); 219 case FERMI_A_ZBC_DEPTH: 220 return gf100_fermi_mthd_zbc_depth(object, data, size); 221 default: 222 break; 223 } 224 return -EINVAL; 225 } 226 227 struct nvkm_ofuncs 228 gf100_fermi_ofuncs = { 229 .ctor = _nvkm_object_ctor, 230 .dtor = nvkm_object_destroy, 231 .init = nvkm_object_init, 232 .fini = nvkm_object_fini, 233 .mthd = gf100_fermi_mthd, 234 }; 235 236 static int 237 gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd, 238 void *pdata, u32 size) 239 { 240 struct gf100_gr *gr = (void *)object->engine; 241 struct nvkm_device *device = gr->base.engine.subdev.device; 242 if (size >= sizeof(u32)) { 243 u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000; 244 nvkm_wr32(device, 0x419e44, data); 245 nvkm_wr32(device, 0x419e4c, data); 246 return 0; 247 } 248 return -EINVAL; 249 } 250 251 struct nvkm_omthds 252 gf100_gr_9097_omthds[] = { 253 { 0x1528, 0x1528, gf100_gr_set_shader_exceptions }, 254 {} 255 }; 256 257 struct nvkm_omthds 258 gf100_gr_90c0_omthds[] = { 259 { 0x1528, 0x1528, gf100_gr_set_shader_exceptions }, 260 {} 261 }; 262 263 struct nvkm_oclass 264 gf100_gr_sclass[] = { 265 { FERMI_TWOD_A, &nvkm_object_ofuncs }, 266 { FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs }, 267 { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, 268 { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, 269 {} 270 }; 271 272 /******************************************************************************* 273 * PGRAPH context 274 ******************************************************************************/ 275 276 int 277 gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 278 struct nvkm_oclass *oclass, void *args, u32 size, 279 struct nvkm_object **pobject) 280 { 281 struct nvkm_vm *vm = nvkm_client(parent)->vm; 282 struct gf100_gr *gr = (void *)engine; 283 struct gf100_gr_data *data = gr->mmio_data; 284 struct gf100_gr_mmio *mmio = gr->mmio_list; 285 struct gf100_gr_chan *chan; 286 int ret, i; 287 288 /* allocate memory for context, and fill with default values */ 289 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 290 gr->size, 0x100, 291 NVOBJ_FLAG_ZERO_ALLOC, &chan); 292 *pobject = nv_object(chan); 293 if (ret) 294 return ret; 295 296 /* allocate memory for a "mmio list" buffer that's used by the HUB 297 * fuc to modify some per-context register settings on first load 298 * of the context. 299 */ 300 ret = nvkm_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0, 301 &chan->mmio); 302 if (ret) 303 return ret; 304 305 ret = nvkm_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm, 306 NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS, 307 &chan->mmio_vma); 308 if (ret) 309 return ret; 310 311 /* allocate buffers referenced by mmio list */ 312 for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) { 313 ret = nvkm_gpuobj_new(nv_object(chan), NULL, data->size, 314 data->align, 0, &chan->data[i].mem); 315 if (ret) 316 return ret; 317 318 ret = nvkm_gpuobj_map_vm(chan->data[i].mem, vm, data->access, 319 &chan->data[i].vma); 320 if (ret) 321 return ret; 322 323 data++; 324 } 325 326 /* finally, fill in the mmio list and point the context at it */ 327 for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) { 328 u32 addr = mmio->addr; 329 u32 data = mmio->data; 330 331 if (mmio->buffer >= 0) { 332 u64 info = chan->data[mmio->buffer].vma.offset; 333 data |= info >> mmio->shift; 334 } 335 336 nv_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); 337 nv_wo32(chan->mmio, chan->mmio_nr++ * 4, data); 338 mmio++; 339 } 340 341 for (i = 0; i < gr->size; i += 4) 342 nv_wo32(chan, i, gr->data[i / 4]); 343 344 if (!gr->firmware) { 345 nv_wo32(chan, 0x00, chan->mmio_nr / 2); 346 nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8); 347 } else { 348 nv_wo32(chan, 0xf4, 0); 349 nv_wo32(chan, 0xf8, 0); 350 nv_wo32(chan, 0x10, chan->mmio_nr / 2); 351 nv_wo32(chan, 0x14, lower_32_bits(chan->mmio_vma.offset)); 352 nv_wo32(chan, 0x18, upper_32_bits(chan->mmio_vma.offset)); 353 nv_wo32(chan, 0x1c, 1); 354 nv_wo32(chan, 0x20, 0); 355 nv_wo32(chan, 0x28, 0); 356 nv_wo32(chan, 0x2c, 0); 357 } 358 359 return 0; 360 } 361 362 void 363 gf100_gr_context_dtor(struct nvkm_object *object) 364 { 365 struct gf100_gr_chan *chan = (void *)object; 366 int i; 367 368 for (i = 0; i < ARRAY_SIZE(chan->data); i++) { 369 nvkm_gpuobj_unmap(&chan->data[i].vma); 370 nvkm_gpuobj_ref(NULL, &chan->data[i].mem); 371 } 372 373 nvkm_gpuobj_unmap(&chan->mmio_vma); 374 nvkm_gpuobj_ref(NULL, &chan->mmio); 375 376 nvkm_gr_context_destroy(&chan->base); 377 } 378 379 /******************************************************************************* 380 * PGRAPH register lists 381 ******************************************************************************/ 382 383 const struct gf100_gr_init 384 gf100_gr_init_main_0[] = { 385 { 0x400080, 1, 0x04, 0x003083c2 }, 386 { 0x400088, 1, 0x04, 0x00006fe7 }, 387 { 0x40008c, 1, 0x04, 0x00000000 }, 388 { 0x400090, 1, 0x04, 0x00000030 }, 389 { 0x40013c, 1, 0x04, 0x013901f7 }, 390 { 0x400140, 1, 0x04, 0x00000100 }, 391 { 0x400144, 1, 0x04, 0x00000000 }, 392 { 0x400148, 1, 0x04, 0x00000110 }, 393 { 0x400138, 1, 0x04, 0x00000000 }, 394 { 0x400130, 2, 0x04, 0x00000000 }, 395 { 0x400124, 1, 0x04, 0x00000002 }, 396 {} 397 }; 398 399 const struct gf100_gr_init 400 gf100_gr_init_fe_0[] = { 401 { 0x40415c, 1, 0x04, 0x00000000 }, 402 { 0x404170, 1, 0x04, 0x00000000 }, 403 {} 404 }; 405 406 const struct gf100_gr_init 407 gf100_gr_init_pri_0[] = { 408 { 0x404488, 2, 0x04, 0x00000000 }, 409 {} 410 }; 411 412 const struct gf100_gr_init 413 gf100_gr_init_rstr2d_0[] = { 414 { 0x407808, 1, 0x04, 0x00000000 }, 415 {} 416 }; 417 418 const struct gf100_gr_init 419 gf100_gr_init_pd_0[] = { 420 { 0x406024, 1, 0x04, 0x00000000 }, 421 {} 422 }; 423 424 const struct gf100_gr_init 425 gf100_gr_init_ds_0[] = { 426 { 0x405844, 1, 0x04, 0x00ffffff }, 427 { 0x405850, 1, 0x04, 0x00000000 }, 428 { 0x405908, 1, 0x04, 0x00000000 }, 429 {} 430 }; 431 432 const struct gf100_gr_init 433 gf100_gr_init_scc_0[] = { 434 { 0x40803c, 1, 0x04, 0x00000000 }, 435 {} 436 }; 437 438 const struct gf100_gr_init 439 gf100_gr_init_prop_0[] = { 440 { 0x4184a0, 1, 0x04, 0x00000000 }, 441 {} 442 }; 443 444 const struct gf100_gr_init 445 gf100_gr_init_gpc_unk_0[] = { 446 { 0x418604, 1, 0x04, 0x00000000 }, 447 { 0x418680, 1, 0x04, 0x00000000 }, 448 { 0x418714, 1, 0x04, 0x80000000 }, 449 { 0x418384, 1, 0x04, 0x00000000 }, 450 {} 451 }; 452 453 const struct gf100_gr_init 454 gf100_gr_init_setup_0[] = { 455 { 0x418814, 3, 0x04, 0x00000000 }, 456 {} 457 }; 458 459 const struct gf100_gr_init 460 gf100_gr_init_crstr_0[] = { 461 { 0x418b04, 1, 0x04, 0x00000000 }, 462 {} 463 }; 464 465 const struct gf100_gr_init 466 gf100_gr_init_setup_1[] = { 467 { 0x4188c8, 1, 0x04, 0x80000000 }, 468 { 0x4188cc, 1, 0x04, 0x00000000 }, 469 { 0x4188d0, 1, 0x04, 0x00010000 }, 470 { 0x4188d4, 1, 0x04, 0x00000001 }, 471 {} 472 }; 473 474 const struct gf100_gr_init 475 gf100_gr_init_zcull_0[] = { 476 { 0x418910, 1, 0x04, 0x00010001 }, 477 { 0x418914, 1, 0x04, 0x00000301 }, 478 { 0x418918, 1, 0x04, 0x00800000 }, 479 { 0x418980, 1, 0x04, 0x77777770 }, 480 { 0x418984, 3, 0x04, 0x77777777 }, 481 {} 482 }; 483 484 const struct gf100_gr_init 485 gf100_gr_init_gpm_0[] = { 486 { 0x418c04, 1, 0x04, 0x00000000 }, 487 { 0x418c88, 1, 0x04, 0x00000000 }, 488 {} 489 }; 490 491 const struct gf100_gr_init 492 gf100_gr_init_gpc_unk_1[] = { 493 { 0x418d00, 1, 0x04, 0x00000000 }, 494 { 0x418f08, 1, 0x04, 0x00000000 }, 495 { 0x418e00, 1, 0x04, 0x00000050 }, 496 { 0x418e08, 1, 0x04, 0x00000000 }, 497 {} 498 }; 499 500 const struct gf100_gr_init 501 gf100_gr_init_gcc_0[] = { 502 { 0x41900c, 1, 0x04, 0x00000000 }, 503 { 0x419018, 1, 0x04, 0x00000000 }, 504 {} 505 }; 506 507 const struct gf100_gr_init 508 gf100_gr_init_tpccs_0[] = { 509 { 0x419d08, 2, 0x04, 0x00000000 }, 510 { 0x419d10, 1, 0x04, 0x00000014 }, 511 {} 512 }; 513 514 const struct gf100_gr_init 515 gf100_gr_init_tex_0[] = { 516 { 0x419ab0, 1, 0x04, 0x00000000 }, 517 { 0x419ab8, 1, 0x04, 0x000000e7 }, 518 { 0x419abc, 2, 0x04, 0x00000000 }, 519 {} 520 }; 521 522 const struct gf100_gr_init 523 gf100_gr_init_pe_0[] = { 524 { 0x41980c, 3, 0x04, 0x00000000 }, 525 { 0x419844, 1, 0x04, 0x00000000 }, 526 { 0x41984c, 1, 0x04, 0x00005bc5 }, 527 { 0x419850, 4, 0x04, 0x00000000 }, 528 {} 529 }; 530 531 const struct gf100_gr_init 532 gf100_gr_init_l1c_0[] = { 533 { 0x419c98, 1, 0x04, 0x00000000 }, 534 { 0x419ca8, 1, 0x04, 0x80000000 }, 535 { 0x419cb4, 1, 0x04, 0x00000000 }, 536 { 0x419cb8, 1, 0x04, 0x00008bf4 }, 537 { 0x419cbc, 1, 0x04, 0x28137606 }, 538 { 0x419cc0, 2, 0x04, 0x00000000 }, 539 {} 540 }; 541 542 const struct gf100_gr_init 543 gf100_gr_init_wwdx_0[] = { 544 { 0x419bd4, 1, 0x04, 0x00800000 }, 545 { 0x419bdc, 1, 0x04, 0x00000000 }, 546 {} 547 }; 548 549 const struct gf100_gr_init 550 gf100_gr_init_tpccs_1[] = { 551 { 0x419d2c, 1, 0x04, 0x00000000 }, 552 {} 553 }; 554 555 const struct gf100_gr_init 556 gf100_gr_init_mpc_0[] = { 557 { 0x419c0c, 1, 0x04, 0x00000000 }, 558 {} 559 }; 560 561 static const struct gf100_gr_init 562 gf100_gr_init_sm_0[] = { 563 { 0x419e00, 1, 0x04, 0x00000000 }, 564 { 0x419ea0, 1, 0x04, 0x00000000 }, 565 { 0x419ea4, 1, 0x04, 0x00000100 }, 566 { 0x419ea8, 1, 0x04, 0x00001100 }, 567 { 0x419eac, 1, 0x04, 0x11100702 }, 568 { 0x419eb0, 1, 0x04, 0x00000003 }, 569 { 0x419eb4, 4, 0x04, 0x00000000 }, 570 { 0x419ec8, 1, 0x04, 0x06060618 }, 571 { 0x419ed0, 1, 0x04, 0x0eff0e38 }, 572 { 0x419ed4, 1, 0x04, 0x011104f1 }, 573 { 0x419edc, 1, 0x04, 0x00000000 }, 574 { 0x419f00, 1, 0x04, 0x00000000 }, 575 { 0x419f2c, 1, 0x04, 0x00000000 }, 576 {} 577 }; 578 579 const struct gf100_gr_init 580 gf100_gr_init_be_0[] = { 581 { 0x40880c, 1, 0x04, 0x00000000 }, 582 { 0x408910, 9, 0x04, 0x00000000 }, 583 { 0x408950, 1, 0x04, 0x00000000 }, 584 { 0x408954, 1, 0x04, 0x0000ffff }, 585 { 0x408984, 1, 0x04, 0x00000000 }, 586 { 0x408988, 1, 0x04, 0x08040201 }, 587 { 0x40898c, 1, 0x04, 0x80402010 }, 588 {} 589 }; 590 591 const struct gf100_gr_init 592 gf100_gr_init_fe_1[] = { 593 { 0x4040f0, 1, 0x04, 0x00000000 }, 594 {} 595 }; 596 597 const struct gf100_gr_init 598 gf100_gr_init_pe_1[] = { 599 { 0x419880, 1, 0x04, 0x00000002 }, 600 {} 601 }; 602 603 static const struct gf100_gr_pack 604 gf100_gr_pack_mmio[] = { 605 { gf100_gr_init_main_0 }, 606 { gf100_gr_init_fe_0 }, 607 { gf100_gr_init_pri_0 }, 608 { gf100_gr_init_rstr2d_0 }, 609 { gf100_gr_init_pd_0 }, 610 { gf100_gr_init_ds_0 }, 611 { gf100_gr_init_scc_0 }, 612 { gf100_gr_init_prop_0 }, 613 { gf100_gr_init_gpc_unk_0 }, 614 { gf100_gr_init_setup_0 }, 615 { gf100_gr_init_crstr_0 }, 616 { gf100_gr_init_setup_1 }, 617 { gf100_gr_init_zcull_0 }, 618 { gf100_gr_init_gpm_0 }, 619 { gf100_gr_init_gpc_unk_1 }, 620 { gf100_gr_init_gcc_0 }, 621 { gf100_gr_init_tpccs_0 }, 622 { gf100_gr_init_tex_0 }, 623 { gf100_gr_init_pe_0 }, 624 { gf100_gr_init_l1c_0 }, 625 { gf100_gr_init_wwdx_0 }, 626 { gf100_gr_init_tpccs_1 }, 627 { gf100_gr_init_mpc_0 }, 628 { gf100_gr_init_sm_0 }, 629 { gf100_gr_init_be_0 }, 630 { gf100_gr_init_fe_1 }, 631 { gf100_gr_init_pe_1 }, 632 {} 633 }; 634 635 /******************************************************************************* 636 * PGRAPH engine/subdev functions 637 ******************************************************************************/ 638 639 void 640 gf100_gr_zbc_init(struct gf100_gr *gr) 641 { 642 const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 643 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 644 const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 645 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; 646 const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 647 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 648 const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 649 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; 650 struct nvkm_ltc *ltc = nvkm_ltc(gr); 651 int index; 652 653 if (!gr->zbc_color[0].format) { 654 gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); 655 gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); 656 gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); 657 gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); 658 gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); 659 gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); 660 } 661 662 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) 663 gf100_gr_zbc_clear_color(gr, index); 664 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) 665 gf100_gr_zbc_clear_depth(gr, index); 666 } 667 668 /** 669 * Wait until GR goes idle. GR is considered idle if it is disabled by the 670 * MC (0x200) register, or GR is not busy and a context switch is not in 671 * progress. 672 */ 673 int 674 gf100_gr_wait_idle(struct gf100_gr *gr) 675 { 676 struct nvkm_device *device = gr->base.engine.subdev.device; 677 unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000); 678 bool gr_enabled, ctxsw_active, gr_busy; 679 680 do { 681 /* 682 * required to make sure FIFO_ENGINE_STATUS (0x2640) is 683 * up-to-date 684 */ 685 nvkm_rd32(device, 0x400700); 686 687 gr_enabled = nvkm_rd32(device, 0x200) & 0x1000; 688 ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000; 689 gr_busy = nvkm_rd32(device, 0x40060c) & 0x1; 690 691 if (!gr_enabled || (!gr_busy && !ctxsw_active)) 692 return 0; 693 } while (time_before(jiffies, end_jiffies)); 694 695 nv_error(gr, "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n", 696 gr_enabled, ctxsw_active, gr_busy); 697 return -EAGAIN; 698 } 699 700 void 701 gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) 702 { 703 struct nvkm_device *device = gr->base.engine.subdev.device; 704 const struct gf100_gr_pack *pack; 705 const struct gf100_gr_init *init; 706 707 pack_for_each_init(init, pack, p) { 708 u32 next = init->addr + init->count * init->pitch; 709 u32 addr = init->addr; 710 while (addr < next) { 711 nvkm_wr32(device, addr, init->data); 712 addr += init->pitch; 713 } 714 } 715 } 716 717 void 718 gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) 719 { 720 struct nvkm_device *device = gr->base.engine.subdev.device; 721 const struct gf100_gr_pack *pack; 722 const struct gf100_gr_init *init; 723 u32 data = 0; 724 725 nvkm_wr32(device, 0x400208, 0x80000000); 726 727 pack_for_each_init(init, pack, p) { 728 u32 next = init->addr + init->count * init->pitch; 729 u32 addr = init->addr; 730 731 if ((pack == p && init == p->init) || data != init->data) { 732 nvkm_wr32(device, 0x400204, init->data); 733 data = init->data; 734 } 735 736 while (addr < next) { 737 nvkm_wr32(device, 0x400200, addr); 738 /** 739 * Wait for GR to go idle after submitting a 740 * GO_IDLE bundle 741 */ 742 if ((addr & 0xffff) == 0xe100) 743 gf100_gr_wait_idle(gr); 744 nvkm_msec(device, 2000, 745 if (!(nvkm_rd32(device, 0x400700) & 0x00000004)) 746 break; 747 ); 748 addr += init->pitch; 749 } 750 } 751 752 nvkm_wr32(device, 0x400208, 0x00000000); 753 } 754 755 void 756 gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) 757 { 758 struct nvkm_device *device = gr->base.engine.subdev.device; 759 const struct gf100_gr_pack *pack; 760 const struct gf100_gr_init *init; 761 u32 data = 0; 762 763 pack_for_each_init(init, pack, p) { 764 u32 ctrl = 0x80000000 | pack->type; 765 u32 next = init->addr + init->count * init->pitch; 766 u32 addr = init->addr; 767 768 if ((pack == p && init == p->init) || data != init->data) { 769 nvkm_wr32(device, 0x40448c, init->data); 770 data = init->data; 771 } 772 773 while (addr < next) { 774 nvkm_wr32(device, 0x404488, ctrl | (addr << 14)); 775 addr += init->pitch; 776 } 777 } 778 } 779 780 u64 781 gf100_gr_units(struct nvkm_gr *obj) 782 { 783 struct gf100_gr *gr = container_of(obj, typeof(*gr), base); 784 u64 cfg; 785 786 cfg = (u32)gr->gpc_nr; 787 cfg |= (u32)gr->tpc_total << 8; 788 cfg |= (u64)gr->rop_nr << 32; 789 790 return cfg; 791 } 792 793 static const struct nvkm_enum gk104_sked_error[] = { 794 { 7, "CONSTANT_BUFFER_SIZE" }, 795 { 9, "LOCAL_MEMORY_SIZE_POS" }, 796 { 10, "LOCAL_MEMORY_SIZE_NEG" }, 797 { 11, "WARP_CSTACK_SIZE" }, 798 { 12, "TOTAL_TEMP_SIZE" }, 799 { 13, "REGISTER_COUNT" }, 800 { 18, "TOTAL_THREADS" }, 801 { 20, "PROGRAM_OFFSET" }, 802 { 21, "SHARED_MEMORY_SIZE" }, 803 { 25, "SHARED_CONFIG_TOO_SMALL" }, 804 { 26, "TOTAL_REGISTER_COUNT" }, 805 {} 806 }; 807 808 static const struct nvkm_enum gf100_gpc_rop_error[] = { 809 { 1, "RT_PITCH_OVERRUN" }, 810 { 4, "RT_WIDTH_OVERRUN" }, 811 { 5, "RT_HEIGHT_OVERRUN" }, 812 { 7, "ZETA_STORAGE_TYPE_MISMATCH" }, 813 { 8, "RT_STORAGE_TYPE_MISMATCH" }, 814 { 10, "RT_LINEAR_MISMATCH" }, 815 {} 816 }; 817 818 static void 819 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) 820 { 821 struct nvkm_device *device = gr->base.engine.subdev.device; 822 u32 trap[4]; 823 int i; 824 825 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)); 826 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); 827 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); 828 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); 829 830 nv_error(gr, "GPC%d/PROP trap:", gpc); 831 for (i = 0; i <= 29; ++i) { 832 if (!(trap[0] & (1 << i))) 833 continue; 834 pr_cont(" "); 835 nvkm_enum_print(gf100_gpc_rop_error, i); 836 } 837 pr_cont("\n"); 838 839 nv_error(gr, "x = %u, y = %u, format = %x, storage type = %x\n", 840 trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f, 841 trap[3] & 0xff); 842 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); 843 } 844 845 static const struct nvkm_enum gf100_mp_warp_error[] = { 846 { 0x00, "NO_ERROR" }, 847 { 0x01, "STACK_MISMATCH" }, 848 { 0x05, "MISALIGNED_PC" }, 849 { 0x08, "MISALIGNED_GPR" }, 850 { 0x09, "INVALID_OPCODE" }, 851 { 0x0d, "GPR_OUT_OF_BOUNDS" }, 852 { 0x0e, "MEM_OUT_OF_BOUNDS" }, 853 { 0x0f, "UNALIGNED_MEM_ACCESS" }, 854 { 0x11, "INVALID_PARAM" }, 855 {} 856 }; 857 858 static const struct nvkm_bitfield gf100_mp_global_error[] = { 859 { 0x00000004, "MULTIPLE_WARP_ERRORS" }, 860 { 0x00000008, "OUT_OF_STACK_SPACE" }, 861 {} 862 }; 863 864 static void 865 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) 866 { 867 struct nvkm_device *device = gr->base.engine.subdev.device; 868 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); 869 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); 870 871 nv_error(gr, "GPC%i/TPC%i/MP trap:", gpc, tpc); 872 nvkm_bitfield_print(gf100_mp_global_error, gerr); 873 if (werr) { 874 pr_cont(" "); 875 nvkm_enum_print(gf100_mp_warp_error, werr & 0xffff); 876 } 877 pr_cont("\n"); 878 879 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); 880 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); 881 } 882 883 static void 884 gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) 885 { 886 struct nvkm_device *device = gr->base.engine.subdev.device; 887 u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); 888 889 if (stat & 0x00000001) { 890 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); 891 nv_error(gr, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap); 892 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); 893 stat &= ~0x00000001; 894 } 895 896 if (stat & 0x00000002) { 897 gf100_gr_trap_mp(gr, gpc, tpc); 898 stat &= ~0x00000002; 899 } 900 901 if (stat & 0x00000004) { 902 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); 903 nv_error(gr, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap); 904 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); 905 stat &= ~0x00000004; 906 } 907 908 if (stat & 0x00000008) { 909 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); 910 nv_error(gr, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap); 911 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); 912 stat &= ~0x00000008; 913 } 914 915 if (stat) { 916 nv_error(gr, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat); 917 } 918 } 919 920 static void 921 gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) 922 { 923 struct nvkm_device *device = gr->base.engine.subdev.device; 924 u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); 925 int tpc; 926 927 if (stat & 0x00000001) { 928 gf100_gr_trap_gpc_rop(gr, gpc); 929 stat &= ~0x00000001; 930 } 931 932 if (stat & 0x00000002) { 933 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); 934 nv_error(gr, "GPC%d/ZCULL: 0x%08x\n", gpc, trap); 935 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); 936 stat &= ~0x00000002; 937 } 938 939 if (stat & 0x00000004) { 940 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); 941 nv_error(gr, "GPC%d/CCACHE: 0x%08x\n", gpc, trap); 942 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); 943 stat &= ~0x00000004; 944 } 945 946 if (stat & 0x00000008) { 947 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); 948 nv_error(gr, "GPC%d/ESETUP: 0x%08x\n", gpc, trap); 949 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); 950 stat &= ~0x00000009; 951 } 952 953 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { 954 u32 mask = 0x00010000 << tpc; 955 if (stat & mask) { 956 gf100_gr_trap_tpc(gr, gpc, tpc); 957 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); 958 stat &= ~mask; 959 } 960 } 961 962 if (stat) { 963 nv_error(gr, "GPC%d/0x%08x: unknown\n", gpc, stat); 964 } 965 } 966 967 static void 968 gf100_gr_trap_intr(struct gf100_gr *gr) 969 { 970 struct nvkm_device *device = gr->base.engine.subdev.device; 971 u32 trap = nvkm_rd32(device, 0x400108); 972 int rop, gpc, i; 973 974 if (trap & 0x00000001) { 975 u32 stat = nvkm_rd32(device, 0x404000); 976 nv_error(gr, "DISPATCH 0x%08x\n", stat); 977 nvkm_wr32(device, 0x404000, 0xc0000000); 978 nvkm_wr32(device, 0x400108, 0x00000001); 979 trap &= ~0x00000001; 980 } 981 982 if (trap & 0x00000002) { 983 u32 stat = nvkm_rd32(device, 0x404600); 984 nv_error(gr, "M2MF 0x%08x\n", stat); 985 nvkm_wr32(device, 0x404600, 0xc0000000); 986 nvkm_wr32(device, 0x400108, 0x00000002); 987 trap &= ~0x00000002; 988 } 989 990 if (trap & 0x00000008) { 991 u32 stat = nvkm_rd32(device, 0x408030); 992 nv_error(gr, "CCACHE 0x%08x\n", stat); 993 nvkm_wr32(device, 0x408030, 0xc0000000); 994 nvkm_wr32(device, 0x400108, 0x00000008); 995 trap &= ~0x00000008; 996 } 997 998 if (trap & 0x00000010) { 999 u32 stat = nvkm_rd32(device, 0x405840); 1000 nv_error(gr, "SHADER 0x%08x\n", stat); 1001 nvkm_wr32(device, 0x405840, 0xc0000000); 1002 nvkm_wr32(device, 0x400108, 0x00000010); 1003 trap &= ~0x00000010; 1004 } 1005 1006 if (trap & 0x00000040) { 1007 u32 stat = nvkm_rd32(device, 0x40601c); 1008 nv_error(gr, "UNK6 0x%08x\n", stat); 1009 nvkm_wr32(device, 0x40601c, 0xc0000000); 1010 nvkm_wr32(device, 0x400108, 0x00000040); 1011 trap &= ~0x00000040; 1012 } 1013 1014 if (trap & 0x00000080) { 1015 u32 stat = nvkm_rd32(device, 0x404490); 1016 nv_error(gr, "MACRO 0x%08x\n", stat); 1017 nvkm_wr32(device, 0x404490, 0xc0000000); 1018 nvkm_wr32(device, 0x400108, 0x00000080); 1019 trap &= ~0x00000080; 1020 } 1021 1022 if (trap & 0x00000100) { 1023 u32 stat = nvkm_rd32(device, 0x407020); 1024 1025 nv_error(gr, "SKED:"); 1026 for (i = 0; i <= 29; ++i) { 1027 if (!(stat & (1 << i))) 1028 continue; 1029 pr_cont(" "); 1030 nvkm_enum_print(gk104_sked_error, i); 1031 } 1032 pr_cont("\n"); 1033 1034 if (stat & 0x3fffffff) 1035 nvkm_wr32(device, 0x407020, 0x40000000); 1036 nvkm_wr32(device, 0x400108, 0x00000100); 1037 trap &= ~0x00000100; 1038 } 1039 1040 if (trap & 0x01000000) { 1041 u32 stat = nvkm_rd32(device, 0x400118); 1042 for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { 1043 u32 mask = 0x00000001 << gpc; 1044 if (stat & mask) { 1045 gf100_gr_trap_gpc(gr, gpc); 1046 nvkm_wr32(device, 0x400118, mask); 1047 stat &= ~mask; 1048 } 1049 } 1050 nvkm_wr32(device, 0x400108, 0x01000000); 1051 trap &= ~0x01000000; 1052 } 1053 1054 if (trap & 0x02000000) { 1055 for (rop = 0; rop < gr->rop_nr; rop++) { 1056 u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); 1057 u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); 1058 nv_error(gr, "ROP%d 0x%08x 0x%08x\n", 1059 rop, statz, statc); 1060 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); 1061 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); 1062 } 1063 nvkm_wr32(device, 0x400108, 0x02000000); 1064 trap &= ~0x02000000; 1065 } 1066 1067 if (trap) { 1068 nv_error(gr, "TRAP UNHANDLED 0x%08x\n", trap); 1069 nvkm_wr32(device, 0x400108, trap); 1070 } 1071 } 1072 1073 static void 1074 gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) 1075 { 1076 struct nvkm_device *device = gr->base.engine.subdev.device; 1077 nv_error(gr, "%06x - done 0x%08x\n", base, 1078 nvkm_rd32(device, base + 0x400)); 1079 nv_error(gr, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, 1080 nvkm_rd32(device, base + 0x800), nvkm_rd32(device, base + 0x804), 1081 nvkm_rd32(device, base + 0x808), nvkm_rd32(device, base + 0x80c)); 1082 nv_error(gr, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, 1083 nvkm_rd32(device, base + 0x810), nvkm_rd32(device, base + 0x814), 1084 nvkm_rd32(device, base + 0x818), nvkm_rd32(device, base + 0x81c)); 1085 } 1086 1087 void 1088 gf100_gr_ctxctl_debug(struct gf100_gr *gr) 1089 { 1090 struct nvkm_device *device = gr->base.engine.subdev.device; 1091 u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff; 1092 u32 gpc; 1093 1094 gf100_gr_ctxctl_debug_unit(gr, 0x409000); 1095 for (gpc = 0; gpc < gpcnr; gpc++) 1096 gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000)); 1097 } 1098 1099 static void 1100 gf100_gr_ctxctl_isr(struct gf100_gr *gr) 1101 { 1102 struct nvkm_device *device = gr->base.engine.subdev.device; 1103 u32 stat = nvkm_rd32(device, 0x409c18); 1104 1105 if (stat & 0x00000001) { 1106 u32 code = nvkm_rd32(device, 0x409814); 1107 if (code == E_BAD_FWMTHD) { 1108 u32 class = nvkm_rd32(device, 0x409808); 1109 u32 addr = nvkm_rd32(device, 0x40980c); 1110 u32 subc = (addr & 0x00070000) >> 16; 1111 u32 mthd = (addr & 0x00003ffc); 1112 u32 data = nvkm_rd32(device, 0x409810); 1113 1114 nv_error(gr, "FECS MTHD subc %d class 0x%04x " 1115 "mthd 0x%04x data 0x%08x\n", 1116 subc, class, mthd, data); 1117 1118 nvkm_wr32(device, 0x409c20, 0x00000001); 1119 stat &= ~0x00000001; 1120 } else { 1121 nv_error(gr, "FECS ucode error %d\n", code); 1122 } 1123 } 1124 1125 if (stat & 0x00080000) { 1126 nv_error(gr, "FECS watchdog timeout\n"); 1127 gf100_gr_ctxctl_debug(gr); 1128 nvkm_wr32(device, 0x409c20, 0x00080000); 1129 stat &= ~0x00080000; 1130 } 1131 1132 if (stat) { 1133 nv_error(gr, "FECS 0x%08x\n", stat); 1134 gf100_gr_ctxctl_debug(gr); 1135 nvkm_wr32(device, 0x409c20, stat); 1136 } 1137 } 1138 1139 static void 1140 gf100_gr_intr(struct nvkm_subdev *subdev) 1141 { 1142 struct gf100_gr *gr = (void *)subdev; 1143 struct nvkm_device *device = gr->base.engine.subdev.device; 1144 struct nvkm_fifo *fifo = device->fifo; 1145 struct nvkm_engine *engine = nv_engine(subdev); 1146 struct nvkm_object *engctx; 1147 struct nvkm_handle *handle; 1148 u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; 1149 u32 stat = nvkm_rd32(device, 0x400100); 1150 u32 addr = nvkm_rd32(device, 0x400704); 1151 u32 mthd = (addr & 0x00003ffc); 1152 u32 subc = (addr & 0x00070000) >> 16; 1153 u32 data = nvkm_rd32(device, 0x400708); 1154 u32 code = nvkm_rd32(device, 0x400110); 1155 u32 class; 1156 int chid; 1157 1158 if (nv_device(gr)->card_type < NV_E0 || subc < 4) 1159 class = nvkm_rd32(device, 0x404200 + (subc * 4)); 1160 else 1161 class = 0x0000; 1162 1163 engctx = nvkm_engctx_get(engine, inst); 1164 chid = fifo->chid(fifo, engctx); 1165 1166 if (stat & 0x00000001) { 1167 /* 1168 * notifier interrupt, only needed for cyclestats 1169 * can be safely ignored 1170 */ 1171 nvkm_wr32(device, 0x400100, 0x00000001); 1172 stat &= ~0x00000001; 1173 } 1174 1175 if (stat & 0x00000010) { 1176 handle = nvkm_handle_get_class(engctx, class); 1177 if (!handle || nv_call(handle->object, mthd, data)) { 1178 nv_error(gr, 1179 "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", 1180 chid, inst << 12, nvkm_client_name(engctx), 1181 subc, class, mthd, data); 1182 } 1183 nvkm_handle_put(handle); 1184 nvkm_wr32(device, 0x400100, 0x00000010); 1185 stat &= ~0x00000010; 1186 } 1187 1188 if (stat & 0x00000020) { 1189 nv_error(gr, 1190 "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", 1191 chid, inst << 12, nvkm_client_name(engctx), subc, 1192 class, mthd, data); 1193 nvkm_wr32(device, 0x400100, 0x00000020); 1194 stat &= ~0x00000020; 1195 } 1196 1197 if (stat & 0x00100000) { 1198 nv_error(gr, "DATA_ERROR ["); 1199 nvkm_enum_print(nv50_data_error_names, code); 1200 pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", 1201 chid, inst << 12, nvkm_client_name(engctx), subc, 1202 class, mthd, data); 1203 nvkm_wr32(device, 0x400100, 0x00100000); 1204 stat &= ~0x00100000; 1205 } 1206 1207 if (stat & 0x00200000) { 1208 nv_error(gr, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12, 1209 nvkm_client_name(engctx)); 1210 gf100_gr_trap_intr(gr); 1211 nvkm_wr32(device, 0x400100, 0x00200000); 1212 stat &= ~0x00200000; 1213 } 1214 1215 if (stat & 0x00080000) { 1216 gf100_gr_ctxctl_isr(gr); 1217 nvkm_wr32(device, 0x400100, 0x00080000); 1218 stat &= ~0x00080000; 1219 } 1220 1221 if (stat) { 1222 nv_error(gr, "unknown stat 0x%08x\n", stat); 1223 nvkm_wr32(device, 0x400100, stat); 1224 } 1225 1226 nvkm_wr32(device, 0x400500, 0x00010001); 1227 nvkm_engctx_put(engctx); 1228 } 1229 1230 void 1231 gf100_gr_init_fw(struct gf100_gr *gr, u32 fuc_base, 1232 struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) 1233 { 1234 struct nvkm_device *device = gr->base.engine.subdev.device; 1235 int i; 1236 1237 nvkm_wr32(device, fuc_base + 0x01c0, 0x01000000); 1238 for (i = 0; i < data->size / 4; i++) 1239 nvkm_wr32(device, fuc_base + 0x01c4, data->data[i]); 1240 1241 nvkm_wr32(device, fuc_base + 0x0180, 0x01000000); 1242 for (i = 0; i < code->size / 4; i++) { 1243 if ((i & 0x3f) == 0) 1244 nvkm_wr32(device, fuc_base + 0x0188, i >> 6); 1245 nvkm_wr32(device, fuc_base + 0x0184, code->data[i]); 1246 } 1247 1248 /* code must be padded to 0x40 words */ 1249 for (; i & 0x3f; i++) 1250 nvkm_wr32(device, fuc_base + 0x0184, 0); 1251 } 1252 1253 static void 1254 gf100_gr_init_csdata(struct gf100_gr *gr, 1255 const struct gf100_gr_pack *pack, 1256 u32 falcon, u32 starstar, u32 base) 1257 { 1258 struct nvkm_device *device = gr->base.engine.subdev.device; 1259 const struct gf100_gr_pack *iter; 1260 const struct gf100_gr_init *init; 1261 u32 addr = ~0, prev = ~0, xfer = 0; 1262 u32 star, temp; 1263 1264 nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar); 1265 star = nvkm_rd32(device, falcon + 0x01c4); 1266 temp = nvkm_rd32(device, falcon + 0x01c4); 1267 if (temp > star) 1268 star = temp; 1269 nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star); 1270 1271 pack_for_each_init(init, iter, pack) { 1272 u32 head = init->addr - base; 1273 u32 tail = head + init->count * init->pitch; 1274 while (head < tail) { 1275 if (head != prev + 4 || xfer >= 32) { 1276 if (xfer) { 1277 u32 data = ((--xfer << 26) | addr); 1278 nvkm_wr32(device, falcon + 0x01c4, data); 1279 star += 4; 1280 } 1281 addr = head; 1282 xfer = 0; 1283 } 1284 prev = head; 1285 xfer = xfer + 1; 1286 head = head + init->pitch; 1287 } 1288 } 1289 1290 nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr); 1291 nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar); 1292 nvkm_wr32(device, falcon + 0x01c4, star + 4); 1293 } 1294 1295 int 1296 gf100_gr_init_ctxctl(struct gf100_gr *gr) 1297 { 1298 struct nvkm_device *device = gr->base.engine.subdev.device; 1299 struct gf100_gr_oclass *oclass = (void *)nv_object(gr)->oclass; 1300 struct gf100_grctx_oclass *cclass = (void *)nv_engine(gr)->cclass; 1301 int i; 1302 1303 if (gr->firmware) { 1304 /* load fuc microcode */ 1305 nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); 1306 gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, 1307 &gr->fuc409d); 1308 gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, 1309 &gr->fuc41ad); 1310 nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); 1311 1312 /* start both of them running */ 1313 nvkm_wr32(device, 0x409840, 0xffffffff); 1314 nvkm_wr32(device, 0x41a10c, 0x00000000); 1315 nvkm_wr32(device, 0x40910c, 0x00000000); 1316 nvkm_wr32(device, 0x41a100, 0x00000002); 1317 nvkm_wr32(device, 0x409100, 0x00000002); 1318 if (nvkm_msec(device, 2000, 1319 if (nvkm_rd32(device, 0x409800) & 0x00000001) 1320 break; 1321 ) < 0) 1322 return -EBUSY; 1323 1324 nvkm_wr32(device, 0x409840, 0xffffffff); 1325 nvkm_wr32(device, 0x409500, 0x7fffffff); 1326 nvkm_wr32(device, 0x409504, 0x00000021); 1327 1328 nvkm_wr32(device, 0x409840, 0xffffffff); 1329 nvkm_wr32(device, 0x409500, 0x00000000); 1330 nvkm_wr32(device, 0x409504, 0x00000010); 1331 if (nvkm_msec(device, 2000, 1332 if ((gr->size = nvkm_rd32(device, 0x409800))) 1333 break; 1334 ) < 0) 1335 return -EBUSY; 1336 1337 nvkm_wr32(device, 0x409840, 0xffffffff); 1338 nvkm_wr32(device, 0x409500, 0x00000000); 1339 nvkm_wr32(device, 0x409504, 0x00000016); 1340 if (nvkm_msec(device, 2000, 1341 if (nvkm_rd32(device, 0x409800)) 1342 break; 1343 ) < 0) 1344 return -EBUSY; 1345 1346 nvkm_wr32(device, 0x409840, 0xffffffff); 1347 nvkm_wr32(device, 0x409500, 0x00000000); 1348 nvkm_wr32(device, 0x409504, 0x00000025); 1349 if (nvkm_msec(device, 2000, 1350 if (nvkm_rd32(device, 0x409800)) 1351 break; 1352 ) < 0) 1353 return -EBUSY; 1354 1355 if (nv_device(gr)->chipset >= 0xe0) { 1356 nvkm_wr32(device, 0x409800, 0x00000000); 1357 nvkm_wr32(device, 0x409500, 0x00000001); 1358 nvkm_wr32(device, 0x409504, 0x00000030); 1359 if (nvkm_msec(device, 2000, 1360 if (nvkm_rd32(device, 0x409800)) 1361 break; 1362 ) < 0) 1363 return -EBUSY; 1364 1365 nvkm_wr32(device, 0x409810, 0xb00095c8); 1366 nvkm_wr32(device, 0x409800, 0x00000000); 1367 nvkm_wr32(device, 0x409500, 0x00000001); 1368 nvkm_wr32(device, 0x409504, 0x00000031); 1369 if (nvkm_msec(device, 2000, 1370 if (nvkm_rd32(device, 0x409800)) 1371 break; 1372 ) < 0) 1373 return -EBUSY; 1374 1375 nvkm_wr32(device, 0x409810, 0x00080420); 1376 nvkm_wr32(device, 0x409800, 0x00000000); 1377 nvkm_wr32(device, 0x409500, 0x00000001); 1378 nvkm_wr32(device, 0x409504, 0x00000032); 1379 if (nvkm_msec(device, 2000, 1380 if (nvkm_rd32(device, 0x409800)) 1381 break; 1382 ) < 0) 1383 return -EBUSY; 1384 1385 nvkm_wr32(device, 0x409614, 0x00000070); 1386 nvkm_wr32(device, 0x409614, 0x00000770); 1387 nvkm_wr32(device, 0x40802c, 0x00000001); 1388 } 1389 1390 if (gr->data == NULL) { 1391 int ret = gf100_grctx_generate(gr); 1392 if (ret) { 1393 nv_error(gr, "failed to construct context\n"); 1394 return ret; 1395 } 1396 } 1397 1398 return 0; 1399 } else 1400 if (!oclass->fecs.ucode) { 1401 return -ENOSYS; 1402 } 1403 1404 /* load HUB microcode */ 1405 nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); 1406 nvkm_wr32(device, 0x4091c0, 0x01000000); 1407 for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) 1408 nvkm_wr32(device, 0x4091c4, oclass->fecs.ucode->data.data[i]); 1409 1410 nvkm_wr32(device, 0x409180, 0x01000000); 1411 for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) { 1412 if ((i & 0x3f) == 0) 1413 nvkm_wr32(device, 0x409188, i >> 6); 1414 nvkm_wr32(device, 0x409184, oclass->fecs.ucode->code.data[i]); 1415 } 1416 1417 /* load GPC microcode */ 1418 nvkm_wr32(device, 0x41a1c0, 0x01000000); 1419 for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++) 1420 nvkm_wr32(device, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); 1421 1422 nvkm_wr32(device, 0x41a180, 0x01000000); 1423 for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) { 1424 if ((i & 0x3f) == 0) 1425 nvkm_wr32(device, 0x41a188, i >> 6); 1426 nvkm_wr32(device, 0x41a184, oclass->gpccs.ucode->code.data[i]); 1427 } 1428 nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); 1429 1430 /* load register lists */ 1431 gf100_gr_init_csdata(gr, cclass->hub, 0x409000, 0x000, 0x000000); 1432 gf100_gr_init_csdata(gr, cclass->gpc, 0x41a000, 0x000, 0x418000); 1433 gf100_gr_init_csdata(gr, cclass->tpc, 0x41a000, 0x004, 0x419800); 1434 gf100_gr_init_csdata(gr, cclass->ppc, 0x41a000, 0x008, 0x41be00); 1435 1436 /* start HUB ucode running, it'll init the GPCs */ 1437 nvkm_wr32(device, 0x40910c, 0x00000000); 1438 nvkm_wr32(device, 0x409100, 0x00000002); 1439 if (nvkm_msec(device, 2000, 1440 if (nvkm_rd32(device, 0x409800) & 0x80000000) 1441 break; 1442 ) < 0) { 1443 gf100_gr_ctxctl_debug(gr); 1444 return -EBUSY; 1445 } 1446 1447 gr->size = nvkm_rd32(device, 0x409804); 1448 if (gr->data == NULL) { 1449 int ret = gf100_grctx_generate(gr); 1450 if (ret) { 1451 nv_error(gr, "failed to construct context\n"); 1452 return ret; 1453 } 1454 } 1455 1456 return 0; 1457 } 1458 1459 int 1460 gf100_gr_init(struct nvkm_object *object) 1461 { 1462 struct gf100_gr *gr = (void *)object; 1463 struct nvkm_device *device = gr->base.engine.subdev.device; 1464 struct gf100_gr_oclass *oclass = (void *)object->oclass; 1465 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); 1466 u32 data[TPC_MAX / 8] = {}; 1467 u8 tpcnr[GPC_MAX]; 1468 int gpc, tpc, rop; 1469 int ret, i; 1470 1471 ret = nvkm_gr_init(&gr->base); 1472 if (ret) 1473 return ret; 1474 1475 nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); 1476 nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000); 1477 nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000); 1478 nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000); 1479 nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); 1480 nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); 1481 nvkm_wr32(device, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8); 1482 nvkm_wr32(device, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8); 1483 1484 gf100_gr_mmio(gr, oclass->mmio); 1485 1486 memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); 1487 for (i = 0, gpc = -1; i < gr->tpc_total; i++) { 1488 do { 1489 gpc = (gpc + 1) % gr->gpc_nr; 1490 } while (!tpcnr[gpc]); 1491 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; 1492 1493 data[i / 8] |= tpc << ((i % 8) * 4); 1494 } 1495 1496 nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); 1497 nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); 1498 nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); 1499 nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); 1500 1501 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 1502 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), 1503 gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); 1504 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | 1505 gr->tpc_total); 1506 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); 1507 } 1508 1509 if (nv_device(gr)->chipset != 0xd7) 1510 nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); 1511 else 1512 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); 1513 1514 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); 1515 1516 nvkm_wr32(device, 0x400500, 0x00010001); 1517 1518 nvkm_wr32(device, 0x400100, 0xffffffff); 1519 nvkm_wr32(device, 0x40013c, 0xffffffff); 1520 1521 nvkm_wr32(device, 0x409c24, 0x000f0000); 1522 nvkm_wr32(device, 0x404000, 0xc0000000); 1523 nvkm_wr32(device, 0x404600, 0xc0000000); 1524 nvkm_wr32(device, 0x408030, 0xc0000000); 1525 nvkm_wr32(device, 0x40601c, 0xc0000000); 1526 nvkm_wr32(device, 0x404490, 0xc0000000); 1527 nvkm_wr32(device, 0x406018, 0xc0000000); 1528 nvkm_wr32(device, 0x405840, 0xc0000000); 1529 nvkm_wr32(device, 0x405844, 0x00ffffff); 1530 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); 1531 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); 1532 1533 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 1534 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); 1535 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); 1536 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); 1537 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); 1538 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { 1539 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); 1540 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); 1541 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); 1542 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); 1543 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); 1544 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); 1545 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); 1546 } 1547 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); 1548 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); 1549 } 1550 1551 for (rop = 0; rop < gr->rop_nr; rop++) { 1552 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); 1553 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); 1554 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); 1555 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); 1556 } 1557 1558 nvkm_wr32(device, 0x400108, 0xffffffff); 1559 nvkm_wr32(device, 0x400138, 0xffffffff); 1560 nvkm_wr32(device, 0x400118, 0xffffffff); 1561 nvkm_wr32(device, 0x400130, 0xffffffff); 1562 nvkm_wr32(device, 0x40011c, 0xffffffff); 1563 nvkm_wr32(device, 0x400134, 0xffffffff); 1564 1565 nvkm_wr32(device, 0x400054, 0x34ce3464); 1566 1567 gf100_gr_zbc_init(gr); 1568 1569 return gf100_gr_init_ctxctl(gr); 1570 } 1571 1572 void 1573 gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) 1574 { 1575 kfree(fuc->data); 1576 fuc->data = NULL; 1577 } 1578 1579 int 1580 gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, 1581 struct gf100_gr_fuc *fuc) 1582 { 1583 struct nvkm_device *device = nv_device(gr); 1584 const struct firmware *fw; 1585 char f[64]; 1586 char cname[16]; 1587 int ret; 1588 int i; 1589 1590 /* Convert device name to lowercase */ 1591 strncpy(cname, device->cname, sizeof(cname)); 1592 cname[sizeof(cname) - 1] = '\0'; 1593 i = strlen(cname); 1594 while (i) { 1595 --i; 1596 cname[i] = tolower(cname[i]); 1597 } 1598 1599 snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); 1600 ret = request_firmware(&fw, f, nv_device_base(device)); 1601 if (ret) { 1602 nv_error(gr, "failed to load %s\n", fwname); 1603 return ret; 1604 } 1605 1606 fuc->size = fw->size; 1607 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); 1608 release_firmware(fw); 1609 return (fuc->data != NULL) ? 0 : -ENOMEM; 1610 } 1611 1612 void 1613 gf100_gr_dtor(struct nvkm_object *object) 1614 { 1615 struct gf100_gr *gr = (void *)object; 1616 1617 kfree(gr->data); 1618 1619 gf100_gr_dtor_fw(&gr->fuc409c); 1620 gf100_gr_dtor_fw(&gr->fuc409d); 1621 gf100_gr_dtor_fw(&gr->fuc41ac); 1622 gf100_gr_dtor_fw(&gr->fuc41ad); 1623 1624 nvkm_gpuobj_ref(NULL, &gr->unk4188b8); 1625 nvkm_gpuobj_ref(NULL, &gr->unk4188b4); 1626 1627 nvkm_gr_destroy(&gr->base); 1628 } 1629 1630 int 1631 gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 1632 struct nvkm_oclass *bclass, void *data, u32 size, 1633 struct nvkm_object **pobject) 1634 { 1635 struct gf100_gr_oclass *oclass = (void *)bclass; 1636 struct nvkm_device *device = nv_device(parent); 1637 struct gf100_gr *gr; 1638 bool use_ext_fw, enable; 1639 int ret, i, j; 1640 1641 use_ext_fw = nvkm_boolopt(device->cfgopt, "NvGrUseFW", 1642 oclass->fecs.ucode == NULL); 1643 enable = use_ext_fw || oclass->fecs.ucode != NULL; 1644 1645 ret = nvkm_gr_create(parent, engine, bclass, enable, &gr); 1646 *pobject = nv_object(gr); 1647 if (ret) 1648 return ret; 1649 1650 nv_subdev(gr)->unit = 0x08001000; 1651 nv_subdev(gr)->intr = gf100_gr_intr; 1652 1653 gr->base.units = gf100_gr_units; 1654 1655 if (use_ext_fw) { 1656 nv_info(gr, "using external firmware\n"); 1657 if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || 1658 gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || 1659 gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || 1660 gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) 1661 return -ENODEV; 1662 gr->firmware = true; 1663 } 1664 1665 ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x1000, 256, 0, 1666 &gr->unk4188b4); 1667 if (ret) 1668 return ret; 1669 1670 ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x1000, 256, 0, 1671 &gr->unk4188b8); 1672 if (ret) 1673 return ret; 1674 1675 for (i = 0; i < 0x1000; i += 4) { 1676 nv_wo32(gr->unk4188b4, i, 0x00000010); 1677 nv_wo32(gr->unk4188b8, i, 0x00000010); 1678 } 1679 1680 gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; 1681 gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; 1682 for (i = 0; i < gr->gpc_nr; i++) { 1683 gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); 1684 gr->tpc_total += gr->tpc_nr[i]; 1685 gr->ppc_nr[i] = oclass->ppc_nr; 1686 for (j = 0; j < gr->ppc_nr[i]; j++) { 1687 u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); 1688 gr->ppc_tpc_nr[i][j] = hweight8(mask); 1689 } 1690 } 1691 1692 /*XXX: these need figuring out... though it might not even matter */ 1693 switch (nv_device(gr)->chipset) { 1694 case 0xc0: 1695 if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ 1696 gr->magic_not_rop_nr = 0x07; 1697 } else 1698 if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ 1699 gr->magic_not_rop_nr = 0x05; 1700 } else 1701 if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ 1702 gr->magic_not_rop_nr = 0x06; 1703 } 1704 break; 1705 case 0xc3: /* 450, 4/0/0/0, 2 */ 1706 gr->magic_not_rop_nr = 0x03; 1707 break; 1708 case 0xc4: /* 460, 3/4/0/0, 4 */ 1709 gr->magic_not_rop_nr = 0x01; 1710 break; 1711 case 0xc1: /* 2/0/0/0, 1 */ 1712 gr->magic_not_rop_nr = 0x01; 1713 break; 1714 case 0xc8: /* 4/4/3/4, 5 */ 1715 gr->magic_not_rop_nr = 0x06; 1716 break; 1717 case 0xce: /* 4/4/0/0, 4 */ 1718 gr->magic_not_rop_nr = 0x03; 1719 break; 1720 case 0xcf: /* 4/0/0/0, 3 */ 1721 gr->magic_not_rop_nr = 0x03; 1722 break; 1723 case 0xd7: 1724 case 0xd9: /* 1/0/0/0, 1 */ 1725 case 0xea: /* gk20a */ 1726 case 0x12b: /* gm20b */ 1727 gr->magic_not_rop_nr = 0x01; 1728 break; 1729 } 1730 1731 nv_engine(gr)->cclass = *oclass->cclass; 1732 nv_engine(gr)->sclass = oclass->sclass; 1733 return 0; 1734 } 1735 1736 #include "fuc/hubgf100.fuc3.h" 1737 1738 struct gf100_gr_ucode 1739 gf100_gr_fecs_ucode = { 1740 .code.data = gf100_grhub_code, 1741 .code.size = sizeof(gf100_grhub_code), 1742 .data.data = gf100_grhub_data, 1743 .data.size = sizeof(gf100_grhub_data), 1744 }; 1745 1746 #include "fuc/gpcgf100.fuc3.h" 1747 1748 struct gf100_gr_ucode 1749 gf100_gr_gpccs_ucode = { 1750 .code.data = gf100_grgpc_code, 1751 .code.size = sizeof(gf100_grgpc_code), 1752 .data.data = gf100_grgpc_data, 1753 .data.size = sizeof(gf100_grgpc_data), 1754 }; 1755 1756 struct nvkm_oclass * 1757 gf100_gr_oclass = &(struct gf100_gr_oclass) { 1758 .base.handle = NV_ENGINE(GR, 0xc0), 1759 .base.ofuncs = &(struct nvkm_ofuncs) { 1760 .ctor = gf100_gr_ctor, 1761 .dtor = gf100_gr_dtor, 1762 .init = gf100_gr_init, 1763 .fini = _nvkm_gr_fini, 1764 }, 1765 .cclass = &gf100_grctx_oclass, 1766 .sclass = gf100_gr_sclass, 1767 .mmio = gf100_gr_pack_mmio, 1768 .fecs.ucode = &gf100_gr_fecs_ucode, 1769 .gpccs.ucode = &gf100_gr_gpccs_ucode, 1770 }.base; 1771