1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "gf100.h" 25 #include "ctxgf100.h" 26 #include "fuc/os.h" 27 28 #include <core/client.h> 29 #include <core/firmware.h> 30 #include <core/option.h> 31 #include <subdev/acr.h> 32 #include <subdev/fb.h> 33 #include <subdev/mc.h> 34 #include <subdev/pmu.h> 35 #include <subdev/therm.h> 36 #include <subdev/timer.h> 37 #include <engine/fifo.h> 38 39 #include <nvif/class.h> 40 #include <nvif/cl9097.h> 41 #include <nvif/if900d.h> 42 #include <nvif/unpack.h> 43 44 /******************************************************************************* 45 * Zero Bandwidth Clear 46 ******************************************************************************/ 47 48 static void 49 gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) 50 { 51 struct nvkm_device *device = gr->base.engine.subdev.device; 52 if (gr->zbc_color[zbc].format) { 53 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); 54 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); 55 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); 56 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); 57 } 58 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); 59 nvkm_wr32(device, 0x405820, zbc); 60 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ 61 } 62 63 static int 64 gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, 65 const u32 ds[4], const u32 l2[4]) 66 { 67 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; 68 int zbc = -ENOSPC, i; 69 70 for (i = ltc->zbc_color_min; i <= ltc->zbc_color_max; i++) { 71 if (gr->zbc_color[i].format) { 72 if (gr->zbc_color[i].format != format) 73 continue; 74 if (memcmp(gr->zbc_color[i].ds, ds, sizeof( 75 gr->zbc_color[i].ds))) 76 continue; 77 if (memcmp(gr->zbc_color[i].l2, l2, sizeof( 78 gr->zbc_color[i].l2))) { 79 WARN_ON(1); 80 return -EINVAL; 81 } 82 return i; 83 } else { 84 zbc = (zbc < 0) ? i : zbc; 85 } 86 } 87 88 if (zbc < 0) 89 return zbc; 90 91 memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); 92 memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); 93 gr->zbc_color[zbc].format = format; 94 nvkm_ltc_zbc_color_get(ltc, zbc, l2); 95 gr->func->zbc->clear_color(gr, zbc); 96 return zbc; 97 } 98 99 static void 100 gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) 101 { 102 struct nvkm_device *device = gr->base.engine.subdev.device; 103 if (gr->zbc_depth[zbc].format) 104 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); 105 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); 106 nvkm_wr32(device, 0x405820, zbc); 107 nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ 108 } 109 110 static int 111 gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, 112 const u32 ds, const u32 l2) 113 { 114 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; 115 int zbc = -ENOSPC, i; 116 117 for (i = ltc->zbc_depth_min; i <= ltc->zbc_depth_max; i++) { 118 if (gr->zbc_depth[i].format) { 119 if (gr->zbc_depth[i].format != format) 120 continue; 121 if (gr->zbc_depth[i].ds != ds) 122 continue; 123 if (gr->zbc_depth[i].l2 != l2) { 124 WARN_ON(1); 125 return -EINVAL; 126 } 127 return i; 128 } else { 129 zbc = (zbc < 0) ? i : zbc; 130 } 131 } 132 133 if (zbc < 0) 134 return zbc; 135 136 gr->zbc_depth[zbc].format = format; 137 gr->zbc_depth[zbc].ds = ds; 138 gr->zbc_depth[zbc].l2 = l2; 139 nvkm_ltc_zbc_depth_get(ltc, zbc, l2); 140 gr->func->zbc->clear_depth(gr, zbc); 141 return zbc; 142 } 143 144 const struct gf100_gr_func_zbc 145 gf100_gr_zbc = { 146 .clear_color = gf100_gr_zbc_clear_color, 147 .clear_depth = gf100_gr_zbc_clear_depth, 148 }; 149 150 /******************************************************************************* 151 * Graphics object classes 152 ******************************************************************************/ 153 #define gf100_gr_object(p) container_of((p), struct gf100_gr_object, object) 154 155 struct gf100_gr_object { 156 struct nvkm_object object; 157 struct gf100_gr_chan *chan; 158 }; 159 160 static int 161 gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) 162 { 163 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); 164 union { 165 struct fermi_a_zbc_color_v0 v0; 166 } *args = data; 167 int ret = -ENOSYS; 168 169 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { 170 switch (args->v0.format) { 171 case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: 172 case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: 173 case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32: 174 case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16: 175 case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16: 176 case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16: 177 case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16: 178 case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16: 179 case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8: 180 case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8: 181 case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10: 182 case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10: 183 case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8: 184 case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8: 185 case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8: 186 case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8: 187 case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: 188 case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: 189 case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: 190 ret = gf100_gr_zbc_color_get(gr, args->v0.format, 191 args->v0.ds, 192 args->v0.l2); 193 if (ret >= 0) { 194 args->v0.index = ret; 195 return 0; 196 } 197 break; 198 default: 199 return -EINVAL; 200 } 201 } 202 203 return ret; 204 } 205 206 static int 207 gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) 208 { 209 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); 210 union { 211 struct fermi_a_zbc_depth_v0 v0; 212 } *args = data; 213 int ret = -ENOSYS; 214 215 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { 216 switch (args->v0.format) { 217 case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: 218 ret = gf100_gr_zbc_depth_get(gr, args->v0.format, 219 args->v0.ds, 220 args->v0.l2); 221 return (ret >= 0) ? 0 : -ENOSPC; 222 default: 223 return -EINVAL; 224 } 225 } 226 227 return ret; 228 } 229 230 static int 231 gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) 232 { 233 nvif_ioctl(object, "fermi mthd %08x\n", mthd); 234 switch (mthd) { 235 case FERMI_A_ZBC_COLOR: 236 return gf100_fermi_mthd_zbc_color(object, data, size); 237 case FERMI_A_ZBC_DEPTH: 238 return gf100_fermi_mthd_zbc_depth(object, data, size); 239 default: 240 break; 241 } 242 return -EINVAL; 243 } 244 245 const struct nvkm_object_func 246 gf100_fermi = { 247 .mthd = gf100_fermi_mthd, 248 }; 249 250 static void 251 gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data) 252 { 253 nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000); 254 nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000); 255 } 256 257 static bool 258 gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data) 259 { 260 switch (class & 0x00ff) { 261 case 0x97: 262 case 0xc0: 263 switch (mthd) { 264 case 0x1528: 265 gf100_gr_mthd_set_shader_exceptions(device, data); 266 return true; 267 default: 268 break; 269 } 270 break; 271 default: 272 break; 273 } 274 return false; 275 } 276 277 static const struct nvkm_object_func 278 gf100_gr_object_func = { 279 }; 280 281 static int 282 gf100_gr_object_new(const struct nvkm_oclass *oclass, void *data, u32 size, 283 struct nvkm_object **pobject) 284 { 285 struct gf100_gr_chan *chan = gf100_gr_chan(oclass->parent); 286 struct gf100_gr_object *object; 287 288 if (!(object = kzalloc(sizeof(*object), GFP_KERNEL))) 289 return -ENOMEM; 290 *pobject = &object->object; 291 292 nvkm_object_ctor(oclass->base.func ? oclass->base.func : 293 &gf100_gr_object_func, oclass, &object->object); 294 object->chan = chan; 295 return 0; 296 } 297 298 static int 299 gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass) 300 { 301 struct gf100_gr *gr = gf100_gr(base); 302 int c = 0; 303 304 while (gr->func->sclass[c].oclass) { 305 if (c++ == index) { 306 *sclass = gr->func->sclass[index]; 307 sclass->ctor = gf100_gr_object_new; 308 return index; 309 } 310 } 311 312 return c; 313 } 314 315 /******************************************************************************* 316 * PGRAPH context 317 ******************************************************************************/ 318 319 static int 320 gf100_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, 321 int align, struct nvkm_gpuobj **pgpuobj) 322 { 323 struct gf100_gr_chan *chan = gf100_gr_chan(object); 324 struct gf100_gr *gr = chan->gr; 325 int ret, i; 326 327 ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, 328 align, false, parent, pgpuobj); 329 if (ret) 330 return ret; 331 332 nvkm_kmap(*pgpuobj); 333 for (i = 0; i < gr->size; i += 4) 334 nvkm_wo32(*pgpuobj, i, gr->data[i / 4]); 335 336 if (!gr->firmware) { 337 nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2); 338 nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma->addr >> 8); 339 } else { 340 nvkm_wo32(*pgpuobj, 0xf4, 0); 341 nvkm_wo32(*pgpuobj, 0xf8, 0); 342 nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2); 343 nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma->addr)); 344 nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma->addr)); 345 nvkm_wo32(*pgpuobj, 0x1c, 1); 346 nvkm_wo32(*pgpuobj, 0x20, 0); 347 nvkm_wo32(*pgpuobj, 0x28, 0); 348 nvkm_wo32(*pgpuobj, 0x2c, 0); 349 } 350 nvkm_done(*pgpuobj); 351 return 0; 352 } 353 354 static void * 355 gf100_gr_chan_dtor(struct nvkm_object *object) 356 { 357 struct gf100_gr_chan *chan = gf100_gr_chan(object); 358 359 nvkm_vmm_put(chan->vmm, &chan->mmio_vma); 360 nvkm_memory_unref(&chan->mmio); 361 362 nvkm_vmm_put(chan->vmm, &chan->attrib_cb); 363 nvkm_vmm_put(chan->vmm, &chan->unknown); 364 nvkm_vmm_put(chan->vmm, &chan->bundle_cb); 365 nvkm_vmm_put(chan->vmm, &chan->pagepool); 366 nvkm_vmm_unref(&chan->vmm); 367 return chan; 368 } 369 370 static const struct nvkm_object_func 371 gf100_gr_chan = { 372 .dtor = gf100_gr_chan_dtor, 373 .bind = gf100_gr_chan_bind, 374 }; 375 376 static int 377 gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, 378 const struct nvkm_oclass *oclass, 379 struct nvkm_object **pobject) 380 { 381 struct gf100_gr *gr = gf100_gr(base); 382 struct gf100_gr_chan *chan; 383 struct gf100_vmm_map_v0 args = { .priv = 1 }; 384 struct nvkm_device *device = gr->base.engine.subdev.device; 385 int ret; 386 387 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) 388 return -ENOMEM; 389 nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object); 390 chan->gr = gr; 391 chan->vmm = nvkm_vmm_ref(fifoch->vmm); 392 *pobject = &chan->object; 393 394 /* Map pagepool. */ 395 ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->pagepool), &chan->pagepool); 396 if (ret) 397 return ret; 398 399 ret = nvkm_memory_map(gr->pagepool, 0, chan->vmm, chan->pagepool, &args, sizeof(args)); 400 if (ret) 401 return ret; 402 403 /* Map bundle circular buffer. */ 404 ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->bundle_cb), &chan->bundle_cb); 405 if (ret) 406 return ret; 407 408 ret = nvkm_memory_map(gr->bundle_cb, 0, chan->vmm, chan->bundle_cb, &args, sizeof(args)); 409 if (ret) 410 return ret; 411 412 /* Map attribute circular buffer. */ 413 ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->attrib_cb), &chan->attrib_cb); 414 if (ret) 415 return ret; 416 417 if (device->card_type < GP100) { 418 ret = nvkm_memory_map(gr->attrib_cb, 0, chan->vmm, chan->attrib_cb, NULL, 0); 419 if (ret) 420 return ret; 421 } else { 422 ret = nvkm_memory_map(gr->attrib_cb, 0, chan->vmm, chan->attrib_cb, 423 &args, sizeof(args));; 424 if (ret) 425 return ret; 426 } 427 428 /* Map some context buffer of unknown purpose. */ 429 if (gr->func->grctx->unknown_size) { 430 ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->unknown), &chan->unknown); 431 if (ret) 432 return ret; 433 434 ret = nvkm_memory_map(gr->unknown, 0, chan->vmm, chan->unknown, 435 &args, sizeof(args)); 436 if (ret) 437 return ret; 438 } 439 440 /* Generate golden context image. */ 441 mutex_lock(&gr->fecs.mutex); 442 if (gr->data == NULL) { 443 ret = gf100_grctx_generate(gr, chan, fifoch->inst); 444 if (ret) { 445 nvkm_error(&base->engine.subdev, "failed to construct context\n"); 446 return ret; 447 } 448 } 449 mutex_unlock(&gr->fecs.mutex); 450 451 /* allocate memory for a "mmio list" buffer that's used by the HUB 452 * fuc to modify some per-context register settings on first load 453 * of the context. 454 */ 455 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100, 456 false, &chan->mmio); 457 if (ret) 458 return ret; 459 460 ret = nvkm_vmm_get(fifoch->vmm, 12, 0x1000, &chan->mmio_vma); 461 if (ret) 462 return ret; 463 464 ret = nvkm_memory_map(chan->mmio, 0, fifoch->vmm, 465 chan->mmio_vma, &args, sizeof(args)); 466 if (ret) 467 return ret; 468 469 /* finally, fill in the mmio list and point the context at it */ 470 nvkm_kmap(chan->mmio); 471 gr->func->grctx->pagepool(chan, chan->pagepool->addr); 472 gr->func->grctx->bundle(chan, chan->bundle_cb->addr, gr->func->grctx->bundle_size); 473 gr->func->grctx->attrib_cb(chan, chan->attrib_cb->addr, gr->func->grctx->attrib_cb_size(gr)); 474 gr->func->grctx->attrib(chan); 475 if (gr->func->grctx->patch_ltc) 476 gr->func->grctx->patch_ltc(chan); 477 if (gr->func->grctx->unknown_size) 478 gr->func->grctx->unknown(chan, chan->unknown->addr, gr->func->grctx->unknown_size); 479 nvkm_done(chan->mmio); 480 return 0; 481 } 482 483 /******************************************************************************* 484 * PGRAPH register lists 485 ******************************************************************************/ 486 487 const struct gf100_gr_init 488 gf100_gr_init_main_0[] = { 489 { 0x400080, 1, 0x04, 0x003083c2 }, 490 { 0x400088, 1, 0x04, 0x00006fe7 }, 491 { 0x40008c, 1, 0x04, 0x00000000 }, 492 { 0x400090, 1, 0x04, 0x00000030 }, 493 { 0x40013c, 1, 0x04, 0x013901f7 }, 494 { 0x400140, 1, 0x04, 0x00000100 }, 495 { 0x400144, 1, 0x04, 0x00000000 }, 496 { 0x400148, 1, 0x04, 0x00000110 }, 497 { 0x400138, 1, 0x04, 0x00000000 }, 498 { 0x400130, 2, 0x04, 0x00000000 }, 499 { 0x400124, 1, 0x04, 0x00000002 }, 500 {} 501 }; 502 503 const struct gf100_gr_init 504 gf100_gr_init_fe_0[] = { 505 { 0x40415c, 1, 0x04, 0x00000000 }, 506 { 0x404170, 1, 0x04, 0x00000000 }, 507 {} 508 }; 509 510 const struct gf100_gr_init 511 gf100_gr_init_pri_0[] = { 512 { 0x404488, 2, 0x04, 0x00000000 }, 513 {} 514 }; 515 516 const struct gf100_gr_init 517 gf100_gr_init_rstr2d_0[] = { 518 { 0x407808, 1, 0x04, 0x00000000 }, 519 {} 520 }; 521 522 const struct gf100_gr_init 523 gf100_gr_init_pd_0[] = { 524 { 0x406024, 1, 0x04, 0x00000000 }, 525 {} 526 }; 527 528 const struct gf100_gr_init 529 gf100_gr_init_ds_0[] = { 530 { 0x405844, 1, 0x04, 0x00ffffff }, 531 { 0x405850, 1, 0x04, 0x00000000 }, 532 { 0x405908, 1, 0x04, 0x00000000 }, 533 {} 534 }; 535 536 const struct gf100_gr_init 537 gf100_gr_init_scc_0[] = { 538 { 0x40803c, 1, 0x04, 0x00000000 }, 539 {} 540 }; 541 542 const struct gf100_gr_init 543 gf100_gr_init_prop_0[] = { 544 { 0x4184a0, 1, 0x04, 0x00000000 }, 545 {} 546 }; 547 548 const struct gf100_gr_init 549 gf100_gr_init_gpc_unk_0[] = { 550 { 0x418604, 1, 0x04, 0x00000000 }, 551 { 0x418680, 1, 0x04, 0x00000000 }, 552 { 0x418714, 1, 0x04, 0x80000000 }, 553 { 0x418384, 1, 0x04, 0x00000000 }, 554 {} 555 }; 556 557 const struct gf100_gr_init 558 gf100_gr_init_setup_0[] = { 559 { 0x418814, 3, 0x04, 0x00000000 }, 560 {} 561 }; 562 563 const struct gf100_gr_init 564 gf100_gr_init_crstr_0[] = { 565 { 0x418b04, 1, 0x04, 0x00000000 }, 566 {} 567 }; 568 569 const struct gf100_gr_init 570 gf100_gr_init_setup_1[] = { 571 { 0x4188c8, 1, 0x04, 0x80000000 }, 572 { 0x4188cc, 1, 0x04, 0x00000000 }, 573 { 0x4188d0, 1, 0x04, 0x00010000 }, 574 { 0x4188d4, 1, 0x04, 0x00000001 }, 575 {} 576 }; 577 578 const struct gf100_gr_init 579 gf100_gr_init_zcull_0[] = { 580 { 0x418910, 1, 0x04, 0x00010001 }, 581 { 0x418914, 1, 0x04, 0x00000301 }, 582 { 0x418918, 1, 0x04, 0x00800000 }, 583 { 0x418980, 1, 0x04, 0x77777770 }, 584 { 0x418984, 3, 0x04, 0x77777777 }, 585 {} 586 }; 587 588 const struct gf100_gr_init 589 gf100_gr_init_gpm_0[] = { 590 { 0x418c04, 1, 0x04, 0x00000000 }, 591 { 0x418c88, 1, 0x04, 0x00000000 }, 592 {} 593 }; 594 595 const struct gf100_gr_init 596 gf100_gr_init_gpc_unk_1[] = { 597 { 0x418d00, 1, 0x04, 0x00000000 }, 598 { 0x418f08, 1, 0x04, 0x00000000 }, 599 { 0x418e00, 1, 0x04, 0x00000050 }, 600 { 0x418e08, 1, 0x04, 0x00000000 }, 601 {} 602 }; 603 604 const struct gf100_gr_init 605 gf100_gr_init_gcc_0[] = { 606 { 0x41900c, 1, 0x04, 0x00000000 }, 607 { 0x419018, 1, 0x04, 0x00000000 }, 608 {} 609 }; 610 611 const struct gf100_gr_init 612 gf100_gr_init_tpccs_0[] = { 613 { 0x419d08, 2, 0x04, 0x00000000 }, 614 { 0x419d10, 1, 0x04, 0x00000014 }, 615 {} 616 }; 617 618 const struct gf100_gr_init 619 gf100_gr_init_tex_0[] = { 620 { 0x419ab0, 1, 0x04, 0x00000000 }, 621 { 0x419ab8, 1, 0x04, 0x000000e7 }, 622 { 0x419abc, 2, 0x04, 0x00000000 }, 623 {} 624 }; 625 626 const struct gf100_gr_init 627 gf100_gr_init_pe_0[] = { 628 { 0x41980c, 3, 0x04, 0x00000000 }, 629 { 0x419844, 1, 0x04, 0x00000000 }, 630 { 0x41984c, 1, 0x04, 0x00005bc5 }, 631 { 0x419850, 4, 0x04, 0x00000000 }, 632 {} 633 }; 634 635 const struct gf100_gr_init 636 gf100_gr_init_l1c_0[] = { 637 { 0x419c98, 1, 0x04, 0x00000000 }, 638 { 0x419ca8, 1, 0x04, 0x80000000 }, 639 { 0x419cb4, 1, 0x04, 0x00000000 }, 640 { 0x419cb8, 1, 0x04, 0x00008bf4 }, 641 { 0x419cbc, 1, 0x04, 0x28137606 }, 642 { 0x419cc0, 2, 0x04, 0x00000000 }, 643 {} 644 }; 645 646 const struct gf100_gr_init 647 gf100_gr_init_wwdx_0[] = { 648 { 0x419bd4, 1, 0x04, 0x00800000 }, 649 { 0x419bdc, 1, 0x04, 0x00000000 }, 650 {} 651 }; 652 653 const struct gf100_gr_init 654 gf100_gr_init_tpccs_1[] = { 655 { 0x419d2c, 1, 0x04, 0x00000000 }, 656 {} 657 }; 658 659 const struct gf100_gr_init 660 gf100_gr_init_mpc_0[] = { 661 { 0x419c0c, 1, 0x04, 0x00000000 }, 662 {} 663 }; 664 665 static const struct gf100_gr_init 666 gf100_gr_init_sm_0[] = { 667 { 0x419e00, 1, 0x04, 0x00000000 }, 668 { 0x419ea0, 1, 0x04, 0x00000000 }, 669 { 0x419ea4, 1, 0x04, 0x00000100 }, 670 { 0x419ea8, 1, 0x04, 0x00001100 }, 671 { 0x419eac, 1, 0x04, 0x11100702 }, 672 { 0x419eb0, 1, 0x04, 0x00000003 }, 673 { 0x419eb4, 4, 0x04, 0x00000000 }, 674 { 0x419ec8, 1, 0x04, 0x06060618 }, 675 { 0x419ed0, 1, 0x04, 0x0eff0e38 }, 676 { 0x419ed4, 1, 0x04, 0x011104f1 }, 677 { 0x419edc, 1, 0x04, 0x00000000 }, 678 { 0x419f00, 1, 0x04, 0x00000000 }, 679 { 0x419f2c, 1, 0x04, 0x00000000 }, 680 {} 681 }; 682 683 const struct gf100_gr_init 684 gf100_gr_init_be_0[] = { 685 { 0x40880c, 1, 0x04, 0x00000000 }, 686 { 0x408910, 9, 0x04, 0x00000000 }, 687 { 0x408950, 1, 0x04, 0x00000000 }, 688 { 0x408954, 1, 0x04, 0x0000ffff }, 689 { 0x408984, 1, 0x04, 0x00000000 }, 690 { 0x408988, 1, 0x04, 0x08040201 }, 691 { 0x40898c, 1, 0x04, 0x80402010 }, 692 {} 693 }; 694 695 const struct gf100_gr_init 696 gf100_gr_init_fe_1[] = { 697 { 0x4040f0, 1, 0x04, 0x00000000 }, 698 {} 699 }; 700 701 const struct gf100_gr_init 702 gf100_gr_init_pe_1[] = { 703 { 0x419880, 1, 0x04, 0x00000002 }, 704 {} 705 }; 706 707 static const struct gf100_gr_pack 708 gf100_gr_pack_mmio[] = { 709 { gf100_gr_init_main_0 }, 710 { gf100_gr_init_fe_0 }, 711 { gf100_gr_init_pri_0 }, 712 { gf100_gr_init_rstr2d_0 }, 713 { gf100_gr_init_pd_0 }, 714 { gf100_gr_init_ds_0 }, 715 { gf100_gr_init_scc_0 }, 716 { gf100_gr_init_prop_0 }, 717 { gf100_gr_init_gpc_unk_0 }, 718 { gf100_gr_init_setup_0 }, 719 { gf100_gr_init_crstr_0 }, 720 { gf100_gr_init_setup_1 }, 721 { gf100_gr_init_zcull_0 }, 722 { gf100_gr_init_gpm_0 }, 723 { gf100_gr_init_gpc_unk_1 }, 724 { gf100_gr_init_gcc_0 }, 725 { gf100_gr_init_tpccs_0 }, 726 { gf100_gr_init_tex_0 }, 727 { gf100_gr_init_pe_0 }, 728 { gf100_gr_init_l1c_0 }, 729 { gf100_gr_init_wwdx_0 }, 730 { gf100_gr_init_tpccs_1 }, 731 { gf100_gr_init_mpc_0 }, 732 { gf100_gr_init_sm_0 }, 733 { gf100_gr_init_be_0 }, 734 { gf100_gr_init_fe_1 }, 735 { gf100_gr_init_pe_1 }, 736 {} 737 }; 738 739 /******************************************************************************* 740 * PGRAPH engine/subdev functions 741 ******************************************************************************/ 742 743 static u32 744 gf100_gr_ctxsw_inst(struct nvkm_gr *gr) 745 { 746 return nvkm_rd32(gr->engine.subdev.device, 0x409b00); 747 } 748 749 static int 750 gf100_gr_fecs_ctrl_ctxsw(struct gf100_gr *gr, u32 mthd) 751 { 752 struct nvkm_device *device = gr->base.engine.subdev.device; 753 754 nvkm_wr32(device, 0x409804, 0xffffffff); 755 nvkm_wr32(device, 0x409800, 0x00000000); 756 nvkm_wr32(device, 0x409500, 0xffffffff); 757 nvkm_wr32(device, 0x409504, mthd); 758 nvkm_msec(device, 2000, 759 u32 stat = nvkm_rd32(device, 0x409804); 760 if (stat == 0x00000002) 761 return -EIO; 762 if (stat == 0x00000001) 763 return 0; 764 ); 765 766 return -ETIMEDOUT; 767 } 768 769 static int 770 gf100_gr_fecs_start_ctxsw(struct nvkm_gr *base) 771 { 772 struct gf100_gr *gr = gf100_gr(base); 773 int ret = 0; 774 775 mutex_lock(&gr->fecs.mutex); 776 if (!--gr->fecs.disable) { 777 if (WARN_ON(ret = gf100_gr_fecs_ctrl_ctxsw(gr, 0x39))) 778 gr->fecs.disable++; 779 } 780 mutex_unlock(&gr->fecs.mutex); 781 return ret; 782 } 783 784 static int 785 gf100_gr_fecs_stop_ctxsw(struct nvkm_gr *base) 786 { 787 struct gf100_gr *gr = gf100_gr(base); 788 int ret = 0; 789 790 mutex_lock(&gr->fecs.mutex); 791 if (!gr->fecs.disable++) { 792 if (WARN_ON(ret = gf100_gr_fecs_ctrl_ctxsw(gr, 0x38))) 793 gr->fecs.disable--; 794 } 795 mutex_unlock(&gr->fecs.mutex); 796 return ret; 797 } 798 799 static int 800 gf100_gr_fecs_halt_pipeline(struct gf100_gr *gr) 801 { 802 int ret = 0; 803 804 if (gr->firmware) { 805 mutex_lock(&gr->fecs.mutex); 806 ret = gf100_gr_fecs_ctrl_ctxsw(gr, 0x04); 807 mutex_unlock(&gr->fecs.mutex); 808 } 809 810 return ret; 811 } 812 813 int 814 gf100_gr_fecs_wfi_golden_save(struct gf100_gr *gr, u32 inst) 815 { 816 struct nvkm_device *device = gr->base.engine.subdev.device; 817 818 nvkm_mask(device, 0x409800, 0x00000003, 0x00000000); 819 nvkm_wr32(device, 0x409500, inst); 820 nvkm_wr32(device, 0x409504, 0x00000009); 821 nvkm_msec(device, 2000, 822 u32 stat = nvkm_rd32(device, 0x409800); 823 if (stat & 0x00000002) 824 return -EIO; 825 if (stat & 0x00000001) 826 return 0; 827 ); 828 829 return -ETIMEDOUT; 830 } 831 832 int 833 gf100_gr_fecs_bind_pointer(struct gf100_gr *gr, u32 inst) 834 { 835 struct nvkm_device *device = gr->base.engine.subdev.device; 836 837 nvkm_mask(device, 0x409800, 0x00000030, 0x00000000); 838 nvkm_wr32(device, 0x409500, inst); 839 nvkm_wr32(device, 0x409504, 0x00000003); 840 nvkm_msec(device, 2000, 841 u32 stat = nvkm_rd32(device, 0x409800); 842 if (stat & 0x00000020) 843 return -EIO; 844 if (stat & 0x00000010) 845 return 0; 846 ); 847 848 return -ETIMEDOUT; 849 } 850 851 static int 852 gf100_gr_fecs_set_reglist_virtual_address(struct gf100_gr *gr, u64 addr) 853 { 854 struct nvkm_device *device = gr->base.engine.subdev.device; 855 856 nvkm_wr32(device, 0x409810, addr >> 8); 857 nvkm_wr32(device, 0x409800, 0x00000000); 858 nvkm_wr32(device, 0x409500, 0x00000001); 859 nvkm_wr32(device, 0x409504, 0x00000032); 860 nvkm_msec(device, 2000, 861 if (nvkm_rd32(device, 0x409800) == 0x00000001) 862 return 0; 863 ); 864 865 return -ETIMEDOUT; 866 } 867 868 static int 869 gf100_gr_fecs_set_reglist_bind_instance(struct gf100_gr *gr, u32 inst) 870 { 871 struct nvkm_device *device = gr->base.engine.subdev.device; 872 873 nvkm_wr32(device, 0x409810, inst); 874 nvkm_wr32(device, 0x409800, 0x00000000); 875 nvkm_wr32(device, 0x409500, 0x00000001); 876 nvkm_wr32(device, 0x409504, 0x00000031); 877 nvkm_msec(device, 2000, 878 if (nvkm_rd32(device, 0x409800) == 0x00000001) 879 return 0; 880 ); 881 882 return -ETIMEDOUT; 883 } 884 885 static int 886 gf100_gr_fecs_discover_reglist_image_size(struct gf100_gr *gr, u32 *psize) 887 { 888 struct nvkm_device *device = gr->base.engine.subdev.device; 889 890 nvkm_wr32(device, 0x409800, 0x00000000); 891 nvkm_wr32(device, 0x409500, 0x00000001); 892 nvkm_wr32(device, 0x409504, 0x00000030); 893 nvkm_msec(device, 2000, 894 if ((*psize = nvkm_rd32(device, 0x409800))) 895 return 0; 896 ); 897 898 return -ETIMEDOUT; 899 } 900 901 static int 902 gf100_gr_fecs_elpg_bind(struct gf100_gr *gr) 903 { 904 u32 size; 905 int ret; 906 907 ret = gf100_gr_fecs_discover_reglist_image_size(gr, &size); 908 if (ret) 909 return ret; 910 911 /*XXX: We need to allocate + map the above into PMU's inst block, 912 * which which means we probably need a proper PMU before we 913 * even bother. 914 */ 915 916 ret = gf100_gr_fecs_set_reglist_bind_instance(gr, 0); 917 if (ret) 918 return ret; 919 920 return gf100_gr_fecs_set_reglist_virtual_address(gr, 0); 921 } 922 923 static int 924 gf100_gr_fecs_discover_pm_image_size(struct gf100_gr *gr, u32 *psize) 925 { 926 struct nvkm_device *device = gr->base.engine.subdev.device; 927 928 nvkm_wr32(device, 0x409800, 0x00000000); 929 nvkm_wr32(device, 0x409500, 0x00000000); 930 nvkm_wr32(device, 0x409504, 0x00000025); 931 nvkm_msec(device, 2000, 932 if ((*psize = nvkm_rd32(device, 0x409800))) 933 return 0; 934 ); 935 936 return -ETIMEDOUT; 937 } 938 939 static int 940 gf100_gr_fecs_discover_zcull_image_size(struct gf100_gr *gr, u32 *psize) 941 { 942 struct nvkm_device *device = gr->base.engine.subdev.device; 943 944 nvkm_wr32(device, 0x409800, 0x00000000); 945 nvkm_wr32(device, 0x409500, 0x00000000); 946 nvkm_wr32(device, 0x409504, 0x00000016); 947 nvkm_msec(device, 2000, 948 if ((*psize = nvkm_rd32(device, 0x409800))) 949 return 0; 950 ); 951 952 return -ETIMEDOUT; 953 } 954 955 static int 956 gf100_gr_fecs_discover_image_size(struct gf100_gr *gr, u32 *psize) 957 { 958 struct nvkm_device *device = gr->base.engine.subdev.device; 959 960 nvkm_wr32(device, 0x409800, 0x00000000); 961 nvkm_wr32(device, 0x409500, 0x00000000); 962 nvkm_wr32(device, 0x409504, 0x00000010); 963 nvkm_msec(device, 2000, 964 if ((*psize = nvkm_rd32(device, 0x409800))) 965 return 0; 966 ); 967 968 return -ETIMEDOUT; 969 } 970 971 static void 972 gf100_gr_fecs_set_watchdog_timeout(struct gf100_gr *gr, u32 timeout) 973 { 974 struct nvkm_device *device = gr->base.engine.subdev.device; 975 976 nvkm_wr32(device, 0x409800, 0x00000000); 977 nvkm_wr32(device, 0x409500, timeout); 978 nvkm_wr32(device, 0x409504, 0x00000021); 979 } 980 981 static bool 982 gf100_gr_chsw_load(struct nvkm_gr *base) 983 { 984 struct gf100_gr *gr = gf100_gr(base); 985 if (!gr->firmware) { 986 u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c); 987 if (trace & 0x00000040) 988 return true; 989 } else { 990 u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808); 991 if (mthd & 0x00080000) 992 return true; 993 } 994 return false; 995 } 996 997 int 998 gf100_gr_rops(struct gf100_gr *gr) 999 { 1000 struct nvkm_device *device = gr->base.engine.subdev.device; 1001 return (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; 1002 } 1003 1004 void 1005 gf100_gr_zbc_init(struct gf100_gr *gr) 1006 { 1007 const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1008 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 1009 const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 1010 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; 1011 const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1012 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 1013 const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 1014 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; 1015 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; 1016 int index, c = ltc->zbc_color_min, d = ltc->zbc_depth_min, s = ltc->zbc_depth_min; 1017 1018 if (!gr->zbc_color[0].format) { 1019 gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); c++; 1020 gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); c++; 1021 gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); c++; 1022 gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); c++; 1023 gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); d++; 1024 gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); d++; 1025 if (gr->func->zbc->stencil_get) { 1026 gr->func->zbc->stencil_get(gr, 1, 0x00, 0x00); s++; 1027 gr->func->zbc->stencil_get(gr, 1, 0x01, 0x01); s++; 1028 gr->func->zbc->stencil_get(gr, 1, 0xff, 0xff); s++; 1029 } 1030 } 1031 1032 for (index = c; index <= ltc->zbc_color_max; index++) 1033 gr->func->zbc->clear_color(gr, index); 1034 for (index = d; index <= ltc->zbc_depth_max; index++) 1035 gr->func->zbc->clear_depth(gr, index); 1036 1037 if (gr->func->zbc->clear_stencil) { 1038 for (index = s; index <= ltc->zbc_depth_max; index++) 1039 gr->func->zbc->clear_stencil(gr, index); 1040 } 1041 } 1042 1043 /** 1044 * Wait until GR goes idle. GR is considered idle if it is disabled by the 1045 * MC (0x200) register, or GR is not busy and a context switch is not in 1046 * progress. 1047 */ 1048 int 1049 gf100_gr_wait_idle(struct gf100_gr *gr) 1050 { 1051 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1052 struct nvkm_device *device = subdev->device; 1053 unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000); 1054 bool gr_enabled, ctxsw_active, gr_busy; 1055 1056 do { 1057 /* 1058 * required to make sure FIFO_ENGINE_STATUS (0x2640) is 1059 * up-to-date 1060 */ 1061 nvkm_rd32(device, 0x400700); 1062 1063 gr_enabled = nvkm_rd32(device, 0x200) & 0x1000; 1064 ctxsw_active = nvkm_fifo_ctxsw_in_progress(&gr->base.engine); 1065 gr_busy = nvkm_rd32(device, 0x40060c) & 0x1; 1066 1067 if (!gr_enabled || (!gr_busy && !ctxsw_active)) 1068 return 0; 1069 } while (time_before(jiffies, end_jiffies)); 1070 1071 nvkm_error(subdev, 1072 "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n", 1073 gr_enabled, ctxsw_active, gr_busy); 1074 return -EAGAIN; 1075 } 1076 1077 void 1078 gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) 1079 { 1080 struct nvkm_device *device = gr->base.engine.subdev.device; 1081 const struct gf100_gr_pack *pack; 1082 const struct gf100_gr_init *init; 1083 1084 pack_for_each_init(init, pack, p) { 1085 u32 next = init->addr + init->count * init->pitch; 1086 u32 addr = init->addr; 1087 while (addr < next) { 1088 nvkm_wr32(device, addr, init->data); 1089 addr += init->pitch; 1090 } 1091 } 1092 } 1093 1094 void 1095 gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) 1096 { 1097 struct nvkm_device *device = gr->base.engine.subdev.device; 1098 const struct gf100_gr_pack *pack; 1099 const struct gf100_gr_init *init; 1100 u32 data = 0; 1101 1102 nvkm_wr32(device, 0x400208, 0x80000000); 1103 1104 pack_for_each_init(init, pack, p) { 1105 u32 next = init->addr + init->count * init->pitch; 1106 u32 addr = init->addr; 1107 1108 if ((pack == p && init == p->init) || data != init->data) { 1109 nvkm_wr32(device, 0x400204, init->data); 1110 data = init->data; 1111 } 1112 1113 while (addr < next) { 1114 nvkm_wr32(device, 0x400200, addr); 1115 /** 1116 * Wait for GR to go idle after submitting a 1117 * GO_IDLE bundle 1118 */ 1119 if ((addr & 0xffff) == 0xe100) 1120 gf100_gr_wait_idle(gr); 1121 nvkm_msec(device, 2000, 1122 if (!(nvkm_rd32(device, 0x400700) & 0x00000004)) 1123 break; 1124 ); 1125 addr += init->pitch; 1126 } 1127 } 1128 1129 nvkm_wr32(device, 0x400208, 0x00000000); 1130 } 1131 1132 void 1133 gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) 1134 { 1135 struct nvkm_device *device = gr->base.engine.subdev.device; 1136 const struct gf100_gr_pack *pack; 1137 const struct gf100_gr_init *init; 1138 u32 data = 0; 1139 1140 pack_for_each_init(init, pack, p) { 1141 u32 ctrl = 0x80000000 | pack->type; 1142 u32 next = init->addr + init->count * init->pitch; 1143 u32 addr = init->addr; 1144 1145 if ((pack == p && init == p->init) || data != init->data) { 1146 nvkm_wr32(device, 0x40448c, init->data); 1147 data = init->data; 1148 } 1149 1150 while (addr < next) { 1151 nvkm_wr32(device, 0x404488, ctrl | (addr << 14)); 1152 addr += init->pitch; 1153 } 1154 } 1155 } 1156 1157 u64 1158 gf100_gr_units(struct nvkm_gr *base) 1159 { 1160 struct gf100_gr *gr = gf100_gr(base); 1161 u64 cfg; 1162 1163 cfg = (u32)gr->gpc_nr; 1164 cfg |= (u32)gr->tpc_total << 8; 1165 cfg |= (u64)gr->rop_nr << 32; 1166 1167 return cfg; 1168 } 1169 1170 static const struct nvkm_bitfield gf100_dispatch_error[] = { 1171 { 0x00000001, "INJECTED_BUNDLE_ERROR" }, 1172 { 0x00000002, "CLASS_SUBCH_MISMATCH" }, 1173 { 0x00000004, "SUBCHSW_DURING_NOTIFY" }, 1174 {} 1175 }; 1176 1177 static const struct nvkm_bitfield gf100_m2mf_error[] = { 1178 { 0x00000001, "PUSH_TOO_MUCH_DATA" }, 1179 { 0x00000002, "PUSH_NOT_ENOUGH_DATA" }, 1180 {} 1181 }; 1182 1183 static const struct nvkm_bitfield gf100_unk6_error[] = { 1184 { 0x00000001, "TEMP_TOO_SMALL" }, 1185 {} 1186 }; 1187 1188 static const struct nvkm_bitfield gf100_ccache_error[] = { 1189 { 0x00000001, "INTR" }, 1190 { 0x00000002, "LDCONST_OOB" }, 1191 {} 1192 }; 1193 1194 static const struct nvkm_bitfield gf100_macro_error[] = { 1195 { 0x00000001, "TOO_FEW_PARAMS" }, 1196 { 0x00000002, "TOO_MANY_PARAMS" }, 1197 { 0x00000004, "ILLEGAL_OPCODE" }, 1198 { 0x00000008, "DOUBLE_BRANCH" }, 1199 { 0x00000010, "WATCHDOG" }, 1200 {} 1201 }; 1202 1203 static const struct nvkm_bitfield gk104_sked_error[] = { 1204 { 0x00000040, "CTA_RESUME" }, 1205 { 0x00000080, "CONSTANT_BUFFER_SIZE" }, 1206 { 0x00000200, "LOCAL_MEMORY_SIZE_POS" }, 1207 { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" }, 1208 { 0x00000800, "WARP_CSTACK_SIZE" }, 1209 { 0x00001000, "TOTAL_TEMP_SIZE" }, 1210 { 0x00002000, "REGISTER_COUNT" }, 1211 { 0x00040000, "TOTAL_THREADS" }, 1212 { 0x00100000, "PROGRAM_OFFSET" }, 1213 { 0x00200000, "SHARED_MEMORY_SIZE" }, 1214 { 0x00800000, "CTA_THREAD_DIMENSION_ZERO" }, 1215 { 0x01000000, "MEMORY_WINDOW_OVERLAP" }, 1216 { 0x02000000, "SHARED_CONFIG_TOO_SMALL" }, 1217 { 0x04000000, "TOTAL_REGISTER_COUNT" }, 1218 {} 1219 }; 1220 1221 static const struct nvkm_bitfield gf100_gpc_rop_error[] = { 1222 { 0x00000002, "RT_PITCH_OVERRUN" }, 1223 { 0x00000010, "RT_WIDTH_OVERRUN" }, 1224 { 0x00000020, "RT_HEIGHT_OVERRUN" }, 1225 { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" }, 1226 { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" }, 1227 { 0x00000400, "RT_LINEAR_MISMATCH" }, 1228 {} 1229 }; 1230 1231 static void 1232 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) 1233 { 1234 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1235 struct nvkm_device *device = subdev->device; 1236 char error[128]; 1237 u32 trap[4]; 1238 1239 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; 1240 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); 1241 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); 1242 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); 1243 1244 nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]); 1245 1246 nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, " 1247 "format = %x, storage type = %x\n", 1248 gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, 1249 (trap[2] >> 8) & 0x3f, trap[3] & 0xff); 1250 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); 1251 } 1252 1253 const struct nvkm_enum gf100_mp_warp_error[] = { 1254 { 0x01, "STACK_ERROR" }, 1255 { 0x02, "API_STACK_ERROR" }, 1256 { 0x03, "RET_EMPTY_STACK_ERROR" }, 1257 { 0x04, "PC_WRAP" }, 1258 { 0x05, "MISALIGNED_PC" }, 1259 { 0x06, "PC_OVERFLOW" }, 1260 { 0x07, "MISALIGNED_IMMC_ADDR" }, 1261 { 0x08, "MISALIGNED_REG" }, 1262 { 0x09, "ILLEGAL_INSTR_ENCODING" }, 1263 { 0x0a, "ILLEGAL_SPH_INSTR_COMBO" }, 1264 { 0x0b, "ILLEGAL_INSTR_PARAM" }, 1265 { 0x0c, "INVALID_CONST_ADDR" }, 1266 { 0x0d, "OOR_REG" }, 1267 { 0x0e, "OOR_ADDR" }, 1268 { 0x0f, "MISALIGNED_ADDR" }, 1269 { 0x10, "INVALID_ADDR_SPACE" }, 1270 { 0x11, "ILLEGAL_INSTR_PARAM2" }, 1271 { 0x12, "INVALID_CONST_ADDR_LDC" }, 1272 { 0x13, "GEOMETRY_SM_ERROR" }, 1273 { 0x14, "DIVERGENT" }, 1274 { 0x15, "WARP_EXIT" }, 1275 {} 1276 }; 1277 1278 const struct nvkm_bitfield gf100_mp_global_error[] = { 1279 { 0x00000001, "SM_TO_SM_FAULT" }, 1280 { 0x00000002, "L1_ERROR" }, 1281 { 0x00000004, "MULTIPLE_WARP_ERRORS" }, 1282 { 0x00000008, "PHYSICAL_STACK_OVERFLOW" }, 1283 { 0x00000010, "BPT_INT" }, 1284 { 0x00000020, "BPT_PAUSE" }, 1285 { 0x00000040, "SINGLE_STEP_COMPLETE" }, 1286 { 0x20000000, "ECC_SEC_ERROR" }, 1287 { 0x40000000, "ECC_DED_ERROR" }, 1288 { 0x80000000, "TIMEOUT" }, 1289 {} 1290 }; 1291 1292 void 1293 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) 1294 { 1295 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1296 struct nvkm_device *device = subdev->device; 1297 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); 1298 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); 1299 const struct nvkm_enum *warp; 1300 char glob[128]; 1301 1302 nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr); 1303 warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff); 1304 1305 nvkm_error(subdev, "GPC%i/TPC%i/MP trap: " 1306 "global %08x [%s] warp %04x [%s]\n", 1307 gpc, tpc, gerr, glob, werr, warp ? warp->name : ""); 1308 1309 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); 1310 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); 1311 } 1312 1313 static void 1314 gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) 1315 { 1316 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1317 struct nvkm_device *device = subdev->device; 1318 u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); 1319 1320 if (stat & 0x00000001) { 1321 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); 1322 nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap); 1323 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); 1324 stat &= ~0x00000001; 1325 } 1326 1327 if (stat & 0x00000002) { 1328 gr->func->trap_mp(gr, gpc, tpc); 1329 stat &= ~0x00000002; 1330 } 1331 1332 if (stat & 0x00000004) { 1333 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); 1334 nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap); 1335 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); 1336 stat &= ~0x00000004; 1337 } 1338 1339 if (stat & 0x00000008) { 1340 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); 1341 nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap); 1342 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); 1343 stat &= ~0x00000008; 1344 } 1345 1346 if (stat & 0x00000010) { 1347 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0430)); 1348 nvkm_error(subdev, "GPC%d/TPC%d/MPC: %08x\n", gpc, tpc, trap); 1349 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0430), 0xc0000000); 1350 stat &= ~0x00000010; 1351 } 1352 1353 if (stat) { 1354 nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat); 1355 } 1356 } 1357 1358 static void 1359 gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) 1360 { 1361 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1362 struct nvkm_device *device = subdev->device; 1363 u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); 1364 int tpc; 1365 1366 if (stat & 0x00000001) { 1367 gf100_gr_trap_gpc_rop(gr, gpc); 1368 stat &= ~0x00000001; 1369 } 1370 1371 if (stat & 0x00000002) { 1372 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); 1373 nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap); 1374 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); 1375 stat &= ~0x00000002; 1376 } 1377 1378 if (stat & 0x00000004) { 1379 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); 1380 nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap); 1381 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); 1382 stat &= ~0x00000004; 1383 } 1384 1385 if (stat & 0x00000008) { 1386 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); 1387 nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap); 1388 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); 1389 stat &= ~0x00000009; 1390 } 1391 1392 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { 1393 u32 mask = 0x00010000 << tpc; 1394 if (stat & mask) { 1395 gf100_gr_trap_tpc(gr, gpc, tpc); 1396 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); 1397 stat &= ~mask; 1398 } 1399 } 1400 1401 if (stat) { 1402 nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat); 1403 } 1404 } 1405 1406 static void 1407 gf100_gr_trap_intr(struct gf100_gr *gr) 1408 { 1409 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1410 struct nvkm_device *device = subdev->device; 1411 char error[128]; 1412 u32 trap = nvkm_rd32(device, 0x400108); 1413 int rop, gpc; 1414 1415 if (trap & 0x00000001) { 1416 u32 stat = nvkm_rd32(device, 0x404000); 1417 1418 nvkm_snprintbf(error, sizeof(error), gf100_dispatch_error, 1419 stat & 0x3fffffff); 1420 nvkm_error(subdev, "DISPATCH %08x [%s]\n", stat, error); 1421 nvkm_wr32(device, 0x404000, 0xc0000000); 1422 nvkm_wr32(device, 0x400108, 0x00000001); 1423 trap &= ~0x00000001; 1424 } 1425 1426 if (trap & 0x00000002) { 1427 u32 stat = nvkm_rd32(device, 0x404600); 1428 1429 nvkm_snprintbf(error, sizeof(error), gf100_m2mf_error, 1430 stat & 0x3fffffff); 1431 nvkm_error(subdev, "M2MF %08x [%s]\n", stat, error); 1432 1433 nvkm_wr32(device, 0x404600, 0xc0000000); 1434 nvkm_wr32(device, 0x400108, 0x00000002); 1435 trap &= ~0x00000002; 1436 } 1437 1438 if (trap & 0x00000008) { 1439 u32 stat = nvkm_rd32(device, 0x408030); 1440 1441 nvkm_snprintbf(error, sizeof(error), gf100_ccache_error, 1442 stat & 0x3fffffff); 1443 nvkm_error(subdev, "CCACHE %08x [%s]\n", stat, error); 1444 nvkm_wr32(device, 0x408030, 0xc0000000); 1445 nvkm_wr32(device, 0x400108, 0x00000008); 1446 trap &= ~0x00000008; 1447 } 1448 1449 if (trap & 0x00000010) { 1450 u32 stat = nvkm_rd32(device, 0x405840); 1451 nvkm_error(subdev, "SHADER %08x, sph: 0x%06x, stage: 0x%02x\n", 1452 stat, stat & 0xffffff, (stat >> 24) & 0x3f); 1453 nvkm_wr32(device, 0x405840, 0xc0000000); 1454 nvkm_wr32(device, 0x400108, 0x00000010); 1455 trap &= ~0x00000010; 1456 } 1457 1458 if (trap & 0x00000040) { 1459 u32 stat = nvkm_rd32(device, 0x40601c); 1460 1461 nvkm_snprintbf(error, sizeof(error), gf100_unk6_error, 1462 stat & 0x3fffffff); 1463 nvkm_error(subdev, "UNK6 %08x [%s]\n", stat, error); 1464 1465 nvkm_wr32(device, 0x40601c, 0xc0000000); 1466 nvkm_wr32(device, 0x400108, 0x00000040); 1467 trap &= ~0x00000040; 1468 } 1469 1470 if (trap & 0x00000080) { 1471 u32 stat = nvkm_rd32(device, 0x404490); 1472 u32 pc = nvkm_rd32(device, 0x404494); 1473 u32 op = nvkm_rd32(device, 0x40449c); 1474 1475 nvkm_snprintbf(error, sizeof(error), gf100_macro_error, 1476 stat & 0x1fffffff); 1477 nvkm_error(subdev, "MACRO %08x [%s], pc: 0x%03x%s, op: 0x%08x\n", 1478 stat, error, pc & 0x7ff, 1479 (pc & 0x10000000) ? "" : " (invalid)", 1480 op); 1481 1482 nvkm_wr32(device, 0x404490, 0xc0000000); 1483 nvkm_wr32(device, 0x400108, 0x00000080); 1484 trap &= ~0x00000080; 1485 } 1486 1487 if (trap & 0x00000100) { 1488 u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff; 1489 1490 nvkm_snprintbf(error, sizeof(error), gk104_sked_error, stat); 1491 nvkm_error(subdev, "SKED: %08x [%s]\n", stat, error); 1492 1493 if (stat) 1494 nvkm_wr32(device, 0x407020, 0x40000000); 1495 nvkm_wr32(device, 0x400108, 0x00000100); 1496 trap &= ~0x00000100; 1497 } 1498 1499 if (trap & 0x01000000) { 1500 u32 stat = nvkm_rd32(device, 0x400118); 1501 for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { 1502 u32 mask = 0x00000001 << gpc; 1503 if (stat & mask) { 1504 gf100_gr_trap_gpc(gr, gpc); 1505 nvkm_wr32(device, 0x400118, mask); 1506 stat &= ~mask; 1507 } 1508 } 1509 nvkm_wr32(device, 0x400108, 0x01000000); 1510 trap &= ~0x01000000; 1511 } 1512 1513 if (trap & 0x02000000) { 1514 for (rop = 0; rop < gr->rop_nr; rop++) { 1515 u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); 1516 u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); 1517 nvkm_error(subdev, "ROP%d %08x %08x\n", 1518 rop, statz, statc); 1519 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); 1520 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); 1521 } 1522 nvkm_wr32(device, 0x400108, 0x02000000); 1523 trap &= ~0x02000000; 1524 } 1525 1526 if (trap) { 1527 nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap); 1528 nvkm_wr32(device, 0x400108, trap); 1529 } 1530 } 1531 1532 static void 1533 gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) 1534 { 1535 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1536 struct nvkm_device *device = subdev->device; 1537 nvkm_error(subdev, "%06x - done %08x\n", base, 1538 nvkm_rd32(device, base + 0x400)); 1539 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, 1540 nvkm_rd32(device, base + 0x800), 1541 nvkm_rd32(device, base + 0x804), 1542 nvkm_rd32(device, base + 0x808), 1543 nvkm_rd32(device, base + 0x80c)); 1544 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, 1545 nvkm_rd32(device, base + 0x810), 1546 nvkm_rd32(device, base + 0x814), 1547 nvkm_rd32(device, base + 0x818), 1548 nvkm_rd32(device, base + 0x81c)); 1549 } 1550 1551 void 1552 gf100_gr_ctxctl_debug(struct gf100_gr *gr) 1553 { 1554 struct nvkm_device *device = gr->base.engine.subdev.device; 1555 u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff; 1556 u32 gpc; 1557 1558 gf100_gr_ctxctl_debug_unit(gr, 0x409000); 1559 for (gpc = 0; gpc < gpcnr; gpc++) 1560 gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000)); 1561 } 1562 1563 static void 1564 gf100_gr_ctxctl_isr(struct gf100_gr *gr) 1565 { 1566 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1567 struct nvkm_device *device = subdev->device; 1568 u32 stat = nvkm_rd32(device, 0x409c18); 1569 1570 if (!gr->firmware && (stat & 0x00000001)) { 1571 u32 code = nvkm_rd32(device, 0x409814); 1572 if (code == E_BAD_FWMTHD) { 1573 u32 class = nvkm_rd32(device, 0x409808); 1574 u32 addr = nvkm_rd32(device, 0x40980c); 1575 u32 subc = (addr & 0x00070000) >> 16; 1576 u32 mthd = (addr & 0x00003ffc); 1577 u32 data = nvkm_rd32(device, 0x409810); 1578 1579 nvkm_error(subdev, "FECS MTHD subc %d class %04x " 1580 "mthd %04x data %08x\n", 1581 subc, class, mthd, data); 1582 } else { 1583 nvkm_error(subdev, "FECS ucode error %d\n", code); 1584 } 1585 nvkm_wr32(device, 0x409c20, 0x00000001); 1586 stat &= ~0x00000001; 1587 } 1588 1589 if (!gr->firmware && (stat & 0x00080000)) { 1590 nvkm_error(subdev, "FECS watchdog timeout\n"); 1591 gf100_gr_ctxctl_debug(gr); 1592 nvkm_wr32(device, 0x409c20, 0x00080000); 1593 stat &= ~0x00080000; 1594 } 1595 1596 if (stat) { 1597 nvkm_error(subdev, "FECS %08x\n", stat); 1598 gf100_gr_ctxctl_debug(gr); 1599 nvkm_wr32(device, 0x409c20, stat); 1600 } 1601 } 1602 1603 static void 1604 gf100_gr_intr(struct nvkm_gr *base) 1605 { 1606 struct gf100_gr *gr = gf100_gr(base); 1607 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1608 struct nvkm_device *device = subdev->device; 1609 struct nvkm_chan *chan; 1610 unsigned long flags; 1611 u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; 1612 u32 stat = nvkm_rd32(device, 0x400100); 1613 u32 addr = nvkm_rd32(device, 0x400704); 1614 u32 mthd = (addr & 0x00003ffc); 1615 u32 subc = (addr & 0x00070000) >> 16; 1616 u32 data = nvkm_rd32(device, 0x400708); 1617 u32 code = nvkm_rd32(device, 0x400110); 1618 u32 class; 1619 const char *name = "unknown"; 1620 int chid = -1; 1621 1622 chan = nvkm_chan_get_inst(&gr->base.engine, (u64)inst << 12, &flags); 1623 if (chan) { 1624 name = chan->name; 1625 chid = chan->id; 1626 } 1627 1628 if (device->card_type < NV_E0 || subc < 4) 1629 class = nvkm_rd32(device, 0x404200 + (subc * 4)); 1630 else 1631 class = 0x0000; 1632 1633 if (stat & 0x00000001) { 1634 /* 1635 * notifier interrupt, only needed for cyclestats 1636 * can be safely ignored 1637 */ 1638 nvkm_wr32(device, 0x400100, 0x00000001); 1639 stat &= ~0x00000001; 1640 } 1641 1642 if (stat & 0x00000010) { 1643 if (!gf100_gr_mthd_sw(device, class, mthd, data)) { 1644 nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] " 1645 "subc %d class %04x mthd %04x data %08x\n", 1646 chid, inst << 12, name, subc, 1647 class, mthd, data); 1648 } 1649 nvkm_wr32(device, 0x400100, 0x00000010); 1650 stat &= ~0x00000010; 1651 } 1652 1653 if (stat & 0x00000020) { 1654 nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] " 1655 "subc %d class %04x mthd %04x data %08x\n", 1656 chid, inst << 12, name, subc, class, mthd, data); 1657 nvkm_wr32(device, 0x400100, 0x00000020); 1658 stat &= ~0x00000020; 1659 } 1660 1661 if (stat & 0x00100000) { 1662 const struct nvkm_enum *en = 1663 nvkm_enum_find(nv50_data_error_names, code); 1664 nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] " 1665 "subc %d class %04x mthd %04x data %08x\n", 1666 code, en ? en->name : "", chid, inst << 12, 1667 name, subc, class, mthd, data); 1668 nvkm_wr32(device, 0x400100, 0x00100000); 1669 stat &= ~0x00100000; 1670 } 1671 1672 if (stat & 0x00200000) { 1673 nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n", 1674 chid, inst << 12, name); 1675 gf100_gr_trap_intr(gr); 1676 nvkm_wr32(device, 0x400100, 0x00200000); 1677 stat &= ~0x00200000; 1678 } 1679 1680 if (stat & 0x00080000) { 1681 gf100_gr_ctxctl_isr(gr); 1682 nvkm_wr32(device, 0x400100, 0x00080000); 1683 stat &= ~0x00080000; 1684 } 1685 1686 if (stat) { 1687 nvkm_error(subdev, "intr %08x\n", stat); 1688 nvkm_wr32(device, 0x400100, stat); 1689 } 1690 1691 nvkm_wr32(device, 0x400500, 0x00010001); 1692 nvkm_chan_put(&chan, flags); 1693 } 1694 1695 static void 1696 gf100_gr_init_fw(struct nvkm_falcon *falcon, 1697 struct nvkm_blob *code, struct nvkm_blob *data) 1698 { 1699 nvkm_falcon_load_dmem(falcon, data->data, 0x0, data->size, 0); 1700 nvkm_falcon_load_imem(falcon, code->data, 0x0, code->size, 0, 0, false); 1701 } 1702 1703 static void 1704 gf100_gr_init_csdata(struct gf100_gr *gr, 1705 const struct gf100_gr_pack *pack, 1706 u32 falcon, u32 starstar, u32 base) 1707 { 1708 struct nvkm_device *device = gr->base.engine.subdev.device; 1709 const struct gf100_gr_pack *iter; 1710 const struct gf100_gr_init *init; 1711 u32 addr = ~0, prev = ~0, xfer = 0; 1712 u32 star, temp; 1713 1714 nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar); 1715 star = nvkm_rd32(device, falcon + 0x01c4); 1716 temp = nvkm_rd32(device, falcon + 0x01c4); 1717 if (temp > star) 1718 star = temp; 1719 nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star); 1720 1721 pack_for_each_init(init, iter, pack) { 1722 u32 head = init->addr - base; 1723 u32 tail = head + init->count * init->pitch; 1724 while (head < tail) { 1725 if (head != prev + 4 || xfer >= 32) { 1726 if (xfer) { 1727 u32 data = ((--xfer << 26) | addr); 1728 nvkm_wr32(device, falcon + 0x01c4, data); 1729 star += 4; 1730 } 1731 addr = head; 1732 xfer = 0; 1733 } 1734 prev = head; 1735 xfer = xfer + 1; 1736 head = head + init->pitch; 1737 } 1738 } 1739 1740 nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr); 1741 nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar); 1742 nvkm_wr32(device, falcon + 0x01c4, star + 4); 1743 } 1744 1745 /* Initialize context from an external (secure or not) firmware */ 1746 static int 1747 gf100_gr_init_ctxctl_ext(struct gf100_gr *gr) 1748 { 1749 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1750 struct nvkm_device *device = subdev->device; 1751 u32 lsf_mask = 0; 1752 int ret; 1753 1754 /* load fuc microcode */ 1755 nvkm_mc_unk260(device, 0); 1756 1757 /* securely-managed falcons must be reset using secure boot */ 1758 1759 if (!nvkm_acr_managed_falcon(device, NVKM_ACR_LSF_FECS)) { 1760 gf100_gr_init_fw(&gr->fecs.falcon, &gr->fecs.inst, 1761 &gr->fecs.data); 1762 } else { 1763 lsf_mask |= BIT(NVKM_ACR_LSF_FECS); 1764 } 1765 1766 if (!nvkm_acr_managed_falcon(device, NVKM_ACR_LSF_GPCCS)) { 1767 gf100_gr_init_fw(&gr->gpccs.falcon, &gr->gpccs.inst, 1768 &gr->gpccs.data); 1769 } else { 1770 lsf_mask |= BIT(NVKM_ACR_LSF_GPCCS); 1771 } 1772 1773 if (lsf_mask) { 1774 ret = nvkm_acr_bootstrap_falcons(device, lsf_mask); 1775 if (ret) 1776 return ret; 1777 } 1778 1779 nvkm_mc_unk260(device, 1); 1780 1781 /* start both of them running */ 1782 nvkm_wr32(device, 0x409800, 0x00000000); 1783 nvkm_wr32(device, 0x41a10c, 0x00000000); 1784 nvkm_wr32(device, 0x40910c, 0x00000000); 1785 1786 nvkm_falcon_start(&gr->gpccs.falcon); 1787 nvkm_falcon_start(&gr->fecs.falcon); 1788 1789 if (nvkm_msec(device, 2000, 1790 if (nvkm_rd32(device, 0x409800) & 0x00000001) 1791 break; 1792 ) < 0) 1793 return -EBUSY; 1794 1795 gf100_gr_fecs_set_watchdog_timeout(gr, 0x7fffffff); 1796 1797 /* Determine how much memory is required to store main context image. */ 1798 ret = gf100_gr_fecs_discover_image_size(gr, &gr->size); 1799 if (ret) 1800 return ret; 1801 1802 /* Determine how much memory is required to store ZCULL image. */ 1803 ret = gf100_gr_fecs_discover_zcull_image_size(gr, &gr->size_zcull); 1804 if (ret) 1805 return ret; 1806 1807 /* Determine how much memory is required to store PerfMon image. */ 1808 ret = gf100_gr_fecs_discover_pm_image_size(gr, &gr->size_pm); 1809 if (ret) 1810 return ret; 1811 1812 /*XXX: We (likely) require PMU support to even bother with this. 1813 * 1814 * Also, it seems like not all GPUs support ELPG. Traces I 1815 * have here show RM enabling it on Kepler/Turing, but none 1816 * of the GPUs between those. NVGPU decides this by PCIID. 1817 */ 1818 if (0) { 1819 ret = gf100_gr_fecs_elpg_bind(gr); 1820 if (ret) 1821 return ret; 1822 } 1823 1824 return 0; 1825 } 1826 1827 static int 1828 gf100_gr_init_ctxctl_int(struct gf100_gr *gr) 1829 { 1830 const struct gf100_grctx_func *grctx = gr->func->grctx; 1831 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1832 struct nvkm_device *device = subdev->device; 1833 1834 if (!gr->func->fecs.ucode) { 1835 return -ENOSYS; 1836 } 1837 1838 /* load HUB microcode */ 1839 nvkm_mc_unk260(device, 0); 1840 nvkm_falcon_load_dmem(&gr->fecs.falcon, 1841 gr->func->fecs.ucode->data.data, 0x0, 1842 gr->func->fecs.ucode->data.size, 0); 1843 nvkm_falcon_load_imem(&gr->fecs.falcon, 1844 gr->func->fecs.ucode->code.data, 0x0, 1845 gr->func->fecs.ucode->code.size, 0, 0, false); 1846 1847 /* load GPC microcode */ 1848 nvkm_falcon_load_dmem(&gr->gpccs.falcon, 1849 gr->func->gpccs.ucode->data.data, 0x0, 1850 gr->func->gpccs.ucode->data.size, 0); 1851 nvkm_falcon_load_imem(&gr->gpccs.falcon, 1852 gr->func->gpccs.ucode->code.data, 0x0, 1853 gr->func->gpccs.ucode->code.size, 0, 0, false); 1854 nvkm_mc_unk260(device, 1); 1855 1856 /* load register lists */ 1857 gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000); 1858 gf100_gr_init_csdata(gr, grctx->gpc_0, 0x41a000, 0x000, 0x418000); 1859 gf100_gr_init_csdata(gr, grctx->gpc_1, 0x41a000, 0x000, 0x418000); 1860 gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800); 1861 gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00); 1862 1863 /* start HUB ucode running, it'll init the GPCs */ 1864 nvkm_wr32(device, 0x40910c, 0x00000000); 1865 nvkm_wr32(device, 0x409100, 0x00000002); 1866 if (nvkm_msec(device, 2000, 1867 if (nvkm_rd32(device, 0x409800) & 0x80000000) 1868 break; 1869 ) < 0) { 1870 gf100_gr_ctxctl_debug(gr); 1871 return -EBUSY; 1872 } 1873 1874 gr->size = nvkm_rd32(device, 0x409804); 1875 return 0; 1876 } 1877 1878 int 1879 gf100_gr_init_ctxctl(struct gf100_gr *gr) 1880 { 1881 int ret; 1882 1883 if (gr->firmware) 1884 ret = gf100_gr_init_ctxctl_ext(gr); 1885 else 1886 ret = gf100_gr_init_ctxctl_int(gr); 1887 1888 return ret; 1889 } 1890 1891 void 1892 gf100_gr_oneinit_sm_id(struct gf100_gr *gr) 1893 { 1894 int tpc, gpc; 1895 for (tpc = 0; tpc < gr->tpc_max; tpc++) { 1896 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 1897 if (tpc < gr->tpc_nr[gpc]) { 1898 gr->sm[gr->sm_nr].gpc = gpc; 1899 gr->sm[gr->sm_nr].tpc = tpc; 1900 gr->sm_nr++; 1901 } 1902 } 1903 } 1904 } 1905 1906 void 1907 gf100_gr_oneinit_tiles(struct gf100_gr *gr) 1908 { 1909 static const u8 primes[] = { 1910 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61 1911 }; 1912 int init_frac[GPC_MAX], init_err[GPC_MAX], run_err[GPC_MAX], i, j; 1913 u32 mul_factor, comm_denom; 1914 u8 gpc_map[GPC_MAX]; 1915 bool sorted; 1916 1917 switch (gr->tpc_total) { 1918 case 15: gr->screen_tile_row_offset = 0x06; break; 1919 case 14: gr->screen_tile_row_offset = 0x05; break; 1920 case 13: gr->screen_tile_row_offset = 0x02; break; 1921 case 11: gr->screen_tile_row_offset = 0x07; break; 1922 case 10: gr->screen_tile_row_offset = 0x06; break; 1923 case 7: 1924 case 5: gr->screen_tile_row_offset = 0x01; break; 1925 case 3: gr->screen_tile_row_offset = 0x02; break; 1926 case 2: 1927 case 1: gr->screen_tile_row_offset = 0x01; break; 1928 default: gr->screen_tile_row_offset = 0x03; 1929 for (i = 0; i < ARRAY_SIZE(primes); i++) { 1930 if (gr->tpc_total % primes[i]) { 1931 gr->screen_tile_row_offset = primes[i]; 1932 break; 1933 } 1934 } 1935 break; 1936 } 1937 1938 /* Sort GPCs by TPC count, highest-to-lowest. */ 1939 for (i = 0; i < gr->gpc_nr; i++) 1940 gpc_map[i] = i; 1941 sorted = false; 1942 1943 while (!sorted) { 1944 for (sorted = true, i = 0; i < gr->gpc_nr - 1; i++) { 1945 if (gr->tpc_nr[gpc_map[i + 1]] > 1946 gr->tpc_nr[gpc_map[i + 0]]) { 1947 u8 swap = gpc_map[i]; 1948 gpc_map[i + 0] = gpc_map[i + 1]; 1949 gpc_map[i + 1] = swap; 1950 sorted = false; 1951 } 1952 } 1953 } 1954 1955 /* Determine tile->GPC mapping */ 1956 mul_factor = gr->gpc_nr * gr->tpc_max; 1957 if (mul_factor & 1) 1958 mul_factor = 2; 1959 else 1960 mul_factor = 1; 1961 1962 comm_denom = gr->gpc_nr * gr->tpc_max * mul_factor; 1963 1964 for (i = 0; i < gr->gpc_nr; i++) { 1965 init_frac[i] = gr->tpc_nr[gpc_map[i]] * gr->gpc_nr * mul_factor; 1966 init_err[i] = i * gr->tpc_max * mul_factor - comm_denom/2; 1967 run_err[i] = init_frac[i] + init_err[i]; 1968 } 1969 1970 for (i = 0; i < gr->tpc_total;) { 1971 for (j = 0; j < gr->gpc_nr; j++) { 1972 if ((run_err[j] * 2) >= comm_denom) { 1973 gr->tile[i++] = gpc_map[j]; 1974 run_err[j] += init_frac[j] - comm_denom; 1975 } else { 1976 run_err[j] += init_frac[j]; 1977 } 1978 } 1979 } 1980 } 1981 1982 static int 1983 gf100_gr_oneinit(struct nvkm_gr *base) 1984 { 1985 struct gf100_gr *gr = gf100_gr(base); 1986 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1987 struct nvkm_device *device = subdev->device; 1988 int ret, i, j; 1989 1990 nvkm_pmu_pgob(device->pmu, false); 1991 1992 gr->rop_nr = gr->func->rops(gr); 1993 gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; 1994 for (i = 0; i < gr->gpc_nr; i++) { 1995 gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); 1996 gr->tpc_max = max(gr->tpc_max, gr->tpc_nr[i]); 1997 gr->tpc_total += gr->tpc_nr[i]; 1998 gr->ppc_nr[i] = gr->func->ppc_nr; 1999 for (j = 0; j < gr->ppc_nr[i]; j++) { 2000 gr->ppc_tpc_mask[i][j] = 2001 nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); 2002 if (gr->ppc_tpc_mask[i][j] == 0) 2003 continue; 2004 gr->ppc_mask[i] |= (1 << j); 2005 gr->ppc_tpc_nr[i][j] = hweight8(gr->ppc_tpc_mask[i][j]); 2006 if (gr->ppc_tpc_min == 0 || 2007 gr->ppc_tpc_min > gr->ppc_tpc_nr[i][j]) 2008 gr->ppc_tpc_min = gr->ppc_tpc_nr[i][j]; 2009 if (gr->ppc_tpc_max < gr->ppc_tpc_nr[i][j]) 2010 gr->ppc_tpc_max = gr->ppc_tpc_nr[i][j]; 2011 } 2012 } 2013 2014 /* Allocate global context buffers. */ 2015 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->pagepool_size, 2016 0x100, false, &gr->pagepool); 2017 if (ret) 2018 return ret; 2019 2020 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->bundle_size, 2021 0x100, false, &gr->bundle_cb); 2022 if (ret) 2023 return ret; 2024 2025 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->attrib_cb_size(gr), 2026 0x1000, false, &gr->attrib_cb); 2027 if (ret) 2028 return ret; 2029 2030 if (gr->func->grctx->unknown_size) { 2031 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->unknown_size, 2032 0x100, false, &gr->unknown); 2033 if (ret) 2034 return ret; 2035 } 2036 2037 memset(gr->tile, 0xff, sizeof(gr->tile)); 2038 gr->func->oneinit_tiles(gr); 2039 gr->func->oneinit_sm_id(gr); 2040 return 0; 2041 } 2042 2043 static int 2044 gf100_gr_init_(struct nvkm_gr *base) 2045 { 2046 struct gf100_gr *gr = gf100_gr(base); 2047 struct nvkm_subdev *subdev = &base->engine.subdev; 2048 struct nvkm_device *device = subdev->device; 2049 bool reset = device->chipset == 0x137 || device->chipset == 0x138; 2050 u32 ret; 2051 2052 /* On certain GP107/GP108 boards, we trigger a weird issue where 2053 * GR will stop responding to PRI accesses after we've asked the 2054 * SEC2 RTOS to boot the GR falcons. This happens with far more 2055 * frequency when cold-booting a board (ie. returning from D3). 2056 * 2057 * The root cause for this is not known and has proven difficult 2058 * to isolate, with many avenues being dead-ends. 2059 * 2060 * A workaround was discovered by Karol, whereby putting GR into 2061 * reset for an extended period right before initialisation 2062 * prevents the problem from occuring. 2063 * 2064 * XXX: As RM does not require any such workaround, this is more 2065 * of a hack than a true fix. 2066 */ 2067 reset = nvkm_boolopt(device->cfgopt, "NvGrResetWar", reset); 2068 if (reset) { 2069 nvkm_mask(device, 0x000200, 0x00001000, 0x00000000); 2070 nvkm_rd32(device, 0x000200); 2071 msleep(50); 2072 nvkm_mask(device, 0x000200, 0x00001000, 0x00001000); 2073 nvkm_rd32(device, 0x000200); 2074 } 2075 2076 nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); 2077 2078 ret = nvkm_falcon_get(&gr->fecs.falcon, subdev); 2079 if (ret) 2080 return ret; 2081 2082 ret = nvkm_falcon_get(&gr->gpccs.falcon, subdev); 2083 if (ret) 2084 return ret; 2085 2086 return gr->func->init(gr); 2087 } 2088 2089 static int 2090 gf100_gr_fini(struct nvkm_gr *base, bool suspend) 2091 { 2092 struct gf100_gr *gr = gf100_gr(base); 2093 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 2094 nvkm_falcon_put(&gr->gpccs.falcon, subdev); 2095 nvkm_falcon_put(&gr->fecs.falcon, subdev); 2096 return 0; 2097 } 2098 2099 static void * 2100 gf100_gr_dtor(struct nvkm_gr *base) 2101 { 2102 struct gf100_gr *gr = gf100_gr(base); 2103 2104 kfree(gr->data); 2105 2106 nvkm_memory_unref(&gr->unknown); 2107 nvkm_memory_unref(&gr->attrib_cb); 2108 nvkm_memory_unref(&gr->bundle_cb); 2109 nvkm_memory_unref(&gr->pagepool); 2110 2111 nvkm_falcon_dtor(&gr->gpccs.falcon); 2112 nvkm_falcon_dtor(&gr->fecs.falcon); 2113 2114 nvkm_blob_dtor(&gr->fecs.inst); 2115 nvkm_blob_dtor(&gr->fecs.data); 2116 nvkm_blob_dtor(&gr->gpccs.inst); 2117 nvkm_blob_dtor(&gr->gpccs.data); 2118 2119 vfree(gr->bundle); 2120 vfree(gr->method); 2121 vfree(gr->sw_ctx); 2122 vfree(gr->sw_nonctx); 2123 2124 return gr; 2125 } 2126 2127 static const struct nvkm_falcon_func 2128 gf100_gr_flcn = { 2129 .load_imem = nvkm_falcon_v1_load_imem, 2130 .load_dmem = nvkm_falcon_v1_load_dmem, 2131 .start = nvkm_falcon_v1_start, 2132 }; 2133 2134 void 2135 gf100_gr_init_num_tpc_per_gpc(struct gf100_gr *gr, bool pd, bool ds) 2136 { 2137 struct nvkm_device *device = gr->base.engine.subdev.device; 2138 int gpc, i, j; 2139 u32 data; 2140 2141 for (gpc = 0, i = 0; i < 4; i++) { 2142 for (data = 0, j = 0; j < 8 && gpc < gr->gpc_nr; j++, gpc++) 2143 data |= gr->tpc_nr[gpc] << (j * 4); 2144 if (pd) 2145 nvkm_wr32(device, 0x406028 + (i * 4), data); 2146 if (ds) 2147 nvkm_wr32(device, 0x405870 + (i * 4), data); 2148 } 2149 } 2150 2151 void 2152 gf100_gr_init_400054(struct gf100_gr *gr) 2153 { 2154 nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x34ce3464); 2155 } 2156 2157 void 2158 gf100_gr_init_rop_exceptions(struct gf100_gr *gr) 2159 { 2160 struct nvkm_device *device = gr->base.engine.subdev.device; 2161 int rop; 2162 2163 for (rop = 0; rop < gr->rop_nr; rop++) { 2164 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000); 2165 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000); 2166 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); 2167 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); 2168 } 2169 } 2170 2171 void 2172 gf100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) 2173 { 2174 struct nvkm_device *device = gr->base.engine.subdev.device; 2175 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); 2176 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); 2177 } 2178 2179 void 2180 gf100_gr_init_tex_hww_esr(struct gf100_gr *gr, int gpc, int tpc) 2181 { 2182 struct nvkm_device *device = gr->base.engine.subdev.device; 2183 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); 2184 } 2185 2186 void 2187 gf100_gr_init_419eb4(struct gf100_gr *gr) 2188 { 2189 struct nvkm_device *device = gr->base.engine.subdev.device; 2190 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); 2191 } 2192 2193 void 2194 gf100_gr_init_419cc0(struct gf100_gr *gr) 2195 { 2196 struct nvkm_device *device = gr->base.engine.subdev.device; 2197 int gpc, tpc; 2198 2199 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); 2200 2201 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 2202 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) 2203 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); 2204 } 2205 } 2206 2207 void 2208 gf100_gr_init_40601c(struct gf100_gr *gr) 2209 { 2210 nvkm_wr32(gr->base.engine.subdev.device, 0x40601c, 0xc0000000); 2211 } 2212 2213 void 2214 gf100_gr_init_fecs_exceptions(struct gf100_gr *gr) 2215 { 2216 const u32 data = gr->firmware ? 0x000e0000 : 0x000e0001; 2217 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, data); 2218 } 2219 2220 void 2221 gf100_gr_init_gpc_mmu(struct gf100_gr *gr) 2222 { 2223 struct nvkm_device *device = gr->base.engine.subdev.device; 2224 struct nvkm_fb *fb = device->fb; 2225 2226 nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0x00000001); 2227 nvkm_wr32(device, 0x4188a4, 0x03000000); 2228 nvkm_wr32(device, 0x418888, 0x00000000); 2229 nvkm_wr32(device, 0x41888c, 0x00000000); 2230 nvkm_wr32(device, 0x418890, 0x00000000); 2231 nvkm_wr32(device, 0x418894, 0x00000000); 2232 nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(fb->mmu_wr) >> 8); 2233 nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(fb->mmu_rd) >> 8); 2234 } 2235 2236 void 2237 gf100_gr_init_num_active_ltcs(struct gf100_gr *gr) 2238 { 2239 struct nvkm_device *device = gr->base.engine.subdev.device; 2240 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); 2241 } 2242 2243 void 2244 gf100_gr_init_zcull(struct gf100_gr *gr) 2245 { 2246 struct nvkm_device *device = gr->base.engine.subdev.device; 2247 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); 2248 const u8 tile_nr = ALIGN(gr->tpc_total, 32); 2249 u8 bank[GPC_MAX] = {}, gpc, i, j; 2250 u32 data; 2251 2252 for (i = 0; i < tile_nr; i += 8) { 2253 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { 2254 data |= bank[gr->tile[i + j]] << (j * 4); 2255 bank[gr->tile[i + j]]++; 2256 } 2257 nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data); 2258 } 2259 2260 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 2261 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), 2262 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); 2263 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | 2264 gr->tpc_total); 2265 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); 2266 } 2267 2268 nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); 2269 } 2270 2271 void 2272 gf100_gr_init_vsc_stream_master(struct gf100_gr *gr) 2273 { 2274 struct nvkm_device *device = gr->base.engine.subdev.device; 2275 nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001); 2276 } 2277 2278 static int 2279 gf100_gr_reset(struct nvkm_gr *base) 2280 { 2281 struct nvkm_subdev *subdev = &base->engine.subdev; 2282 struct nvkm_device *device = subdev->device; 2283 struct gf100_gr *gr = gf100_gr(base); 2284 2285 nvkm_mask(device, 0x400500, 0x00000001, 0x00000000); 2286 2287 WARN_ON(gf100_gr_fecs_halt_pipeline(gr)); 2288 2289 subdev->func->fini(subdev, false); 2290 nvkm_mc_disable(device, subdev->type, subdev->inst); 2291 2292 nvkm_mc_enable(device, subdev->type, subdev->inst); 2293 return subdev->func->init(subdev); 2294 } 2295 2296 int 2297 gf100_gr_init(struct gf100_gr *gr) 2298 { 2299 struct nvkm_device *device = gr->base.engine.subdev.device; 2300 int gpc, tpc; 2301 2302 nvkm_mask(device, 0x400500, 0x00010001, 0x00000000); 2303 2304 if (gr->func->init_419bd8) 2305 gr->func->init_419bd8(gr); 2306 2307 gr->func->init_gpc_mmu(gr); 2308 2309 if (gr->sw_nonctx) 2310 gf100_gr_mmio(gr, gr->sw_nonctx); 2311 else 2312 gf100_gr_mmio(gr, gr->func->mmio); 2313 2314 gf100_gr_wait_idle(gr); 2315 2316 if (gr->func->init_r405a14) 2317 gr->func->init_r405a14(gr); 2318 2319 if (gr->func->clkgate_pack) 2320 nvkm_therm_clkgate_init(device->therm, gr->func->clkgate_pack); 2321 2322 if (gr->func->init_bios) 2323 gr->func->init_bios(gr); 2324 2325 gr->func->init_vsc_stream_master(gr); 2326 gr->func->init_zcull(gr); 2327 gr->func->init_num_active_ltcs(gr); 2328 if (gr->func->init_rop_active_fbps) 2329 gr->func->init_rop_active_fbps(gr); 2330 if (gr->func->init_bios_2) 2331 gr->func->init_bios_2(gr); 2332 if (gr->func->init_swdx_pes_mask) 2333 gr->func->init_swdx_pes_mask(gr); 2334 if (gr->func->init_fs) 2335 gr->func->init_fs(gr); 2336 2337 nvkm_wr32(device, 0x400500, 0x00010001); 2338 2339 nvkm_wr32(device, 0x400100, 0xffffffff); 2340 nvkm_wr32(device, 0x40013c, 0xffffffff); 2341 nvkm_wr32(device, 0x400124, 0x00000002); 2342 2343 gr->func->init_fecs_exceptions(gr); 2344 if (gr->func->init_ds_hww_esr_2) 2345 gr->func->init_ds_hww_esr_2(gr); 2346 2347 nvkm_wr32(device, 0x404000, 0xc0000000); 2348 nvkm_wr32(device, 0x404600, 0xc0000000); 2349 nvkm_wr32(device, 0x408030, 0xc0000000); 2350 2351 if (gr->func->init_40601c) 2352 gr->func->init_40601c(gr); 2353 2354 nvkm_wr32(device, 0x406018, 0xc0000000); 2355 nvkm_wr32(device, 0x404490, 0xc0000000); 2356 2357 if (gr->func->init_sked_hww_esr) 2358 gr->func->init_sked_hww_esr(gr); 2359 2360 nvkm_wr32(device, 0x405840, 0xc0000000); 2361 nvkm_wr32(device, 0x405844, 0x00ffffff); 2362 2363 if (gr->func->init_419cc0) 2364 gr->func->init_419cc0(gr); 2365 if (gr->func->init_419eb4) 2366 gr->func->init_419eb4(gr); 2367 if (gr->func->init_419c9c) 2368 gr->func->init_419c9c(gr); 2369 2370 if (gr->func->init_ppc_exceptions) 2371 gr->func->init_ppc_exceptions(gr); 2372 2373 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 2374 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); 2375 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); 2376 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); 2377 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); 2378 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { 2379 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); 2380 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); 2381 if (gr->func->init_tex_hww_esr) 2382 gr->func->init_tex_hww_esr(gr, gpc, tpc); 2383 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); 2384 if (gr->func->init_504430) 2385 gr->func->init_504430(gr, gpc, tpc); 2386 gr->func->init_shader_exceptions(gr, gpc, tpc); 2387 } 2388 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); 2389 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); 2390 } 2391 2392 gr->func->init_rop_exceptions(gr); 2393 2394 nvkm_wr32(device, 0x400108, 0xffffffff); 2395 nvkm_wr32(device, 0x400138, 0xffffffff); 2396 nvkm_wr32(device, 0x400118, 0xffffffff); 2397 nvkm_wr32(device, 0x400130, 0xffffffff); 2398 nvkm_wr32(device, 0x40011c, 0xffffffff); 2399 nvkm_wr32(device, 0x400134, 0xffffffff); 2400 2401 if (gr->func->init_400054) 2402 gr->func->init_400054(gr); 2403 2404 gf100_gr_zbc_init(gr); 2405 2406 if (gr->func->init_4188a4) 2407 gr->func->init_4188a4(gr); 2408 2409 return gf100_gr_init_ctxctl(gr); 2410 } 2411 2412 void 2413 gf100_gr_fecs_reset(struct gf100_gr *gr) 2414 { 2415 struct nvkm_device *device = gr->base.engine.subdev.device; 2416 2417 nvkm_wr32(device, 0x409614, 0x00000070); 2418 nvkm_usec(device, 10, NVKM_DELAY); 2419 nvkm_mask(device, 0x409614, 0x00000700, 0x00000700); 2420 nvkm_usec(device, 10, NVKM_DELAY); 2421 nvkm_rd32(device, 0x409614); 2422 } 2423 2424 #include "fuc/hubgf100.fuc3.h" 2425 2426 struct gf100_gr_ucode 2427 gf100_gr_fecs_ucode = { 2428 .code.data = gf100_grhub_code, 2429 .code.size = sizeof(gf100_grhub_code), 2430 .data.data = gf100_grhub_data, 2431 .data.size = sizeof(gf100_grhub_data), 2432 }; 2433 2434 #include "fuc/gpcgf100.fuc3.h" 2435 2436 struct gf100_gr_ucode 2437 gf100_gr_gpccs_ucode = { 2438 .code.data = gf100_grgpc_code, 2439 .code.size = sizeof(gf100_grgpc_code), 2440 .data.data = gf100_grgpc_data, 2441 .data.size = sizeof(gf100_grgpc_data), 2442 }; 2443 2444 static const struct nvkm_gr_func 2445 gf100_gr_ = { 2446 .dtor = gf100_gr_dtor, 2447 .oneinit = gf100_gr_oneinit, 2448 .init = gf100_gr_init_, 2449 .fini = gf100_gr_fini, 2450 .reset = gf100_gr_reset, 2451 .intr = gf100_gr_intr, 2452 .units = gf100_gr_units, 2453 .chan_new = gf100_gr_chan_new, 2454 .object_get = gf100_gr_object_get, 2455 .chsw_load = gf100_gr_chsw_load, 2456 .ctxsw.pause = gf100_gr_fecs_stop_ctxsw, 2457 .ctxsw.resume = gf100_gr_fecs_start_ctxsw, 2458 .ctxsw.inst = gf100_gr_ctxsw_inst, 2459 }; 2460 2461 static const struct gf100_gr_func 2462 gf100_gr = { 2463 .oneinit_tiles = gf100_gr_oneinit_tiles, 2464 .oneinit_sm_id = gf100_gr_oneinit_sm_id, 2465 .init = gf100_gr_init, 2466 .init_gpc_mmu = gf100_gr_init_gpc_mmu, 2467 .init_vsc_stream_master = gf100_gr_init_vsc_stream_master, 2468 .init_zcull = gf100_gr_init_zcull, 2469 .init_num_active_ltcs = gf100_gr_init_num_active_ltcs, 2470 .init_fecs_exceptions = gf100_gr_init_fecs_exceptions, 2471 .init_40601c = gf100_gr_init_40601c, 2472 .init_419cc0 = gf100_gr_init_419cc0, 2473 .init_419eb4 = gf100_gr_init_419eb4, 2474 .init_tex_hww_esr = gf100_gr_init_tex_hww_esr, 2475 .init_shader_exceptions = gf100_gr_init_shader_exceptions, 2476 .init_rop_exceptions = gf100_gr_init_rop_exceptions, 2477 .init_400054 = gf100_gr_init_400054, 2478 .trap_mp = gf100_gr_trap_mp, 2479 .mmio = gf100_gr_pack_mmio, 2480 .fecs.ucode = &gf100_gr_fecs_ucode, 2481 .fecs.reset = gf100_gr_fecs_reset, 2482 .gpccs.ucode = &gf100_gr_gpccs_ucode, 2483 .rops = gf100_gr_rops, 2484 .grctx = &gf100_grctx, 2485 .zbc = &gf100_gr_zbc, 2486 .sclass = { 2487 { -1, -1, FERMI_TWOD_A }, 2488 { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A }, 2489 { -1, -1, FERMI_A, &gf100_fermi }, 2490 { -1, -1, FERMI_COMPUTE_A }, 2491 {} 2492 } 2493 }; 2494 2495 int 2496 gf100_gr_nofw(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) 2497 { 2498 gr->firmware = false; 2499 return 0; 2500 } 2501 2502 static int 2503 gf100_gr_load_fw(struct gf100_gr *gr, const char *name, 2504 struct nvkm_blob *blob) 2505 { 2506 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 2507 struct nvkm_device *device = subdev->device; 2508 const struct firmware *fw; 2509 char f[32]; 2510 int ret; 2511 2512 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, name); 2513 ret = request_firmware(&fw, f, device->dev); 2514 if (ret) { 2515 snprintf(f, sizeof(f), "nouveau/%s", name); 2516 ret = request_firmware(&fw, f, device->dev); 2517 if (ret) { 2518 nvkm_error(subdev, "failed to load %s\n", name); 2519 return ret; 2520 } 2521 } 2522 2523 blob->size = fw->size; 2524 blob->data = kmemdup(fw->data, blob->size, GFP_KERNEL); 2525 release_firmware(fw); 2526 return (blob->data != NULL) ? 0 : -ENOMEM; 2527 } 2528 2529 int 2530 gf100_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) 2531 { 2532 struct nvkm_device *device = gr->base.engine.subdev.device; 2533 2534 if (!nvkm_boolopt(device->cfgopt, "NvGrUseFW", false)) 2535 return -EINVAL; 2536 2537 if (gf100_gr_load_fw(gr, "fuc409c", &gr->fecs.inst) || 2538 gf100_gr_load_fw(gr, "fuc409d", &gr->fecs.data) || 2539 gf100_gr_load_fw(gr, "fuc41ac", &gr->gpccs.inst) || 2540 gf100_gr_load_fw(gr, "fuc41ad", &gr->gpccs.data)) 2541 return -ENOENT; 2542 2543 gr->firmware = true; 2544 return 0; 2545 } 2546 2547 static const struct gf100_gr_fwif 2548 gf100_gr_fwif[] = { 2549 { -1, gf100_gr_load, &gf100_gr }, 2550 { -1, gf100_gr_nofw, &gf100_gr }, 2551 {} 2552 }; 2553 2554 int 2555 gf100_gr_new_(const struct gf100_gr_fwif *fwif, struct nvkm_device *device, 2556 enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) 2557 { 2558 struct gf100_gr *gr; 2559 int ret; 2560 2561 if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) 2562 return -ENOMEM; 2563 *pgr = &gr->base; 2564 2565 ret = nvkm_gr_ctor(&gf100_gr_, device, type, inst, true, &gr->base); 2566 if (ret) 2567 return ret; 2568 2569 fwif = nvkm_firmware_load(&gr->base.engine.subdev, fwif, "Gr", gr); 2570 if (IS_ERR(fwif)) 2571 return PTR_ERR(fwif); 2572 2573 gr->func = fwif->func; 2574 2575 ret = nvkm_falcon_ctor(&gf100_gr_flcn, &gr->base.engine.subdev, 2576 "fecs", 0x409000, &gr->fecs.falcon); 2577 if (ret) 2578 return ret; 2579 2580 mutex_init(&gr->fecs.mutex); 2581 2582 ret = nvkm_falcon_ctor(&gf100_gr_flcn, &gr->base.engine.subdev, 2583 "gpccs", 0x41a000, &gr->gpccs.falcon); 2584 if (ret) 2585 return ret; 2586 2587 return 0; 2588 } 2589 2590 int 2591 gf100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) 2592 { 2593 return gf100_gr_new_(gf100_gr_fwif, device, type, inst, pgr); 2594 } 2595