1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "gf100.h" 25 #include "ctxgf100.h" 26 #include "fuc/os.h" 27 28 #include <core/client.h> 29 #include <core/option.h> 30 #include <core/firmware.h> 31 #include <subdev/secboot.h> 32 #include <subdev/fb.h> 33 #include <subdev/mc.h> 34 #include <subdev/pmu.h> 35 #include <subdev/therm.h> 36 #include <subdev/timer.h> 37 #include <engine/fifo.h> 38 39 #include <nvif/class.h> 40 #include <nvif/cl9097.h> 41 #include <nvif/if900d.h> 42 #include <nvif/unpack.h> 43 44 /******************************************************************************* 45 * Zero Bandwidth Clear 46 ******************************************************************************/ 47 48 static void 49 gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) 50 { 51 struct nvkm_device *device = gr->base.engine.subdev.device; 52 if (gr->zbc_color[zbc].format) { 53 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); 54 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); 55 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); 56 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); 57 } 58 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); 59 nvkm_wr32(device, 0x405820, zbc); 60 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ 61 } 62 63 static int 64 gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, 65 const u32 ds[4], const u32 l2[4]) 66 { 67 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; 68 int zbc = -ENOSPC, i; 69 70 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { 71 if (gr->zbc_color[i].format) { 72 if (gr->zbc_color[i].format != format) 73 continue; 74 if (memcmp(gr->zbc_color[i].ds, ds, sizeof( 75 gr->zbc_color[i].ds))) 76 continue; 77 if (memcmp(gr->zbc_color[i].l2, l2, sizeof( 78 gr->zbc_color[i].l2))) { 79 WARN_ON(1); 80 return -EINVAL; 81 } 82 return i; 83 } else { 84 zbc = (zbc < 0) ? i : zbc; 85 } 86 } 87 88 if (zbc < 0) 89 return zbc; 90 91 memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); 92 memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); 93 gr->zbc_color[zbc].format = format; 94 nvkm_ltc_zbc_color_get(ltc, zbc, l2); 95 gf100_gr_zbc_clear_color(gr, zbc); 96 return zbc; 97 } 98 99 static void 100 gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) 101 { 102 struct nvkm_device *device = gr->base.engine.subdev.device; 103 if (gr->zbc_depth[zbc].format) 104 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); 105 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); 106 nvkm_wr32(device, 0x405820, zbc); 107 nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ 108 } 109 110 static int 111 gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, 112 const u32 ds, const u32 l2) 113 { 114 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; 115 int zbc = -ENOSPC, i; 116 117 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { 118 if (gr->zbc_depth[i].format) { 119 if (gr->zbc_depth[i].format != format) 120 continue; 121 if (gr->zbc_depth[i].ds != ds) 122 continue; 123 if (gr->zbc_depth[i].l2 != l2) { 124 WARN_ON(1); 125 return -EINVAL; 126 } 127 return i; 128 } else { 129 zbc = (zbc < 0) ? i : zbc; 130 } 131 } 132 133 if (zbc < 0) 134 return zbc; 135 136 gr->zbc_depth[zbc].format = format; 137 gr->zbc_depth[zbc].ds = ds; 138 gr->zbc_depth[zbc].l2 = l2; 139 nvkm_ltc_zbc_depth_get(ltc, zbc, l2); 140 gf100_gr_zbc_clear_depth(gr, zbc); 141 return zbc; 142 } 143 144 /******************************************************************************* 145 * Graphics object classes 146 ******************************************************************************/ 147 #define gf100_gr_object(p) container_of((p), struct gf100_gr_object, object) 148 149 struct gf100_gr_object { 150 struct nvkm_object object; 151 struct gf100_gr_chan *chan; 152 }; 153 154 static int 155 gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) 156 { 157 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); 158 union { 159 struct fermi_a_zbc_color_v0 v0; 160 } *args = data; 161 int ret = -ENOSYS; 162 163 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { 164 switch (args->v0.format) { 165 case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: 166 case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: 167 case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32: 168 case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16: 169 case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16: 170 case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16: 171 case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16: 172 case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16: 173 case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8: 174 case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8: 175 case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10: 176 case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10: 177 case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8: 178 case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8: 179 case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8: 180 case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8: 181 case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: 182 case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: 183 case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: 184 ret = gf100_gr_zbc_color_get(gr, args->v0.format, 185 args->v0.ds, 186 args->v0.l2); 187 if (ret >= 0) { 188 args->v0.index = ret; 189 return 0; 190 } 191 break; 192 default: 193 return -EINVAL; 194 } 195 } 196 197 return ret; 198 } 199 200 static int 201 gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) 202 { 203 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); 204 union { 205 struct fermi_a_zbc_depth_v0 v0; 206 } *args = data; 207 int ret = -ENOSYS; 208 209 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { 210 switch (args->v0.format) { 211 case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: 212 ret = gf100_gr_zbc_depth_get(gr, args->v0.format, 213 args->v0.ds, 214 args->v0.l2); 215 return (ret >= 0) ? 0 : -ENOSPC; 216 default: 217 return -EINVAL; 218 } 219 } 220 221 return ret; 222 } 223 224 static int 225 gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) 226 { 227 nvif_ioctl(object, "fermi mthd %08x\n", mthd); 228 switch (mthd) { 229 case FERMI_A_ZBC_COLOR: 230 return gf100_fermi_mthd_zbc_color(object, data, size); 231 case FERMI_A_ZBC_DEPTH: 232 return gf100_fermi_mthd_zbc_depth(object, data, size); 233 default: 234 break; 235 } 236 return -EINVAL; 237 } 238 239 const struct nvkm_object_func 240 gf100_fermi = { 241 .mthd = gf100_fermi_mthd, 242 }; 243 244 static void 245 gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data) 246 { 247 nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000); 248 nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000); 249 } 250 251 static bool 252 gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data) 253 { 254 switch (class & 0x00ff) { 255 case 0x97: 256 case 0xc0: 257 switch (mthd) { 258 case 0x1528: 259 gf100_gr_mthd_set_shader_exceptions(device, data); 260 return true; 261 default: 262 break; 263 } 264 break; 265 default: 266 break; 267 } 268 return false; 269 } 270 271 static const struct nvkm_object_func 272 gf100_gr_object_func = { 273 }; 274 275 static int 276 gf100_gr_object_new(const struct nvkm_oclass *oclass, void *data, u32 size, 277 struct nvkm_object **pobject) 278 { 279 struct gf100_gr_chan *chan = gf100_gr_chan(oclass->parent); 280 struct gf100_gr_object *object; 281 282 if (!(object = kzalloc(sizeof(*object), GFP_KERNEL))) 283 return -ENOMEM; 284 *pobject = &object->object; 285 286 nvkm_object_ctor(oclass->base.func ? oclass->base.func : 287 &gf100_gr_object_func, oclass, &object->object); 288 object->chan = chan; 289 return 0; 290 } 291 292 static int 293 gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass) 294 { 295 struct gf100_gr *gr = gf100_gr(base); 296 int c = 0; 297 298 while (gr->func->sclass[c].oclass) { 299 if (c++ == index) { 300 *sclass = gr->func->sclass[index]; 301 sclass->ctor = gf100_gr_object_new; 302 return index; 303 } 304 } 305 306 return c; 307 } 308 309 /******************************************************************************* 310 * PGRAPH context 311 ******************************************************************************/ 312 313 static int 314 gf100_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, 315 int align, struct nvkm_gpuobj **pgpuobj) 316 { 317 struct gf100_gr_chan *chan = gf100_gr_chan(object); 318 struct gf100_gr *gr = chan->gr; 319 int ret, i; 320 321 ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, 322 align, false, parent, pgpuobj); 323 if (ret) 324 return ret; 325 326 nvkm_kmap(*pgpuobj); 327 for (i = 0; i < gr->size; i += 4) 328 nvkm_wo32(*pgpuobj, i, gr->data[i / 4]); 329 330 if (!gr->firmware) { 331 nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2); 332 nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma->addr >> 8); 333 } else { 334 nvkm_wo32(*pgpuobj, 0xf4, 0); 335 nvkm_wo32(*pgpuobj, 0xf8, 0); 336 nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2); 337 nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma->addr)); 338 nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma->addr)); 339 nvkm_wo32(*pgpuobj, 0x1c, 1); 340 nvkm_wo32(*pgpuobj, 0x20, 0); 341 nvkm_wo32(*pgpuobj, 0x28, 0); 342 nvkm_wo32(*pgpuobj, 0x2c, 0); 343 } 344 nvkm_done(*pgpuobj); 345 return 0; 346 } 347 348 static void * 349 gf100_gr_chan_dtor(struct nvkm_object *object) 350 { 351 struct gf100_gr_chan *chan = gf100_gr_chan(object); 352 int i; 353 354 for (i = 0; i < ARRAY_SIZE(chan->data); i++) { 355 nvkm_vmm_put(chan->vmm, &chan->data[i].vma); 356 nvkm_memory_unref(&chan->data[i].mem); 357 } 358 359 nvkm_vmm_put(chan->vmm, &chan->mmio_vma); 360 nvkm_memory_unref(&chan->mmio); 361 nvkm_vmm_unref(&chan->vmm); 362 return chan; 363 } 364 365 static const struct nvkm_object_func 366 gf100_gr_chan = { 367 .dtor = gf100_gr_chan_dtor, 368 .bind = gf100_gr_chan_bind, 369 }; 370 371 static int 372 gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, 373 const struct nvkm_oclass *oclass, 374 struct nvkm_object **pobject) 375 { 376 struct gf100_gr *gr = gf100_gr(base); 377 struct gf100_gr_data *data = gr->mmio_data; 378 struct gf100_gr_mmio *mmio = gr->mmio_list; 379 struct gf100_gr_chan *chan; 380 struct gf100_vmm_map_v0 args = { .priv = 1 }; 381 struct nvkm_device *device = gr->base.engine.subdev.device; 382 int ret, i; 383 384 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) 385 return -ENOMEM; 386 nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object); 387 chan->gr = gr; 388 chan->vmm = nvkm_vmm_ref(fifoch->vmm); 389 *pobject = &chan->object; 390 391 /* allocate memory for a "mmio list" buffer that's used by the HUB 392 * fuc to modify some per-context register settings on first load 393 * of the context. 394 */ 395 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100, 396 false, &chan->mmio); 397 if (ret) 398 return ret; 399 400 ret = nvkm_vmm_get(fifoch->vmm, 12, 0x1000, &chan->mmio_vma); 401 if (ret) 402 return ret; 403 404 ret = nvkm_memory_map(chan->mmio, 0, fifoch->vmm, 405 chan->mmio_vma, &args, sizeof(args)); 406 if (ret) 407 return ret; 408 409 /* allocate buffers referenced by mmio list */ 410 for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) { 411 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 412 data->size, data->align, false, 413 &chan->data[i].mem); 414 if (ret) 415 return ret; 416 417 ret = nvkm_vmm_get(fifoch->vmm, 12, 418 nvkm_memory_size(chan->data[i].mem), 419 &chan->data[i].vma); 420 if (ret) 421 return ret; 422 423 args.priv = data->priv; 424 425 ret = nvkm_memory_map(chan->data[i].mem, 0, chan->vmm, 426 chan->data[i].vma, &args, sizeof(args)); 427 if (ret) 428 return ret; 429 430 data++; 431 } 432 433 /* finally, fill in the mmio list and point the context at it */ 434 nvkm_kmap(chan->mmio); 435 for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) { 436 u32 addr = mmio->addr; 437 u32 data = mmio->data; 438 439 if (mmio->buffer >= 0) { 440 u64 info = chan->data[mmio->buffer].vma->addr; 441 data |= info >> mmio->shift; 442 } 443 444 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); 445 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data); 446 mmio++; 447 } 448 nvkm_done(chan->mmio); 449 return 0; 450 } 451 452 /******************************************************************************* 453 * PGRAPH register lists 454 ******************************************************************************/ 455 456 const struct gf100_gr_init 457 gf100_gr_init_main_0[] = { 458 { 0x400080, 1, 0x04, 0x003083c2 }, 459 { 0x400088, 1, 0x04, 0x00006fe7 }, 460 { 0x40008c, 1, 0x04, 0x00000000 }, 461 { 0x400090, 1, 0x04, 0x00000030 }, 462 { 0x40013c, 1, 0x04, 0x013901f7 }, 463 { 0x400140, 1, 0x04, 0x00000100 }, 464 { 0x400144, 1, 0x04, 0x00000000 }, 465 { 0x400148, 1, 0x04, 0x00000110 }, 466 { 0x400138, 1, 0x04, 0x00000000 }, 467 { 0x400130, 2, 0x04, 0x00000000 }, 468 { 0x400124, 1, 0x04, 0x00000002 }, 469 {} 470 }; 471 472 const struct gf100_gr_init 473 gf100_gr_init_fe_0[] = { 474 { 0x40415c, 1, 0x04, 0x00000000 }, 475 { 0x404170, 1, 0x04, 0x00000000 }, 476 {} 477 }; 478 479 const struct gf100_gr_init 480 gf100_gr_init_pri_0[] = { 481 { 0x404488, 2, 0x04, 0x00000000 }, 482 {} 483 }; 484 485 const struct gf100_gr_init 486 gf100_gr_init_rstr2d_0[] = { 487 { 0x407808, 1, 0x04, 0x00000000 }, 488 {} 489 }; 490 491 const struct gf100_gr_init 492 gf100_gr_init_pd_0[] = { 493 { 0x406024, 1, 0x04, 0x00000000 }, 494 {} 495 }; 496 497 const struct gf100_gr_init 498 gf100_gr_init_ds_0[] = { 499 { 0x405844, 1, 0x04, 0x00ffffff }, 500 { 0x405850, 1, 0x04, 0x00000000 }, 501 { 0x405908, 1, 0x04, 0x00000000 }, 502 {} 503 }; 504 505 const struct gf100_gr_init 506 gf100_gr_init_scc_0[] = { 507 { 0x40803c, 1, 0x04, 0x00000000 }, 508 {} 509 }; 510 511 const struct gf100_gr_init 512 gf100_gr_init_prop_0[] = { 513 { 0x4184a0, 1, 0x04, 0x00000000 }, 514 {} 515 }; 516 517 const struct gf100_gr_init 518 gf100_gr_init_gpc_unk_0[] = { 519 { 0x418604, 1, 0x04, 0x00000000 }, 520 { 0x418680, 1, 0x04, 0x00000000 }, 521 { 0x418714, 1, 0x04, 0x80000000 }, 522 { 0x418384, 1, 0x04, 0x00000000 }, 523 {} 524 }; 525 526 const struct gf100_gr_init 527 gf100_gr_init_setup_0[] = { 528 { 0x418814, 3, 0x04, 0x00000000 }, 529 {} 530 }; 531 532 const struct gf100_gr_init 533 gf100_gr_init_crstr_0[] = { 534 { 0x418b04, 1, 0x04, 0x00000000 }, 535 {} 536 }; 537 538 const struct gf100_gr_init 539 gf100_gr_init_setup_1[] = { 540 { 0x4188c8, 1, 0x04, 0x80000000 }, 541 { 0x4188cc, 1, 0x04, 0x00000000 }, 542 { 0x4188d0, 1, 0x04, 0x00010000 }, 543 { 0x4188d4, 1, 0x04, 0x00000001 }, 544 {} 545 }; 546 547 const struct gf100_gr_init 548 gf100_gr_init_zcull_0[] = { 549 { 0x418910, 1, 0x04, 0x00010001 }, 550 { 0x418914, 1, 0x04, 0x00000301 }, 551 { 0x418918, 1, 0x04, 0x00800000 }, 552 { 0x418980, 1, 0x04, 0x77777770 }, 553 { 0x418984, 3, 0x04, 0x77777777 }, 554 {} 555 }; 556 557 const struct gf100_gr_init 558 gf100_gr_init_gpm_0[] = { 559 { 0x418c04, 1, 0x04, 0x00000000 }, 560 { 0x418c88, 1, 0x04, 0x00000000 }, 561 {} 562 }; 563 564 const struct gf100_gr_init 565 gf100_gr_init_gpc_unk_1[] = { 566 { 0x418d00, 1, 0x04, 0x00000000 }, 567 { 0x418f08, 1, 0x04, 0x00000000 }, 568 { 0x418e00, 1, 0x04, 0x00000050 }, 569 { 0x418e08, 1, 0x04, 0x00000000 }, 570 {} 571 }; 572 573 const struct gf100_gr_init 574 gf100_gr_init_gcc_0[] = { 575 { 0x41900c, 1, 0x04, 0x00000000 }, 576 { 0x419018, 1, 0x04, 0x00000000 }, 577 {} 578 }; 579 580 const struct gf100_gr_init 581 gf100_gr_init_tpccs_0[] = { 582 { 0x419d08, 2, 0x04, 0x00000000 }, 583 { 0x419d10, 1, 0x04, 0x00000014 }, 584 {} 585 }; 586 587 const struct gf100_gr_init 588 gf100_gr_init_tex_0[] = { 589 { 0x419ab0, 1, 0x04, 0x00000000 }, 590 { 0x419ab8, 1, 0x04, 0x000000e7 }, 591 { 0x419abc, 2, 0x04, 0x00000000 }, 592 {} 593 }; 594 595 const struct gf100_gr_init 596 gf100_gr_init_pe_0[] = { 597 { 0x41980c, 3, 0x04, 0x00000000 }, 598 { 0x419844, 1, 0x04, 0x00000000 }, 599 { 0x41984c, 1, 0x04, 0x00005bc5 }, 600 { 0x419850, 4, 0x04, 0x00000000 }, 601 {} 602 }; 603 604 const struct gf100_gr_init 605 gf100_gr_init_l1c_0[] = { 606 { 0x419c98, 1, 0x04, 0x00000000 }, 607 { 0x419ca8, 1, 0x04, 0x80000000 }, 608 { 0x419cb4, 1, 0x04, 0x00000000 }, 609 { 0x419cb8, 1, 0x04, 0x00008bf4 }, 610 { 0x419cbc, 1, 0x04, 0x28137606 }, 611 { 0x419cc0, 2, 0x04, 0x00000000 }, 612 {} 613 }; 614 615 const struct gf100_gr_init 616 gf100_gr_init_wwdx_0[] = { 617 { 0x419bd4, 1, 0x04, 0x00800000 }, 618 { 0x419bdc, 1, 0x04, 0x00000000 }, 619 {} 620 }; 621 622 const struct gf100_gr_init 623 gf100_gr_init_tpccs_1[] = { 624 { 0x419d2c, 1, 0x04, 0x00000000 }, 625 {} 626 }; 627 628 const struct gf100_gr_init 629 gf100_gr_init_mpc_0[] = { 630 { 0x419c0c, 1, 0x04, 0x00000000 }, 631 {} 632 }; 633 634 static const struct gf100_gr_init 635 gf100_gr_init_sm_0[] = { 636 { 0x419e00, 1, 0x04, 0x00000000 }, 637 { 0x419ea0, 1, 0x04, 0x00000000 }, 638 { 0x419ea4, 1, 0x04, 0x00000100 }, 639 { 0x419ea8, 1, 0x04, 0x00001100 }, 640 { 0x419eac, 1, 0x04, 0x11100702 }, 641 { 0x419eb0, 1, 0x04, 0x00000003 }, 642 { 0x419eb4, 4, 0x04, 0x00000000 }, 643 { 0x419ec8, 1, 0x04, 0x06060618 }, 644 { 0x419ed0, 1, 0x04, 0x0eff0e38 }, 645 { 0x419ed4, 1, 0x04, 0x011104f1 }, 646 { 0x419edc, 1, 0x04, 0x00000000 }, 647 { 0x419f00, 1, 0x04, 0x00000000 }, 648 { 0x419f2c, 1, 0x04, 0x00000000 }, 649 {} 650 }; 651 652 const struct gf100_gr_init 653 gf100_gr_init_be_0[] = { 654 { 0x40880c, 1, 0x04, 0x00000000 }, 655 { 0x408910, 9, 0x04, 0x00000000 }, 656 { 0x408950, 1, 0x04, 0x00000000 }, 657 { 0x408954, 1, 0x04, 0x0000ffff }, 658 { 0x408984, 1, 0x04, 0x00000000 }, 659 { 0x408988, 1, 0x04, 0x08040201 }, 660 { 0x40898c, 1, 0x04, 0x80402010 }, 661 {} 662 }; 663 664 const struct gf100_gr_init 665 gf100_gr_init_fe_1[] = { 666 { 0x4040f0, 1, 0x04, 0x00000000 }, 667 {} 668 }; 669 670 const struct gf100_gr_init 671 gf100_gr_init_pe_1[] = { 672 { 0x419880, 1, 0x04, 0x00000002 }, 673 {} 674 }; 675 676 static const struct gf100_gr_pack 677 gf100_gr_pack_mmio[] = { 678 { gf100_gr_init_main_0 }, 679 { gf100_gr_init_fe_0 }, 680 { gf100_gr_init_pri_0 }, 681 { gf100_gr_init_rstr2d_0 }, 682 { gf100_gr_init_pd_0 }, 683 { gf100_gr_init_ds_0 }, 684 { gf100_gr_init_scc_0 }, 685 { gf100_gr_init_prop_0 }, 686 { gf100_gr_init_gpc_unk_0 }, 687 { gf100_gr_init_setup_0 }, 688 { gf100_gr_init_crstr_0 }, 689 { gf100_gr_init_setup_1 }, 690 { gf100_gr_init_zcull_0 }, 691 { gf100_gr_init_gpm_0 }, 692 { gf100_gr_init_gpc_unk_1 }, 693 { gf100_gr_init_gcc_0 }, 694 { gf100_gr_init_tpccs_0 }, 695 { gf100_gr_init_tex_0 }, 696 { gf100_gr_init_pe_0 }, 697 { gf100_gr_init_l1c_0 }, 698 { gf100_gr_init_wwdx_0 }, 699 { gf100_gr_init_tpccs_1 }, 700 { gf100_gr_init_mpc_0 }, 701 { gf100_gr_init_sm_0 }, 702 { gf100_gr_init_be_0 }, 703 { gf100_gr_init_fe_1 }, 704 { gf100_gr_init_pe_1 }, 705 {} 706 }; 707 708 /******************************************************************************* 709 * PGRAPH engine/subdev functions 710 ******************************************************************************/ 711 712 static bool 713 gf100_gr_chsw_load(struct nvkm_gr *base) 714 { 715 struct gf100_gr *gr = gf100_gr(base); 716 if (!gr->firmware) { 717 u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c); 718 if (trace & 0x00000040) 719 return true; 720 } else { 721 u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808); 722 if (mthd & 0x00080000) 723 return true; 724 } 725 return false; 726 } 727 728 int 729 gf100_gr_rops(struct gf100_gr *gr) 730 { 731 struct nvkm_device *device = gr->base.engine.subdev.device; 732 return (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; 733 } 734 735 void 736 gf100_gr_zbc_init(struct gf100_gr *gr) 737 { 738 const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 739 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 740 const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 741 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; 742 const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 743 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 744 const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 745 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; 746 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; 747 int index; 748 749 if (!gr->zbc_color[0].format) { 750 gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); 751 gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); 752 gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); 753 gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); 754 gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); 755 gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); 756 } 757 758 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) 759 gf100_gr_zbc_clear_color(gr, index); 760 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) 761 gf100_gr_zbc_clear_depth(gr, index); 762 } 763 764 /** 765 * Wait until GR goes idle. GR is considered idle if it is disabled by the 766 * MC (0x200) register, or GR is not busy and a context switch is not in 767 * progress. 768 */ 769 int 770 gf100_gr_wait_idle(struct gf100_gr *gr) 771 { 772 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 773 struct nvkm_device *device = subdev->device; 774 unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000); 775 bool gr_enabled, ctxsw_active, gr_busy; 776 777 do { 778 /* 779 * required to make sure FIFO_ENGINE_STATUS (0x2640) is 780 * up-to-date 781 */ 782 nvkm_rd32(device, 0x400700); 783 784 gr_enabled = nvkm_rd32(device, 0x200) & 0x1000; 785 ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000; 786 gr_busy = nvkm_rd32(device, 0x40060c) & 0x1; 787 788 if (!gr_enabled || (!gr_busy && !ctxsw_active)) 789 return 0; 790 } while (time_before(jiffies, end_jiffies)); 791 792 nvkm_error(subdev, 793 "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n", 794 gr_enabled, ctxsw_active, gr_busy); 795 return -EAGAIN; 796 } 797 798 void 799 gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) 800 { 801 struct nvkm_device *device = gr->base.engine.subdev.device; 802 const struct gf100_gr_pack *pack; 803 const struct gf100_gr_init *init; 804 805 pack_for_each_init(init, pack, p) { 806 u32 next = init->addr + init->count * init->pitch; 807 u32 addr = init->addr; 808 while (addr < next) { 809 nvkm_wr32(device, addr, init->data); 810 addr += init->pitch; 811 } 812 } 813 } 814 815 void 816 gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) 817 { 818 struct nvkm_device *device = gr->base.engine.subdev.device; 819 const struct gf100_gr_pack *pack; 820 const struct gf100_gr_init *init; 821 u32 data = 0; 822 823 nvkm_wr32(device, 0x400208, 0x80000000); 824 825 pack_for_each_init(init, pack, p) { 826 u32 next = init->addr + init->count * init->pitch; 827 u32 addr = init->addr; 828 829 if ((pack == p && init == p->init) || data != init->data) { 830 nvkm_wr32(device, 0x400204, init->data); 831 data = init->data; 832 } 833 834 while (addr < next) { 835 nvkm_wr32(device, 0x400200, addr); 836 /** 837 * Wait for GR to go idle after submitting a 838 * GO_IDLE bundle 839 */ 840 if ((addr & 0xffff) == 0xe100) 841 gf100_gr_wait_idle(gr); 842 nvkm_msec(device, 2000, 843 if (!(nvkm_rd32(device, 0x400700) & 0x00000004)) 844 break; 845 ); 846 addr += init->pitch; 847 } 848 } 849 850 nvkm_wr32(device, 0x400208, 0x00000000); 851 } 852 853 void 854 gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) 855 { 856 struct nvkm_device *device = gr->base.engine.subdev.device; 857 const struct gf100_gr_pack *pack; 858 const struct gf100_gr_init *init; 859 u32 data = 0; 860 861 pack_for_each_init(init, pack, p) { 862 u32 ctrl = 0x80000000 | pack->type; 863 u32 next = init->addr + init->count * init->pitch; 864 u32 addr = init->addr; 865 866 if ((pack == p && init == p->init) || data != init->data) { 867 nvkm_wr32(device, 0x40448c, init->data); 868 data = init->data; 869 } 870 871 while (addr < next) { 872 nvkm_wr32(device, 0x404488, ctrl | (addr << 14)); 873 addr += init->pitch; 874 } 875 } 876 } 877 878 u64 879 gf100_gr_units(struct nvkm_gr *base) 880 { 881 struct gf100_gr *gr = gf100_gr(base); 882 u64 cfg; 883 884 cfg = (u32)gr->gpc_nr; 885 cfg |= (u32)gr->tpc_total << 8; 886 cfg |= (u64)gr->rop_nr << 32; 887 888 return cfg; 889 } 890 891 static const struct nvkm_bitfield gf100_dispatch_error[] = { 892 { 0x00000001, "INJECTED_BUNDLE_ERROR" }, 893 { 0x00000002, "CLASS_SUBCH_MISMATCH" }, 894 { 0x00000004, "SUBCHSW_DURING_NOTIFY" }, 895 {} 896 }; 897 898 static const struct nvkm_bitfield gf100_m2mf_error[] = { 899 { 0x00000001, "PUSH_TOO_MUCH_DATA" }, 900 { 0x00000002, "PUSH_NOT_ENOUGH_DATA" }, 901 {} 902 }; 903 904 static const struct nvkm_bitfield gf100_unk6_error[] = { 905 { 0x00000001, "TEMP_TOO_SMALL" }, 906 {} 907 }; 908 909 static const struct nvkm_bitfield gf100_ccache_error[] = { 910 { 0x00000001, "INTR" }, 911 { 0x00000002, "LDCONST_OOB" }, 912 {} 913 }; 914 915 static const struct nvkm_bitfield gf100_macro_error[] = { 916 { 0x00000001, "TOO_FEW_PARAMS" }, 917 { 0x00000002, "TOO_MANY_PARAMS" }, 918 { 0x00000004, "ILLEGAL_OPCODE" }, 919 { 0x00000008, "DOUBLE_BRANCH" }, 920 { 0x00000010, "WATCHDOG" }, 921 {} 922 }; 923 924 static const struct nvkm_bitfield gk104_sked_error[] = { 925 { 0x00000040, "CTA_RESUME" }, 926 { 0x00000080, "CONSTANT_BUFFER_SIZE" }, 927 { 0x00000200, "LOCAL_MEMORY_SIZE_POS" }, 928 { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" }, 929 { 0x00000800, "WARP_CSTACK_SIZE" }, 930 { 0x00001000, "TOTAL_TEMP_SIZE" }, 931 { 0x00002000, "REGISTER_COUNT" }, 932 { 0x00040000, "TOTAL_THREADS" }, 933 { 0x00100000, "PROGRAM_OFFSET" }, 934 { 0x00200000, "SHARED_MEMORY_SIZE" }, 935 { 0x00800000, "CTA_THREAD_DIMENSION_ZERO" }, 936 { 0x01000000, "MEMORY_WINDOW_OVERLAP" }, 937 { 0x02000000, "SHARED_CONFIG_TOO_SMALL" }, 938 { 0x04000000, "TOTAL_REGISTER_COUNT" }, 939 {} 940 }; 941 942 static const struct nvkm_bitfield gf100_gpc_rop_error[] = { 943 { 0x00000002, "RT_PITCH_OVERRUN" }, 944 { 0x00000010, "RT_WIDTH_OVERRUN" }, 945 { 0x00000020, "RT_HEIGHT_OVERRUN" }, 946 { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" }, 947 { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" }, 948 { 0x00000400, "RT_LINEAR_MISMATCH" }, 949 {} 950 }; 951 952 static void 953 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) 954 { 955 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 956 struct nvkm_device *device = subdev->device; 957 char error[128]; 958 u32 trap[4]; 959 960 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; 961 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); 962 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); 963 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); 964 965 nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]); 966 967 nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, " 968 "format = %x, storage type = %x\n", 969 gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, 970 (trap[2] >> 8) & 0x3f, trap[3] & 0xff); 971 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); 972 } 973 974 static const struct nvkm_enum gf100_mp_warp_error[] = { 975 { 0x01, "STACK_ERROR" }, 976 { 0x02, "API_STACK_ERROR" }, 977 { 0x03, "RET_EMPTY_STACK_ERROR" }, 978 { 0x04, "PC_WRAP" }, 979 { 0x05, "MISALIGNED_PC" }, 980 { 0x06, "PC_OVERFLOW" }, 981 { 0x07, "MISALIGNED_IMMC_ADDR" }, 982 { 0x08, "MISALIGNED_REG" }, 983 { 0x09, "ILLEGAL_INSTR_ENCODING" }, 984 { 0x0a, "ILLEGAL_SPH_INSTR_COMBO" }, 985 { 0x0b, "ILLEGAL_INSTR_PARAM" }, 986 { 0x0c, "INVALID_CONST_ADDR" }, 987 { 0x0d, "OOR_REG" }, 988 { 0x0e, "OOR_ADDR" }, 989 { 0x0f, "MISALIGNED_ADDR" }, 990 { 0x10, "INVALID_ADDR_SPACE" }, 991 { 0x11, "ILLEGAL_INSTR_PARAM2" }, 992 { 0x12, "INVALID_CONST_ADDR_LDC" }, 993 { 0x13, "GEOMETRY_SM_ERROR" }, 994 { 0x14, "DIVERGENT" }, 995 { 0x15, "WARP_EXIT" }, 996 {} 997 }; 998 999 static const struct nvkm_bitfield gf100_mp_global_error[] = { 1000 { 0x00000001, "SM_TO_SM_FAULT" }, 1001 { 0x00000002, "L1_ERROR" }, 1002 { 0x00000004, "MULTIPLE_WARP_ERRORS" }, 1003 { 0x00000008, "PHYSICAL_STACK_OVERFLOW" }, 1004 { 0x00000010, "BPT_INT" }, 1005 { 0x00000020, "BPT_PAUSE" }, 1006 { 0x00000040, "SINGLE_STEP_COMPLETE" }, 1007 { 0x20000000, "ECC_SEC_ERROR" }, 1008 { 0x40000000, "ECC_DED_ERROR" }, 1009 { 0x80000000, "TIMEOUT" }, 1010 {} 1011 }; 1012 1013 static void 1014 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) 1015 { 1016 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1017 struct nvkm_device *device = subdev->device; 1018 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); 1019 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); 1020 const struct nvkm_enum *warp; 1021 char glob[128]; 1022 1023 nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr); 1024 warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff); 1025 1026 nvkm_error(subdev, "GPC%i/TPC%i/MP trap: " 1027 "global %08x [%s] warp %04x [%s]\n", 1028 gpc, tpc, gerr, glob, werr, warp ? warp->name : ""); 1029 1030 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); 1031 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); 1032 } 1033 1034 static void 1035 gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) 1036 { 1037 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1038 struct nvkm_device *device = subdev->device; 1039 u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); 1040 1041 if (stat & 0x00000001) { 1042 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); 1043 nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap); 1044 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); 1045 stat &= ~0x00000001; 1046 } 1047 1048 if (stat & 0x00000002) { 1049 gf100_gr_trap_mp(gr, gpc, tpc); 1050 stat &= ~0x00000002; 1051 } 1052 1053 if (stat & 0x00000004) { 1054 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); 1055 nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap); 1056 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); 1057 stat &= ~0x00000004; 1058 } 1059 1060 if (stat & 0x00000008) { 1061 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); 1062 nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap); 1063 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); 1064 stat &= ~0x00000008; 1065 } 1066 1067 if (stat & 0x00000010) { 1068 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0430)); 1069 nvkm_error(subdev, "GPC%d/TPC%d/MPC: %08x\n", gpc, tpc, trap); 1070 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0430), 0xc0000000); 1071 stat &= ~0x00000010; 1072 } 1073 1074 if (stat) { 1075 nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat); 1076 } 1077 } 1078 1079 static void 1080 gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) 1081 { 1082 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1083 struct nvkm_device *device = subdev->device; 1084 u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); 1085 int tpc; 1086 1087 if (stat & 0x00000001) { 1088 gf100_gr_trap_gpc_rop(gr, gpc); 1089 stat &= ~0x00000001; 1090 } 1091 1092 if (stat & 0x00000002) { 1093 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); 1094 nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap); 1095 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); 1096 stat &= ~0x00000002; 1097 } 1098 1099 if (stat & 0x00000004) { 1100 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); 1101 nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap); 1102 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); 1103 stat &= ~0x00000004; 1104 } 1105 1106 if (stat & 0x00000008) { 1107 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); 1108 nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap); 1109 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); 1110 stat &= ~0x00000009; 1111 } 1112 1113 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { 1114 u32 mask = 0x00010000 << tpc; 1115 if (stat & mask) { 1116 gf100_gr_trap_tpc(gr, gpc, tpc); 1117 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); 1118 stat &= ~mask; 1119 } 1120 } 1121 1122 if (stat) { 1123 nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat); 1124 } 1125 } 1126 1127 static void 1128 gf100_gr_trap_intr(struct gf100_gr *gr) 1129 { 1130 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1131 struct nvkm_device *device = subdev->device; 1132 char error[128]; 1133 u32 trap = nvkm_rd32(device, 0x400108); 1134 int rop, gpc; 1135 1136 if (trap & 0x00000001) { 1137 u32 stat = nvkm_rd32(device, 0x404000); 1138 1139 nvkm_snprintbf(error, sizeof(error), gf100_dispatch_error, 1140 stat & 0x3fffffff); 1141 nvkm_error(subdev, "DISPATCH %08x [%s]\n", stat, error); 1142 nvkm_wr32(device, 0x404000, 0xc0000000); 1143 nvkm_wr32(device, 0x400108, 0x00000001); 1144 trap &= ~0x00000001; 1145 } 1146 1147 if (trap & 0x00000002) { 1148 u32 stat = nvkm_rd32(device, 0x404600); 1149 1150 nvkm_snprintbf(error, sizeof(error), gf100_m2mf_error, 1151 stat & 0x3fffffff); 1152 nvkm_error(subdev, "M2MF %08x [%s]\n", stat, error); 1153 1154 nvkm_wr32(device, 0x404600, 0xc0000000); 1155 nvkm_wr32(device, 0x400108, 0x00000002); 1156 trap &= ~0x00000002; 1157 } 1158 1159 if (trap & 0x00000008) { 1160 u32 stat = nvkm_rd32(device, 0x408030); 1161 1162 nvkm_snprintbf(error, sizeof(error), gf100_ccache_error, 1163 stat & 0x3fffffff); 1164 nvkm_error(subdev, "CCACHE %08x [%s]\n", stat, error); 1165 nvkm_wr32(device, 0x408030, 0xc0000000); 1166 nvkm_wr32(device, 0x400108, 0x00000008); 1167 trap &= ~0x00000008; 1168 } 1169 1170 if (trap & 0x00000010) { 1171 u32 stat = nvkm_rd32(device, 0x405840); 1172 nvkm_error(subdev, "SHADER %08x, sph: 0x%06x, stage: 0x%02x\n", 1173 stat, stat & 0xffffff, (stat >> 24) & 0x3f); 1174 nvkm_wr32(device, 0x405840, 0xc0000000); 1175 nvkm_wr32(device, 0x400108, 0x00000010); 1176 trap &= ~0x00000010; 1177 } 1178 1179 if (trap & 0x00000040) { 1180 u32 stat = nvkm_rd32(device, 0x40601c); 1181 1182 nvkm_snprintbf(error, sizeof(error), gf100_unk6_error, 1183 stat & 0x3fffffff); 1184 nvkm_error(subdev, "UNK6 %08x [%s]\n", stat, error); 1185 1186 nvkm_wr32(device, 0x40601c, 0xc0000000); 1187 nvkm_wr32(device, 0x400108, 0x00000040); 1188 trap &= ~0x00000040; 1189 } 1190 1191 if (trap & 0x00000080) { 1192 u32 stat = nvkm_rd32(device, 0x404490); 1193 u32 pc = nvkm_rd32(device, 0x404494); 1194 u32 op = nvkm_rd32(device, 0x40449c); 1195 1196 nvkm_snprintbf(error, sizeof(error), gf100_macro_error, 1197 stat & 0x1fffffff); 1198 nvkm_error(subdev, "MACRO %08x [%s], pc: 0x%03x%s, op: 0x%08x\n", 1199 stat, error, pc & 0x7ff, 1200 (pc & 0x10000000) ? "" : " (invalid)", 1201 op); 1202 1203 nvkm_wr32(device, 0x404490, 0xc0000000); 1204 nvkm_wr32(device, 0x400108, 0x00000080); 1205 trap &= ~0x00000080; 1206 } 1207 1208 if (trap & 0x00000100) { 1209 u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff; 1210 1211 nvkm_snprintbf(error, sizeof(error), gk104_sked_error, stat); 1212 nvkm_error(subdev, "SKED: %08x [%s]\n", stat, error); 1213 1214 if (stat) 1215 nvkm_wr32(device, 0x407020, 0x40000000); 1216 nvkm_wr32(device, 0x400108, 0x00000100); 1217 trap &= ~0x00000100; 1218 } 1219 1220 if (trap & 0x01000000) { 1221 u32 stat = nvkm_rd32(device, 0x400118); 1222 for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { 1223 u32 mask = 0x00000001 << gpc; 1224 if (stat & mask) { 1225 gf100_gr_trap_gpc(gr, gpc); 1226 nvkm_wr32(device, 0x400118, mask); 1227 stat &= ~mask; 1228 } 1229 } 1230 nvkm_wr32(device, 0x400108, 0x01000000); 1231 trap &= ~0x01000000; 1232 } 1233 1234 if (trap & 0x02000000) { 1235 for (rop = 0; rop < gr->rop_nr; rop++) { 1236 u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); 1237 u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); 1238 nvkm_error(subdev, "ROP%d %08x %08x\n", 1239 rop, statz, statc); 1240 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); 1241 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); 1242 } 1243 nvkm_wr32(device, 0x400108, 0x02000000); 1244 trap &= ~0x02000000; 1245 } 1246 1247 if (trap) { 1248 nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap); 1249 nvkm_wr32(device, 0x400108, trap); 1250 } 1251 } 1252 1253 static void 1254 gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) 1255 { 1256 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1257 struct nvkm_device *device = subdev->device; 1258 nvkm_error(subdev, "%06x - done %08x\n", base, 1259 nvkm_rd32(device, base + 0x400)); 1260 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, 1261 nvkm_rd32(device, base + 0x800), 1262 nvkm_rd32(device, base + 0x804), 1263 nvkm_rd32(device, base + 0x808), 1264 nvkm_rd32(device, base + 0x80c)); 1265 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, 1266 nvkm_rd32(device, base + 0x810), 1267 nvkm_rd32(device, base + 0x814), 1268 nvkm_rd32(device, base + 0x818), 1269 nvkm_rd32(device, base + 0x81c)); 1270 } 1271 1272 void 1273 gf100_gr_ctxctl_debug(struct gf100_gr *gr) 1274 { 1275 struct nvkm_device *device = gr->base.engine.subdev.device; 1276 u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff; 1277 u32 gpc; 1278 1279 gf100_gr_ctxctl_debug_unit(gr, 0x409000); 1280 for (gpc = 0; gpc < gpcnr; gpc++) 1281 gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000)); 1282 } 1283 1284 static void 1285 gf100_gr_ctxctl_isr(struct gf100_gr *gr) 1286 { 1287 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1288 struct nvkm_device *device = subdev->device; 1289 u32 stat = nvkm_rd32(device, 0x409c18); 1290 1291 if (!gr->firmware && (stat & 0x00000001)) { 1292 u32 code = nvkm_rd32(device, 0x409814); 1293 if (code == E_BAD_FWMTHD) { 1294 u32 class = nvkm_rd32(device, 0x409808); 1295 u32 addr = nvkm_rd32(device, 0x40980c); 1296 u32 subc = (addr & 0x00070000) >> 16; 1297 u32 mthd = (addr & 0x00003ffc); 1298 u32 data = nvkm_rd32(device, 0x409810); 1299 1300 nvkm_error(subdev, "FECS MTHD subc %d class %04x " 1301 "mthd %04x data %08x\n", 1302 subc, class, mthd, data); 1303 } else { 1304 nvkm_error(subdev, "FECS ucode error %d\n", code); 1305 } 1306 nvkm_wr32(device, 0x409c20, 0x00000001); 1307 stat &= ~0x00000001; 1308 } 1309 1310 if (!gr->firmware && (stat & 0x00080000)) { 1311 nvkm_error(subdev, "FECS watchdog timeout\n"); 1312 gf100_gr_ctxctl_debug(gr); 1313 nvkm_wr32(device, 0x409c20, 0x00080000); 1314 stat &= ~0x00080000; 1315 } 1316 1317 if (stat) { 1318 nvkm_error(subdev, "FECS %08x\n", stat); 1319 gf100_gr_ctxctl_debug(gr); 1320 nvkm_wr32(device, 0x409c20, stat); 1321 } 1322 } 1323 1324 static void 1325 gf100_gr_intr(struct nvkm_gr *base) 1326 { 1327 struct gf100_gr *gr = gf100_gr(base); 1328 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1329 struct nvkm_device *device = subdev->device; 1330 struct nvkm_fifo_chan *chan; 1331 unsigned long flags; 1332 u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; 1333 u32 stat = nvkm_rd32(device, 0x400100); 1334 u32 addr = nvkm_rd32(device, 0x400704); 1335 u32 mthd = (addr & 0x00003ffc); 1336 u32 subc = (addr & 0x00070000) >> 16; 1337 u32 data = nvkm_rd32(device, 0x400708); 1338 u32 code = nvkm_rd32(device, 0x400110); 1339 u32 class; 1340 const char *name = "unknown"; 1341 int chid = -1; 1342 1343 chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags); 1344 if (chan) { 1345 name = chan->object.client->name; 1346 chid = chan->chid; 1347 } 1348 1349 if (device->card_type < NV_E0 || subc < 4) 1350 class = nvkm_rd32(device, 0x404200 + (subc * 4)); 1351 else 1352 class = 0x0000; 1353 1354 if (stat & 0x00000001) { 1355 /* 1356 * notifier interrupt, only needed for cyclestats 1357 * can be safely ignored 1358 */ 1359 nvkm_wr32(device, 0x400100, 0x00000001); 1360 stat &= ~0x00000001; 1361 } 1362 1363 if (stat & 0x00000010) { 1364 if (!gf100_gr_mthd_sw(device, class, mthd, data)) { 1365 nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] " 1366 "subc %d class %04x mthd %04x data %08x\n", 1367 chid, inst << 12, name, subc, 1368 class, mthd, data); 1369 } 1370 nvkm_wr32(device, 0x400100, 0x00000010); 1371 stat &= ~0x00000010; 1372 } 1373 1374 if (stat & 0x00000020) { 1375 nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] " 1376 "subc %d class %04x mthd %04x data %08x\n", 1377 chid, inst << 12, name, subc, class, mthd, data); 1378 nvkm_wr32(device, 0x400100, 0x00000020); 1379 stat &= ~0x00000020; 1380 } 1381 1382 if (stat & 0x00100000) { 1383 const struct nvkm_enum *en = 1384 nvkm_enum_find(nv50_data_error_names, code); 1385 nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] " 1386 "subc %d class %04x mthd %04x data %08x\n", 1387 code, en ? en->name : "", chid, inst << 12, 1388 name, subc, class, mthd, data); 1389 nvkm_wr32(device, 0x400100, 0x00100000); 1390 stat &= ~0x00100000; 1391 } 1392 1393 if (stat & 0x00200000) { 1394 nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n", 1395 chid, inst << 12, name); 1396 gf100_gr_trap_intr(gr); 1397 nvkm_wr32(device, 0x400100, 0x00200000); 1398 stat &= ~0x00200000; 1399 } 1400 1401 if (stat & 0x00080000) { 1402 gf100_gr_ctxctl_isr(gr); 1403 nvkm_wr32(device, 0x400100, 0x00080000); 1404 stat &= ~0x00080000; 1405 } 1406 1407 if (stat) { 1408 nvkm_error(subdev, "intr %08x\n", stat); 1409 nvkm_wr32(device, 0x400100, stat); 1410 } 1411 1412 nvkm_wr32(device, 0x400500, 0x00010001); 1413 nvkm_fifo_chan_put(device->fifo, flags, &chan); 1414 } 1415 1416 static void 1417 gf100_gr_init_fw(struct nvkm_falcon *falcon, 1418 struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) 1419 { 1420 nvkm_falcon_load_dmem(falcon, data->data, 0x0, data->size, 0); 1421 nvkm_falcon_load_imem(falcon, code->data, 0x0, code->size, 0, 0, false); 1422 } 1423 1424 static void 1425 gf100_gr_init_csdata(struct gf100_gr *gr, 1426 const struct gf100_gr_pack *pack, 1427 u32 falcon, u32 starstar, u32 base) 1428 { 1429 struct nvkm_device *device = gr->base.engine.subdev.device; 1430 const struct gf100_gr_pack *iter; 1431 const struct gf100_gr_init *init; 1432 u32 addr = ~0, prev = ~0, xfer = 0; 1433 u32 star, temp; 1434 1435 nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar); 1436 star = nvkm_rd32(device, falcon + 0x01c4); 1437 temp = nvkm_rd32(device, falcon + 0x01c4); 1438 if (temp > star) 1439 star = temp; 1440 nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star); 1441 1442 pack_for_each_init(init, iter, pack) { 1443 u32 head = init->addr - base; 1444 u32 tail = head + init->count * init->pitch; 1445 while (head < tail) { 1446 if (head != prev + 4 || xfer >= 32) { 1447 if (xfer) { 1448 u32 data = ((--xfer << 26) | addr); 1449 nvkm_wr32(device, falcon + 0x01c4, data); 1450 star += 4; 1451 } 1452 addr = head; 1453 xfer = 0; 1454 } 1455 prev = head; 1456 xfer = xfer + 1; 1457 head = head + init->pitch; 1458 } 1459 } 1460 1461 nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr); 1462 nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar); 1463 nvkm_wr32(device, falcon + 0x01c4, star + 4); 1464 } 1465 1466 /* Initialize context from an external (secure or not) firmware */ 1467 static int 1468 gf100_gr_init_ctxctl_ext(struct gf100_gr *gr) 1469 { 1470 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1471 struct nvkm_device *device = subdev->device; 1472 struct nvkm_secboot *sb = device->secboot; 1473 u32 secboot_mask = 0; 1474 1475 /* load fuc microcode */ 1476 nvkm_mc_unk260(device, 0); 1477 1478 /* securely-managed falcons must be reset using secure boot */ 1479 if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS)) 1480 secboot_mask |= BIT(NVKM_SECBOOT_FALCON_FECS); 1481 else 1482 gf100_gr_init_fw(gr->fecs, &gr->fuc409c, &gr->fuc409d); 1483 1484 if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS)) 1485 secboot_mask |= BIT(NVKM_SECBOOT_FALCON_GPCCS); 1486 else 1487 gf100_gr_init_fw(gr->gpccs, &gr->fuc41ac, &gr->fuc41ad); 1488 1489 if (secboot_mask != 0) { 1490 int ret = nvkm_secboot_reset(sb, secboot_mask); 1491 if (ret) 1492 return ret; 1493 } 1494 1495 nvkm_mc_unk260(device, 1); 1496 1497 /* start both of them running */ 1498 nvkm_wr32(device, 0x409840, 0xffffffff); 1499 nvkm_wr32(device, 0x41a10c, 0x00000000); 1500 nvkm_wr32(device, 0x40910c, 0x00000000); 1501 1502 nvkm_falcon_start(gr->gpccs); 1503 nvkm_falcon_start(gr->fecs); 1504 1505 if (nvkm_msec(device, 2000, 1506 if (nvkm_rd32(device, 0x409800) & 0x00000001) 1507 break; 1508 ) < 0) 1509 return -EBUSY; 1510 1511 nvkm_wr32(device, 0x409840, 0xffffffff); 1512 nvkm_wr32(device, 0x409500, 0x7fffffff); 1513 nvkm_wr32(device, 0x409504, 0x00000021); 1514 1515 nvkm_wr32(device, 0x409840, 0xffffffff); 1516 nvkm_wr32(device, 0x409500, 0x00000000); 1517 nvkm_wr32(device, 0x409504, 0x00000010); 1518 if (nvkm_msec(device, 2000, 1519 if ((gr->size = nvkm_rd32(device, 0x409800))) 1520 break; 1521 ) < 0) 1522 return -EBUSY; 1523 1524 nvkm_wr32(device, 0x409840, 0xffffffff); 1525 nvkm_wr32(device, 0x409500, 0x00000000); 1526 nvkm_wr32(device, 0x409504, 0x00000016); 1527 if (nvkm_msec(device, 2000, 1528 if (nvkm_rd32(device, 0x409800)) 1529 break; 1530 ) < 0) 1531 return -EBUSY; 1532 1533 nvkm_wr32(device, 0x409840, 0xffffffff); 1534 nvkm_wr32(device, 0x409500, 0x00000000); 1535 nvkm_wr32(device, 0x409504, 0x00000025); 1536 if (nvkm_msec(device, 2000, 1537 if (nvkm_rd32(device, 0x409800)) 1538 break; 1539 ) < 0) 1540 return -EBUSY; 1541 1542 if (device->chipset >= 0xe0) { 1543 nvkm_wr32(device, 0x409800, 0x00000000); 1544 nvkm_wr32(device, 0x409500, 0x00000001); 1545 nvkm_wr32(device, 0x409504, 0x00000030); 1546 if (nvkm_msec(device, 2000, 1547 if (nvkm_rd32(device, 0x409800)) 1548 break; 1549 ) < 0) 1550 return -EBUSY; 1551 1552 nvkm_wr32(device, 0x409810, 0xb00095c8); 1553 nvkm_wr32(device, 0x409800, 0x00000000); 1554 nvkm_wr32(device, 0x409500, 0x00000001); 1555 nvkm_wr32(device, 0x409504, 0x00000031); 1556 if (nvkm_msec(device, 2000, 1557 if (nvkm_rd32(device, 0x409800)) 1558 break; 1559 ) < 0) 1560 return -EBUSY; 1561 1562 nvkm_wr32(device, 0x409810, 0x00080420); 1563 nvkm_wr32(device, 0x409800, 0x00000000); 1564 nvkm_wr32(device, 0x409500, 0x00000001); 1565 nvkm_wr32(device, 0x409504, 0x00000032); 1566 if (nvkm_msec(device, 2000, 1567 if (nvkm_rd32(device, 0x409800)) 1568 break; 1569 ) < 0) 1570 return -EBUSY; 1571 1572 nvkm_wr32(device, 0x409614, 0x00000070); 1573 nvkm_wr32(device, 0x409614, 0x00000770); 1574 nvkm_wr32(device, 0x40802c, 0x00000001); 1575 } 1576 1577 if (gr->data == NULL) { 1578 int ret = gf100_grctx_generate(gr); 1579 if (ret) { 1580 nvkm_error(subdev, "failed to construct context\n"); 1581 return ret; 1582 } 1583 } 1584 1585 return 0; 1586 } 1587 1588 static int 1589 gf100_gr_init_ctxctl_int(struct gf100_gr *gr) 1590 { 1591 const struct gf100_grctx_func *grctx = gr->func->grctx; 1592 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1593 struct nvkm_device *device = subdev->device; 1594 1595 if (!gr->func->fecs.ucode) { 1596 return -ENOSYS; 1597 } 1598 1599 /* load HUB microcode */ 1600 nvkm_mc_unk260(device, 0); 1601 nvkm_falcon_load_dmem(gr->fecs, gr->func->fecs.ucode->data.data, 0x0, 1602 gr->func->fecs.ucode->data.size, 0); 1603 nvkm_falcon_load_imem(gr->fecs, gr->func->fecs.ucode->code.data, 0x0, 1604 gr->func->fecs.ucode->code.size, 0, 0, false); 1605 1606 /* load GPC microcode */ 1607 nvkm_falcon_load_dmem(gr->gpccs, gr->func->gpccs.ucode->data.data, 0x0, 1608 gr->func->gpccs.ucode->data.size, 0); 1609 nvkm_falcon_load_imem(gr->gpccs, gr->func->gpccs.ucode->code.data, 0x0, 1610 gr->func->gpccs.ucode->code.size, 0, 0, false); 1611 nvkm_mc_unk260(device, 1); 1612 1613 /* load register lists */ 1614 gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000); 1615 gf100_gr_init_csdata(gr, grctx->gpc, 0x41a000, 0x000, 0x418000); 1616 gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800); 1617 gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00); 1618 1619 /* start HUB ucode running, it'll init the GPCs */ 1620 nvkm_wr32(device, 0x40910c, 0x00000000); 1621 nvkm_wr32(device, 0x409100, 0x00000002); 1622 if (nvkm_msec(device, 2000, 1623 if (nvkm_rd32(device, 0x409800) & 0x80000000) 1624 break; 1625 ) < 0) { 1626 gf100_gr_ctxctl_debug(gr); 1627 return -EBUSY; 1628 } 1629 1630 gr->size = nvkm_rd32(device, 0x409804); 1631 if (gr->data == NULL) { 1632 int ret = gf100_grctx_generate(gr); 1633 if (ret) { 1634 nvkm_error(subdev, "failed to construct context\n"); 1635 return ret; 1636 } 1637 } 1638 1639 return 0; 1640 } 1641 1642 int 1643 gf100_gr_init_ctxctl(struct gf100_gr *gr) 1644 { 1645 int ret; 1646 1647 if (gr->firmware) 1648 ret = gf100_gr_init_ctxctl_ext(gr); 1649 else 1650 ret = gf100_gr_init_ctxctl_int(gr); 1651 1652 return ret; 1653 } 1654 1655 static int 1656 gf100_gr_oneinit(struct nvkm_gr *base) 1657 { 1658 struct gf100_gr *gr = gf100_gr(base); 1659 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1660 struct nvkm_device *device = subdev->device; 1661 int i, j; 1662 int ret; 1663 1664 ret = nvkm_falcon_v1_new(subdev, "FECS", 0x409000, &gr->fecs); 1665 if (ret) 1666 return ret; 1667 1668 ret = nvkm_falcon_v1_new(subdev, "GPCCS", 0x41a000, &gr->gpccs); 1669 if (ret) 1670 return ret; 1671 1672 nvkm_pmu_pgob(device->pmu, false); 1673 1674 gr->rop_nr = gr->func->rops(gr); 1675 gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; 1676 for (i = 0; i < gr->gpc_nr; i++) { 1677 gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); 1678 gr->tpc_total += gr->tpc_nr[i]; 1679 gr->ppc_nr[i] = gr->func->ppc_nr; 1680 for (j = 0; j < gr->ppc_nr[i]; j++) { 1681 u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); 1682 if (mask) 1683 gr->ppc_mask[i] |= (1 << j); 1684 gr->ppc_tpc_nr[i][j] = hweight8(mask); 1685 } 1686 } 1687 1688 /*XXX: these need figuring out... though it might not even matter */ 1689 switch (device->chipset) { 1690 case 0xc0: 1691 if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ 1692 gr->screen_tile_row_offset = 0x07; 1693 } else 1694 if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ 1695 gr->screen_tile_row_offset = 0x05; 1696 } else 1697 if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ 1698 gr->screen_tile_row_offset = 0x06; 1699 } 1700 break; 1701 case 0xc3: /* 450, 4/0/0/0, 2 */ 1702 gr->screen_tile_row_offset = 0x03; 1703 break; 1704 case 0xc4: /* 460, 3/4/0/0, 4 */ 1705 gr->screen_tile_row_offset = 0x01; 1706 break; 1707 case 0xc1: /* 2/0/0/0, 1 */ 1708 gr->screen_tile_row_offset = 0x01; 1709 break; 1710 case 0xc8: /* 4/4/3/4, 5 */ 1711 gr->screen_tile_row_offset = 0x06; 1712 break; 1713 case 0xce: /* 4/4/0/0, 4 */ 1714 gr->screen_tile_row_offset = 0x03; 1715 break; 1716 case 0xcf: /* 4/0/0/0, 3 */ 1717 gr->screen_tile_row_offset = 0x03; 1718 break; 1719 case 0xd7: 1720 case 0xd9: /* 1/0/0/0, 1 */ 1721 case 0xea: /* gk20a */ 1722 case 0x12b: /* gm20b */ 1723 gr->screen_tile_row_offset = 0x01; 1724 break; 1725 } 1726 1727 return 0; 1728 } 1729 1730 static int 1731 gf100_gr_init_(struct nvkm_gr *base) 1732 { 1733 struct gf100_gr *gr = gf100_gr(base); 1734 struct nvkm_subdev *subdev = &base->engine.subdev; 1735 u32 ret; 1736 1737 nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); 1738 1739 ret = nvkm_falcon_get(gr->fecs, subdev); 1740 if (ret) 1741 return ret; 1742 1743 ret = nvkm_falcon_get(gr->gpccs, subdev); 1744 if (ret) 1745 return ret; 1746 1747 return gr->func->init(gr); 1748 } 1749 1750 static int 1751 gf100_gr_fini_(struct nvkm_gr *base, bool suspend) 1752 { 1753 struct gf100_gr *gr = gf100_gr(base); 1754 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1755 nvkm_falcon_put(gr->gpccs, subdev); 1756 nvkm_falcon_put(gr->fecs, subdev); 1757 return 0; 1758 } 1759 1760 void 1761 gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) 1762 { 1763 kfree(fuc->data); 1764 fuc->data = NULL; 1765 } 1766 1767 static void 1768 gf100_gr_dtor_init(struct gf100_gr_pack *pack) 1769 { 1770 vfree(pack); 1771 } 1772 1773 void * 1774 gf100_gr_dtor(struct nvkm_gr *base) 1775 { 1776 struct gf100_gr *gr = gf100_gr(base); 1777 1778 if (gr->func->dtor) 1779 gr->func->dtor(gr); 1780 kfree(gr->data); 1781 1782 nvkm_falcon_del(&gr->gpccs); 1783 nvkm_falcon_del(&gr->fecs); 1784 1785 gf100_gr_dtor_fw(&gr->fuc409c); 1786 gf100_gr_dtor_fw(&gr->fuc409d); 1787 gf100_gr_dtor_fw(&gr->fuc41ac); 1788 gf100_gr_dtor_fw(&gr->fuc41ad); 1789 1790 gf100_gr_dtor_init(gr->fuc_bundle); 1791 gf100_gr_dtor_init(gr->fuc_method); 1792 gf100_gr_dtor_init(gr->fuc_sw_ctx); 1793 gf100_gr_dtor_init(gr->fuc_sw_nonctx); 1794 1795 return gr; 1796 } 1797 1798 static const struct nvkm_gr_func 1799 gf100_gr_ = { 1800 .dtor = gf100_gr_dtor, 1801 .oneinit = gf100_gr_oneinit, 1802 .init = gf100_gr_init_, 1803 .fini = gf100_gr_fini_, 1804 .intr = gf100_gr_intr, 1805 .units = gf100_gr_units, 1806 .chan_new = gf100_gr_chan_new, 1807 .object_get = gf100_gr_object_get, 1808 .chsw_load = gf100_gr_chsw_load, 1809 }; 1810 1811 int 1812 gf100_gr_ctor_fw_legacy(struct gf100_gr *gr, const char *fwname, 1813 struct gf100_gr_fuc *fuc, int ret) 1814 { 1815 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1816 struct nvkm_device *device = subdev->device; 1817 const struct firmware *fw; 1818 char f[32]; 1819 1820 /* see if this firmware has a legacy path */ 1821 if (!strcmp(fwname, "fecs_inst")) 1822 fwname = "fuc409c"; 1823 else if (!strcmp(fwname, "fecs_data")) 1824 fwname = "fuc409d"; 1825 else if (!strcmp(fwname, "gpccs_inst")) 1826 fwname = "fuc41ac"; 1827 else if (!strcmp(fwname, "gpccs_data")) 1828 fwname = "fuc41ad"; 1829 else { 1830 /* nope, let's just return the error we got */ 1831 nvkm_error(subdev, "failed to load %s\n", fwname); 1832 return ret; 1833 } 1834 1835 /* yes, try to load from the legacy path */ 1836 nvkm_debug(subdev, "%s: falling back to legacy path\n", fwname); 1837 1838 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname); 1839 ret = request_firmware(&fw, f, device->dev); 1840 if (ret) { 1841 snprintf(f, sizeof(f), "nouveau/%s", fwname); 1842 ret = request_firmware(&fw, f, device->dev); 1843 if (ret) { 1844 nvkm_error(subdev, "failed to load %s\n", fwname); 1845 return ret; 1846 } 1847 } 1848 1849 fuc->size = fw->size; 1850 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); 1851 release_firmware(fw); 1852 return (fuc->data != NULL) ? 0 : -ENOMEM; 1853 } 1854 1855 int 1856 gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, 1857 struct gf100_gr_fuc *fuc) 1858 { 1859 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1860 struct nvkm_device *device = subdev->device; 1861 const struct firmware *fw; 1862 int ret; 1863 1864 ret = nvkm_firmware_get(device, fwname, &fw); 1865 if (ret) { 1866 ret = gf100_gr_ctor_fw_legacy(gr, fwname, fuc, ret); 1867 if (ret) 1868 return -ENODEV; 1869 return 0; 1870 } 1871 1872 fuc->size = fw->size; 1873 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); 1874 nvkm_firmware_put(fw); 1875 return (fuc->data != NULL) ? 0 : -ENOMEM; 1876 } 1877 1878 int 1879 gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device, 1880 int index, struct gf100_gr *gr) 1881 { 1882 gr->func = func; 1883 gr->firmware = nvkm_boolopt(device->cfgopt, "NvGrUseFW", 1884 func->fecs.ucode == NULL); 1885 1886 return nvkm_gr_ctor(&gf100_gr_, device, index, 1887 gr->firmware || func->fecs.ucode != NULL, 1888 &gr->base); 1889 } 1890 1891 int 1892 gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device, 1893 int index, struct nvkm_gr **pgr) 1894 { 1895 struct gf100_gr *gr; 1896 int ret; 1897 1898 if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) 1899 return -ENOMEM; 1900 *pgr = &gr->base; 1901 1902 ret = gf100_gr_ctor(func, device, index, gr); 1903 if (ret) 1904 return ret; 1905 1906 if (gr->firmware) { 1907 if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || 1908 gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || 1909 gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || 1910 gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) 1911 return -ENODEV; 1912 } 1913 1914 return 0; 1915 } 1916 1917 void 1918 gf100_gr_init_tex_hww_esr(struct gf100_gr *gr, int tpc, int gpc) 1919 { 1920 struct nvkm_device *device = gr->base.engine.subdev.device; 1921 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); 1922 } 1923 1924 void 1925 gf100_gr_init_419eb4(struct gf100_gr *gr) 1926 { 1927 struct nvkm_device *device = gr->base.engine.subdev.device; 1928 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); 1929 } 1930 1931 void 1932 gf100_gr_init_419cc0(struct gf100_gr *gr) 1933 { 1934 struct nvkm_device *device = gr->base.engine.subdev.device; 1935 int gpc, tpc; 1936 1937 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); 1938 1939 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 1940 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) 1941 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); 1942 } 1943 } 1944 1945 void 1946 gf100_gr_init_40601c(struct gf100_gr *gr) 1947 { 1948 nvkm_wr32(gr->base.engine.subdev.device, 0x40601c, 0xc0000000); 1949 } 1950 1951 void 1952 gf100_gr_init_fecs_exceptions(struct gf100_gr *gr) 1953 { 1954 const u32 data = gr->firmware ? 0x000e0000 : 0x000e0001; 1955 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, data); 1956 } 1957 1958 void 1959 gf100_gr_init_gpc_mmu(struct gf100_gr *gr) 1960 { 1961 struct nvkm_device *device = gr->base.engine.subdev.device; 1962 struct nvkm_fb *fb = device->fb; 1963 1964 nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0x00000001); 1965 nvkm_wr32(device, 0x4188a4, 0x03000000); 1966 nvkm_wr32(device, 0x418888, 0x00000000); 1967 nvkm_wr32(device, 0x41888c, 0x00000000); 1968 nvkm_wr32(device, 0x418890, 0x00000000); 1969 nvkm_wr32(device, 0x418894, 0x00000000); 1970 nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(fb->mmu_wr) >> 8); 1971 nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(fb->mmu_rd) >> 8); 1972 } 1973 1974 void 1975 gf100_gr_init_num_active_ltcs(struct gf100_gr *gr) 1976 { 1977 struct nvkm_device *device = gr->base.engine.subdev.device; 1978 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); 1979 } 1980 1981 void 1982 gf100_gr_init_zcull(struct gf100_gr *gr) 1983 { 1984 struct nvkm_device *device = gr->base.engine.subdev.device; 1985 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); 1986 u32 data[TPC_MAX / 8] = {}; 1987 u8 tpcnr[GPC_MAX]; 1988 int gpc, tpc; 1989 int i; 1990 1991 memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); 1992 for (i = 0, gpc = -1; i < gr->tpc_total; i++) { 1993 do { 1994 gpc = (gpc + 1) % gr->gpc_nr; 1995 } while (!tpcnr[gpc]); 1996 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; 1997 1998 data[i / 8] |= tpc << ((i % 8) * 4); 1999 } 2000 2001 nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); 2002 nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); 2003 nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); 2004 nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); 2005 2006 nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); 2007 } 2008 2009 void 2010 gf100_gr_init_vsc_stream_master(struct gf100_gr *gr) 2011 { 2012 struct nvkm_device *device = gr->base.engine.subdev.device; 2013 nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001); 2014 } 2015 2016 int 2017 gf100_gr_init(struct gf100_gr *gr) 2018 { 2019 struct nvkm_device *device = gr->base.engine.subdev.device; 2020 int gpc, tpc, rop; 2021 2022 gr->func->init_gpc_mmu(gr); 2023 2024 if (gr->fuc_sw_nonctx) 2025 gf100_gr_mmio(gr, gr->fuc_sw_nonctx); 2026 else 2027 gf100_gr_mmio(gr, gr->func->mmio); 2028 2029 if (gr->func->init_r405a14) 2030 gr->func->init_r405a14(gr); 2031 2032 if (gr->func->clkgate_pack) 2033 nvkm_therm_clkgate_init(device->therm, gr->func->clkgate_pack); 2034 2035 if (gr->func->init_bios) 2036 gr->func->init_bios(gr); 2037 2038 gr->func->init_vsc_stream_master(gr); 2039 gr->func->init_zcull(gr); 2040 gr->func->init_num_active_ltcs(gr); 2041 if (gr->func->init_rop_active_fbps) 2042 gr->func->init_rop_active_fbps(gr); 2043 if (gr->func->init_bios_2) 2044 gr->func->init_bios_2(gr); 2045 if (gr->func->init_swdx_pes_mask) 2046 gr->func->init_swdx_pes_mask(gr); 2047 2048 nvkm_wr32(device, 0x400500, 0x00010001); 2049 2050 nvkm_wr32(device, 0x400100, 0xffffffff); 2051 nvkm_wr32(device, 0x40013c, 0xffffffff); 2052 nvkm_wr32(device, 0x400124, 0x00000002); 2053 2054 gr->func->init_fecs_exceptions(gr); 2055 if (gr->func->init_ds_hww_esr_2) 2056 gr->func->init_ds_hww_esr_2(gr); 2057 2058 nvkm_wr32(device, 0x404000, 0xc0000000); 2059 nvkm_wr32(device, 0x404600, 0xc0000000); 2060 nvkm_wr32(device, 0x408030, 0xc0000000); 2061 2062 if (gr->func->init_40601c) 2063 gr->func->init_40601c(gr); 2064 2065 nvkm_wr32(device, 0x404490, 0xc0000000); 2066 nvkm_wr32(device, 0x406018, 0xc0000000); 2067 2068 if (gr->func->init_sked_hww_esr) 2069 gr->func->init_sked_hww_esr(gr); 2070 2071 nvkm_wr32(device, 0x405840, 0xc0000000); 2072 nvkm_wr32(device, 0x405844, 0x00ffffff); 2073 2074 if (gr->func->init_419cc0) 2075 gr->func->init_419cc0(gr); 2076 if (gr->func->init_419eb4) 2077 gr->func->init_419eb4(gr); 2078 if (gr->func->init_419c9c) 2079 gr->func->init_419c9c(gr); 2080 2081 if (gr->func->init_ppc_exceptions) 2082 gr->func->init_ppc_exceptions(gr); 2083 2084 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 2085 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); 2086 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); 2087 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); 2088 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); 2089 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { 2090 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); 2091 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); 2092 if (gr->func->init_tex_hww_esr) 2093 gr->func->init_tex_hww_esr(gr, gpc, tpc); 2094 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); 2095 if (gr->func->init_504430) 2096 gr->func->init_504430(gr, gpc, tpc); 2097 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); 2098 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); 2099 } 2100 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); 2101 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); 2102 } 2103 2104 for (rop = 0; rop < gr->rop_nr; rop++) { 2105 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); 2106 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); 2107 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); 2108 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); 2109 } 2110 2111 nvkm_wr32(device, 0x400108, 0xffffffff); 2112 nvkm_wr32(device, 0x400138, 0xffffffff); 2113 nvkm_wr32(device, 0x400118, 0xffffffff); 2114 nvkm_wr32(device, 0x400130, 0xffffffff); 2115 nvkm_wr32(device, 0x40011c, 0xffffffff); 2116 nvkm_wr32(device, 0x400134, 0xffffffff); 2117 2118 nvkm_wr32(device, 0x400054, 0x34ce3464); 2119 2120 gf100_gr_zbc_init(gr); 2121 2122 return gf100_gr_init_ctxctl(gr); 2123 } 2124 2125 #include "fuc/hubgf100.fuc3.h" 2126 2127 struct gf100_gr_ucode 2128 gf100_gr_fecs_ucode = { 2129 .code.data = gf100_grhub_code, 2130 .code.size = sizeof(gf100_grhub_code), 2131 .data.data = gf100_grhub_data, 2132 .data.size = sizeof(gf100_grhub_data), 2133 }; 2134 2135 #include "fuc/gpcgf100.fuc3.h" 2136 2137 struct gf100_gr_ucode 2138 gf100_gr_gpccs_ucode = { 2139 .code.data = gf100_grgpc_code, 2140 .code.size = sizeof(gf100_grgpc_code), 2141 .data.data = gf100_grgpc_data, 2142 .data.size = sizeof(gf100_grgpc_data), 2143 }; 2144 2145 static const struct gf100_gr_func 2146 gf100_gr = { 2147 .init = gf100_gr_init, 2148 .init_gpc_mmu = gf100_gr_init_gpc_mmu, 2149 .init_vsc_stream_master = gf100_gr_init_vsc_stream_master, 2150 .init_zcull = gf100_gr_init_zcull, 2151 .init_num_active_ltcs = gf100_gr_init_num_active_ltcs, 2152 .init_fecs_exceptions = gf100_gr_init_fecs_exceptions, 2153 .init_40601c = gf100_gr_init_40601c, 2154 .init_419cc0 = gf100_gr_init_419cc0, 2155 .init_419eb4 = gf100_gr_init_419eb4, 2156 .init_tex_hww_esr = gf100_gr_init_tex_hww_esr, 2157 .mmio = gf100_gr_pack_mmio, 2158 .fecs.ucode = &gf100_gr_fecs_ucode, 2159 .gpccs.ucode = &gf100_gr_gpccs_ucode, 2160 .rops = gf100_gr_rops, 2161 .grctx = &gf100_grctx, 2162 .sclass = { 2163 { -1, -1, FERMI_TWOD_A }, 2164 { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A }, 2165 { -1, -1, FERMI_A, &gf100_fermi }, 2166 { -1, -1, FERMI_COMPUTE_A }, 2167 {} 2168 } 2169 }; 2170 2171 int 2172 gf100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) 2173 { 2174 return gf100_gr_new_(&gf100_gr, device, index, pgr); 2175 } 2176