1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "gf100.h" 25 #include "ctxgf100.h" 26 #include "fuc/os.h" 27 28 #include <core/client.h> 29 #include <core/option.h> 30 #include <subdev/fb.h> 31 #include <subdev/mc.h> 32 #include <subdev/timer.h> 33 #include <engine/fifo.h> 34 35 #include <nvif/class.h> 36 #include <nvif/unpack.h> 37 38 /******************************************************************************* 39 * Zero Bandwidth Clear 40 ******************************************************************************/ 41 42 static void 43 gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) 44 { 45 struct nvkm_device *device = gr->base.engine.subdev.device; 46 if (gr->zbc_color[zbc].format) { 47 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); 48 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); 49 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); 50 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); 51 } 52 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); 53 nvkm_wr32(device, 0x405820, zbc); 54 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ 55 } 56 57 static int 58 gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, 59 const u32 ds[4], const u32 l2[4]) 60 { 61 struct nvkm_ltc *ltc = nvkm_ltc(gr); 62 int zbc = -ENOSPC, i; 63 64 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { 65 if (gr->zbc_color[i].format) { 66 if (gr->zbc_color[i].format != format) 67 continue; 68 if (memcmp(gr->zbc_color[i].ds, ds, sizeof( 69 gr->zbc_color[i].ds))) 70 continue; 71 if (memcmp(gr->zbc_color[i].l2, l2, sizeof( 72 gr->zbc_color[i].l2))) { 73 WARN_ON(1); 74 return -EINVAL; 75 } 76 return i; 77 } else { 78 zbc = (zbc < 0) ? i : zbc; 79 } 80 } 81 82 if (zbc < 0) 83 return zbc; 84 85 memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); 86 memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); 87 gr->zbc_color[zbc].format = format; 88 ltc->zbc_color_get(ltc, zbc, l2); 89 gf100_gr_zbc_clear_color(gr, zbc); 90 return zbc; 91 } 92 93 static void 94 gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) 95 { 96 struct nvkm_device *device = gr->base.engine.subdev.device; 97 if (gr->zbc_depth[zbc].format) 98 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); 99 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); 100 nvkm_wr32(device, 0x405820, zbc); 101 nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ 102 } 103 104 static int 105 gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, 106 const u32 ds, const u32 l2) 107 { 108 struct nvkm_ltc *ltc = nvkm_ltc(gr); 109 int zbc = -ENOSPC, i; 110 111 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { 112 if (gr->zbc_depth[i].format) { 113 if (gr->zbc_depth[i].format != format) 114 continue; 115 if (gr->zbc_depth[i].ds != ds) 116 continue; 117 if (gr->zbc_depth[i].l2 != l2) { 118 WARN_ON(1); 119 return -EINVAL; 120 } 121 return i; 122 } else { 123 zbc = (zbc < 0) ? i : zbc; 124 } 125 } 126 127 if (zbc < 0) 128 return zbc; 129 130 gr->zbc_depth[zbc].format = format; 131 gr->zbc_depth[zbc].ds = ds; 132 gr->zbc_depth[zbc].l2 = l2; 133 ltc->zbc_depth_get(ltc, zbc, l2); 134 gf100_gr_zbc_clear_depth(gr, zbc); 135 return zbc; 136 } 137 138 /******************************************************************************* 139 * Graphics object classes 140 ******************************************************************************/ 141 142 static int 143 gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) 144 { 145 struct gf100_gr *gr = (void *)object->engine; 146 union { 147 struct fermi_a_zbc_color_v0 v0; 148 } *args = data; 149 int ret; 150 151 if (nvif_unpack(args->v0, 0, 0, false)) { 152 switch (args->v0.format) { 153 case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: 154 case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: 155 case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32: 156 case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16: 157 case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16: 158 case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16: 159 case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16: 160 case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16: 161 case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8: 162 case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8: 163 case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10: 164 case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10: 165 case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8: 166 case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8: 167 case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8: 168 case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8: 169 case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: 170 case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: 171 case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: 172 ret = gf100_gr_zbc_color_get(gr, args->v0.format, 173 args->v0.ds, 174 args->v0.l2); 175 if (ret >= 0) { 176 args->v0.index = ret; 177 return 0; 178 } 179 break; 180 default: 181 return -EINVAL; 182 } 183 } 184 185 return ret; 186 } 187 188 static int 189 gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) 190 { 191 struct gf100_gr *gr = (void *)object->engine; 192 union { 193 struct fermi_a_zbc_depth_v0 v0; 194 } *args = data; 195 int ret; 196 197 if (nvif_unpack(args->v0, 0, 0, false)) { 198 switch (args->v0.format) { 199 case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: 200 ret = gf100_gr_zbc_depth_get(gr, args->v0.format, 201 args->v0.ds, 202 args->v0.l2); 203 return (ret >= 0) ? 0 : -ENOSPC; 204 default: 205 return -EINVAL; 206 } 207 } 208 209 return ret; 210 } 211 212 static int 213 gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) 214 { 215 switch (mthd) { 216 case FERMI_A_ZBC_COLOR: 217 return gf100_fermi_mthd_zbc_color(object, data, size); 218 case FERMI_A_ZBC_DEPTH: 219 return gf100_fermi_mthd_zbc_depth(object, data, size); 220 default: 221 break; 222 } 223 return -EINVAL; 224 } 225 226 struct nvkm_ofuncs 227 gf100_fermi_ofuncs = { 228 .ctor = _nvkm_object_ctor, 229 .dtor = nvkm_object_destroy, 230 .init = _nvkm_object_init, 231 .fini = _nvkm_object_fini, 232 .mthd = gf100_fermi_mthd, 233 }; 234 235 static void 236 gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data) 237 { 238 nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000); 239 nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000); 240 } 241 242 static bool 243 gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data) 244 { 245 switch (class & 0x00ff) { 246 case 0x97: 247 case 0xc0: 248 switch (mthd) { 249 case 0x1528: 250 gf100_gr_mthd_set_shader_exceptions(device, data); 251 return true; 252 default: 253 break; 254 } 255 break; 256 default: 257 break; 258 } 259 return false; 260 } 261 262 struct nvkm_oclass 263 gf100_gr_sclass[] = { 264 { FERMI_TWOD_A, &nvkm_object_ofuncs }, 265 { FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs }, 266 { FERMI_A, &gf100_fermi_ofuncs }, 267 { FERMI_COMPUTE_A, &nvkm_object_ofuncs }, 268 {} 269 }; 270 271 /******************************************************************************* 272 * PGRAPH context 273 ******************************************************************************/ 274 275 int 276 gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 277 struct nvkm_oclass *oclass, void *args, u32 size, 278 struct nvkm_object **pobject) 279 { 280 struct nvkm_vm *vm = nvkm_client(parent)->vm; 281 struct gf100_gr *gr = (void *)engine; 282 struct gf100_gr_data *data = gr->mmio_data; 283 struct gf100_gr_mmio *mmio = gr->mmio_list; 284 struct gf100_gr_chan *chan; 285 struct nvkm_device *device = gr->base.engine.subdev.device; 286 struct nvkm_gpuobj *image; 287 int ret, i; 288 289 /* allocate memory for context, and fill with default values */ 290 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 291 gr->size, 0x100, 292 NVOBJ_FLAG_ZERO_ALLOC, &chan); 293 *pobject = nv_object(chan); 294 if (ret) 295 return ret; 296 297 /* allocate memory for a "mmio list" buffer that's used by the HUB 298 * fuc to modify some per-context register settings on first load 299 * of the context. 300 */ 301 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100, 302 false, &chan->mmio); 303 if (ret) 304 return ret; 305 306 ret = nvkm_vm_get(vm, 0x1000, 12, NV_MEM_ACCESS_RW | 307 NV_MEM_ACCESS_SYS, &chan->mmio_vma); 308 if (ret) 309 return ret; 310 311 nvkm_memory_map(chan->mmio, &chan->mmio_vma, 0); 312 313 /* allocate buffers referenced by mmio list */ 314 for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) { 315 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 316 data->size, data->align, false, 317 &chan->data[i].mem); 318 if (ret) 319 return ret; 320 321 ret = nvkm_vm_get(vm, nvkm_memory_size(chan->data[i].mem), 322 12, data->access, &chan->data[i].vma); 323 if (ret) 324 return ret; 325 326 nvkm_memory_map(chan->data[i].mem, &chan->data[i].vma, 0); 327 data++; 328 } 329 330 /* finally, fill in the mmio list and point the context at it */ 331 nvkm_kmap(chan->mmio); 332 for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) { 333 u32 addr = mmio->addr; 334 u32 data = mmio->data; 335 336 if (mmio->buffer >= 0) { 337 u64 info = chan->data[mmio->buffer].vma.offset; 338 data |= info >> mmio->shift; 339 } 340 341 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); 342 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data); 343 mmio++; 344 } 345 nvkm_done(chan->mmio); 346 347 image = &chan->base.base.gpuobj; 348 nvkm_kmap(image); 349 for (i = 0; i < gr->size; i += 4) 350 nvkm_wo32(image, i, gr->data[i / 4]); 351 352 if (!gr->firmware) { 353 nvkm_wo32(image, 0x00, chan->mmio_nr / 2); 354 nvkm_wo32(image, 0x04, chan->mmio_vma.offset >> 8); 355 } else { 356 nvkm_wo32(image, 0xf4, 0); 357 nvkm_wo32(image, 0xf8, 0); 358 nvkm_wo32(image, 0x10, chan->mmio_nr / 2); 359 nvkm_wo32(image, 0x14, lower_32_bits(chan->mmio_vma.offset)); 360 nvkm_wo32(image, 0x18, upper_32_bits(chan->mmio_vma.offset)); 361 nvkm_wo32(image, 0x1c, 1); 362 nvkm_wo32(image, 0x20, 0); 363 nvkm_wo32(image, 0x28, 0); 364 nvkm_wo32(image, 0x2c, 0); 365 } 366 nvkm_done(image); 367 return 0; 368 } 369 370 void 371 gf100_gr_context_dtor(struct nvkm_object *object) 372 { 373 struct gf100_gr_chan *chan = (void *)object; 374 int i; 375 376 for (i = 0; i < ARRAY_SIZE(chan->data); i++) { 377 if (chan->data[i].vma.node) { 378 nvkm_vm_unmap(&chan->data[i].vma); 379 nvkm_vm_put(&chan->data[i].vma); 380 } 381 nvkm_memory_del(&chan->data[i].mem); 382 } 383 384 if (chan->mmio_vma.node) { 385 nvkm_vm_unmap(&chan->mmio_vma); 386 nvkm_vm_put(&chan->mmio_vma); 387 } 388 nvkm_memory_del(&chan->mmio); 389 390 nvkm_gr_context_destroy(&chan->base); 391 } 392 393 /******************************************************************************* 394 * PGRAPH register lists 395 ******************************************************************************/ 396 397 const struct gf100_gr_init 398 gf100_gr_init_main_0[] = { 399 { 0x400080, 1, 0x04, 0x003083c2 }, 400 { 0x400088, 1, 0x04, 0x00006fe7 }, 401 { 0x40008c, 1, 0x04, 0x00000000 }, 402 { 0x400090, 1, 0x04, 0x00000030 }, 403 { 0x40013c, 1, 0x04, 0x013901f7 }, 404 { 0x400140, 1, 0x04, 0x00000100 }, 405 { 0x400144, 1, 0x04, 0x00000000 }, 406 { 0x400148, 1, 0x04, 0x00000110 }, 407 { 0x400138, 1, 0x04, 0x00000000 }, 408 { 0x400130, 2, 0x04, 0x00000000 }, 409 { 0x400124, 1, 0x04, 0x00000002 }, 410 {} 411 }; 412 413 const struct gf100_gr_init 414 gf100_gr_init_fe_0[] = { 415 { 0x40415c, 1, 0x04, 0x00000000 }, 416 { 0x404170, 1, 0x04, 0x00000000 }, 417 {} 418 }; 419 420 const struct gf100_gr_init 421 gf100_gr_init_pri_0[] = { 422 { 0x404488, 2, 0x04, 0x00000000 }, 423 {} 424 }; 425 426 const struct gf100_gr_init 427 gf100_gr_init_rstr2d_0[] = { 428 { 0x407808, 1, 0x04, 0x00000000 }, 429 {} 430 }; 431 432 const struct gf100_gr_init 433 gf100_gr_init_pd_0[] = { 434 { 0x406024, 1, 0x04, 0x00000000 }, 435 {} 436 }; 437 438 const struct gf100_gr_init 439 gf100_gr_init_ds_0[] = { 440 { 0x405844, 1, 0x04, 0x00ffffff }, 441 { 0x405850, 1, 0x04, 0x00000000 }, 442 { 0x405908, 1, 0x04, 0x00000000 }, 443 {} 444 }; 445 446 const struct gf100_gr_init 447 gf100_gr_init_scc_0[] = { 448 { 0x40803c, 1, 0x04, 0x00000000 }, 449 {} 450 }; 451 452 const struct gf100_gr_init 453 gf100_gr_init_prop_0[] = { 454 { 0x4184a0, 1, 0x04, 0x00000000 }, 455 {} 456 }; 457 458 const struct gf100_gr_init 459 gf100_gr_init_gpc_unk_0[] = { 460 { 0x418604, 1, 0x04, 0x00000000 }, 461 { 0x418680, 1, 0x04, 0x00000000 }, 462 { 0x418714, 1, 0x04, 0x80000000 }, 463 { 0x418384, 1, 0x04, 0x00000000 }, 464 {} 465 }; 466 467 const struct gf100_gr_init 468 gf100_gr_init_setup_0[] = { 469 { 0x418814, 3, 0x04, 0x00000000 }, 470 {} 471 }; 472 473 const struct gf100_gr_init 474 gf100_gr_init_crstr_0[] = { 475 { 0x418b04, 1, 0x04, 0x00000000 }, 476 {} 477 }; 478 479 const struct gf100_gr_init 480 gf100_gr_init_setup_1[] = { 481 { 0x4188c8, 1, 0x04, 0x80000000 }, 482 { 0x4188cc, 1, 0x04, 0x00000000 }, 483 { 0x4188d0, 1, 0x04, 0x00010000 }, 484 { 0x4188d4, 1, 0x04, 0x00000001 }, 485 {} 486 }; 487 488 const struct gf100_gr_init 489 gf100_gr_init_zcull_0[] = { 490 { 0x418910, 1, 0x04, 0x00010001 }, 491 { 0x418914, 1, 0x04, 0x00000301 }, 492 { 0x418918, 1, 0x04, 0x00800000 }, 493 { 0x418980, 1, 0x04, 0x77777770 }, 494 { 0x418984, 3, 0x04, 0x77777777 }, 495 {} 496 }; 497 498 const struct gf100_gr_init 499 gf100_gr_init_gpm_0[] = { 500 { 0x418c04, 1, 0x04, 0x00000000 }, 501 { 0x418c88, 1, 0x04, 0x00000000 }, 502 {} 503 }; 504 505 const struct gf100_gr_init 506 gf100_gr_init_gpc_unk_1[] = { 507 { 0x418d00, 1, 0x04, 0x00000000 }, 508 { 0x418f08, 1, 0x04, 0x00000000 }, 509 { 0x418e00, 1, 0x04, 0x00000050 }, 510 { 0x418e08, 1, 0x04, 0x00000000 }, 511 {} 512 }; 513 514 const struct gf100_gr_init 515 gf100_gr_init_gcc_0[] = { 516 { 0x41900c, 1, 0x04, 0x00000000 }, 517 { 0x419018, 1, 0x04, 0x00000000 }, 518 {} 519 }; 520 521 const struct gf100_gr_init 522 gf100_gr_init_tpccs_0[] = { 523 { 0x419d08, 2, 0x04, 0x00000000 }, 524 { 0x419d10, 1, 0x04, 0x00000014 }, 525 {} 526 }; 527 528 const struct gf100_gr_init 529 gf100_gr_init_tex_0[] = { 530 { 0x419ab0, 1, 0x04, 0x00000000 }, 531 { 0x419ab8, 1, 0x04, 0x000000e7 }, 532 { 0x419abc, 2, 0x04, 0x00000000 }, 533 {} 534 }; 535 536 const struct gf100_gr_init 537 gf100_gr_init_pe_0[] = { 538 { 0x41980c, 3, 0x04, 0x00000000 }, 539 { 0x419844, 1, 0x04, 0x00000000 }, 540 { 0x41984c, 1, 0x04, 0x00005bc5 }, 541 { 0x419850, 4, 0x04, 0x00000000 }, 542 {} 543 }; 544 545 const struct gf100_gr_init 546 gf100_gr_init_l1c_0[] = { 547 { 0x419c98, 1, 0x04, 0x00000000 }, 548 { 0x419ca8, 1, 0x04, 0x80000000 }, 549 { 0x419cb4, 1, 0x04, 0x00000000 }, 550 { 0x419cb8, 1, 0x04, 0x00008bf4 }, 551 { 0x419cbc, 1, 0x04, 0x28137606 }, 552 { 0x419cc0, 2, 0x04, 0x00000000 }, 553 {} 554 }; 555 556 const struct gf100_gr_init 557 gf100_gr_init_wwdx_0[] = { 558 { 0x419bd4, 1, 0x04, 0x00800000 }, 559 { 0x419bdc, 1, 0x04, 0x00000000 }, 560 {} 561 }; 562 563 const struct gf100_gr_init 564 gf100_gr_init_tpccs_1[] = { 565 { 0x419d2c, 1, 0x04, 0x00000000 }, 566 {} 567 }; 568 569 const struct gf100_gr_init 570 gf100_gr_init_mpc_0[] = { 571 { 0x419c0c, 1, 0x04, 0x00000000 }, 572 {} 573 }; 574 575 static const struct gf100_gr_init 576 gf100_gr_init_sm_0[] = { 577 { 0x419e00, 1, 0x04, 0x00000000 }, 578 { 0x419ea0, 1, 0x04, 0x00000000 }, 579 { 0x419ea4, 1, 0x04, 0x00000100 }, 580 { 0x419ea8, 1, 0x04, 0x00001100 }, 581 { 0x419eac, 1, 0x04, 0x11100702 }, 582 { 0x419eb0, 1, 0x04, 0x00000003 }, 583 { 0x419eb4, 4, 0x04, 0x00000000 }, 584 { 0x419ec8, 1, 0x04, 0x06060618 }, 585 { 0x419ed0, 1, 0x04, 0x0eff0e38 }, 586 { 0x419ed4, 1, 0x04, 0x011104f1 }, 587 { 0x419edc, 1, 0x04, 0x00000000 }, 588 { 0x419f00, 1, 0x04, 0x00000000 }, 589 { 0x419f2c, 1, 0x04, 0x00000000 }, 590 {} 591 }; 592 593 const struct gf100_gr_init 594 gf100_gr_init_be_0[] = { 595 { 0x40880c, 1, 0x04, 0x00000000 }, 596 { 0x408910, 9, 0x04, 0x00000000 }, 597 { 0x408950, 1, 0x04, 0x00000000 }, 598 { 0x408954, 1, 0x04, 0x0000ffff }, 599 { 0x408984, 1, 0x04, 0x00000000 }, 600 { 0x408988, 1, 0x04, 0x08040201 }, 601 { 0x40898c, 1, 0x04, 0x80402010 }, 602 {} 603 }; 604 605 const struct gf100_gr_init 606 gf100_gr_init_fe_1[] = { 607 { 0x4040f0, 1, 0x04, 0x00000000 }, 608 {} 609 }; 610 611 const struct gf100_gr_init 612 gf100_gr_init_pe_1[] = { 613 { 0x419880, 1, 0x04, 0x00000002 }, 614 {} 615 }; 616 617 static const struct gf100_gr_pack 618 gf100_gr_pack_mmio[] = { 619 { gf100_gr_init_main_0 }, 620 { gf100_gr_init_fe_0 }, 621 { gf100_gr_init_pri_0 }, 622 { gf100_gr_init_rstr2d_0 }, 623 { gf100_gr_init_pd_0 }, 624 { gf100_gr_init_ds_0 }, 625 { gf100_gr_init_scc_0 }, 626 { gf100_gr_init_prop_0 }, 627 { gf100_gr_init_gpc_unk_0 }, 628 { gf100_gr_init_setup_0 }, 629 { gf100_gr_init_crstr_0 }, 630 { gf100_gr_init_setup_1 }, 631 { gf100_gr_init_zcull_0 }, 632 { gf100_gr_init_gpm_0 }, 633 { gf100_gr_init_gpc_unk_1 }, 634 { gf100_gr_init_gcc_0 }, 635 { gf100_gr_init_tpccs_0 }, 636 { gf100_gr_init_tex_0 }, 637 { gf100_gr_init_pe_0 }, 638 { gf100_gr_init_l1c_0 }, 639 { gf100_gr_init_wwdx_0 }, 640 { gf100_gr_init_tpccs_1 }, 641 { gf100_gr_init_mpc_0 }, 642 { gf100_gr_init_sm_0 }, 643 { gf100_gr_init_be_0 }, 644 { gf100_gr_init_fe_1 }, 645 { gf100_gr_init_pe_1 }, 646 {} 647 }; 648 649 /******************************************************************************* 650 * PGRAPH engine/subdev functions 651 ******************************************************************************/ 652 653 void 654 gf100_gr_zbc_init(struct gf100_gr *gr) 655 { 656 const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 657 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 658 const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 659 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; 660 const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 661 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 662 const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 663 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; 664 struct nvkm_ltc *ltc = nvkm_ltc(gr); 665 int index; 666 667 if (!gr->zbc_color[0].format) { 668 gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); 669 gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); 670 gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); 671 gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); 672 gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); 673 gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); 674 } 675 676 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) 677 gf100_gr_zbc_clear_color(gr, index); 678 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) 679 gf100_gr_zbc_clear_depth(gr, index); 680 } 681 682 /** 683 * Wait until GR goes idle. GR is considered idle if it is disabled by the 684 * MC (0x200) register, or GR is not busy and a context switch is not in 685 * progress. 686 */ 687 int 688 gf100_gr_wait_idle(struct gf100_gr *gr) 689 { 690 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 691 struct nvkm_device *device = subdev->device; 692 unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000); 693 bool gr_enabled, ctxsw_active, gr_busy; 694 695 do { 696 /* 697 * required to make sure FIFO_ENGINE_STATUS (0x2640) is 698 * up-to-date 699 */ 700 nvkm_rd32(device, 0x400700); 701 702 gr_enabled = nvkm_rd32(device, 0x200) & 0x1000; 703 ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000; 704 gr_busy = nvkm_rd32(device, 0x40060c) & 0x1; 705 706 if (!gr_enabled || (!gr_busy && !ctxsw_active)) 707 return 0; 708 } while (time_before(jiffies, end_jiffies)); 709 710 nvkm_error(subdev, 711 "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n", 712 gr_enabled, ctxsw_active, gr_busy); 713 return -EAGAIN; 714 } 715 716 void 717 gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) 718 { 719 struct nvkm_device *device = gr->base.engine.subdev.device; 720 const struct gf100_gr_pack *pack; 721 const struct gf100_gr_init *init; 722 723 pack_for_each_init(init, pack, p) { 724 u32 next = init->addr + init->count * init->pitch; 725 u32 addr = init->addr; 726 while (addr < next) { 727 nvkm_wr32(device, addr, init->data); 728 addr += init->pitch; 729 } 730 } 731 } 732 733 void 734 gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) 735 { 736 struct nvkm_device *device = gr->base.engine.subdev.device; 737 const struct gf100_gr_pack *pack; 738 const struct gf100_gr_init *init; 739 u32 data = 0; 740 741 nvkm_wr32(device, 0x400208, 0x80000000); 742 743 pack_for_each_init(init, pack, p) { 744 u32 next = init->addr + init->count * init->pitch; 745 u32 addr = init->addr; 746 747 if ((pack == p && init == p->init) || data != init->data) { 748 nvkm_wr32(device, 0x400204, init->data); 749 data = init->data; 750 } 751 752 while (addr < next) { 753 nvkm_wr32(device, 0x400200, addr); 754 /** 755 * Wait for GR to go idle after submitting a 756 * GO_IDLE bundle 757 */ 758 if ((addr & 0xffff) == 0xe100) 759 gf100_gr_wait_idle(gr); 760 nvkm_msec(device, 2000, 761 if (!(nvkm_rd32(device, 0x400700) & 0x00000004)) 762 break; 763 ); 764 addr += init->pitch; 765 } 766 } 767 768 nvkm_wr32(device, 0x400208, 0x00000000); 769 } 770 771 void 772 gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) 773 { 774 struct nvkm_device *device = gr->base.engine.subdev.device; 775 const struct gf100_gr_pack *pack; 776 const struct gf100_gr_init *init; 777 u32 data = 0; 778 779 pack_for_each_init(init, pack, p) { 780 u32 ctrl = 0x80000000 | pack->type; 781 u32 next = init->addr + init->count * init->pitch; 782 u32 addr = init->addr; 783 784 if ((pack == p && init == p->init) || data != init->data) { 785 nvkm_wr32(device, 0x40448c, init->data); 786 data = init->data; 787 } 788 789 while (addr < next) { 790 nvkm_wr32(device, 0x404488, ctrl | (addr << 14)); 791 addr += init->pitch; 792 } 793 } 794 } 795 796 u64 797 gf100_gr_units(struct nvkm_gr *obj) 798 { 799 struct gf100_gr *gr = container_of(obj, typeof(*gr), base); 800 u64 cfg; 801 802 cfg = (u32)gr->gpc_nr; 803 cfg |= (u32)gr->tpc_total << 8; 804 cfg |= (u64)gr->rop_nr << 32; 805 806 return cfg; 807 } 808 809 static const struct nvkm_bitfield gk104_sked_error[] = { 810 { 0x00000080, "CONSTANT_BUFFER_SIZE" }, 811 { 0x00000200, "LOCAL_MEMORY_SIZE_POS" }, 812 { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" }, 813 { 0x00000800, "WARP_CSTACK_SIZE" }, 814 { 0x00001000, "TOTAL_TEMP_SIZE" }, 815 { 0x00002000, "REGISTER_COUNT" }, 816 { 0x00040000, "TOTAL_THREADS" }, 817 { 0x00100000, "PROGRAM_OFFSET" }, 818 { 0x00200000, "SHARED_MEMORY_SIZE" }, 819 { 0x02000000, "SHARED_CONFIG_TOO_SMALL" }, 820 { 0x04000000, "TOTAL_REGISTER_COUNT" }, 821 {} 822 }; 823 824 static const struct nvkm_bitfield gf100_gpc_rop_error[] = { 825 { 0x00000002, "RT_PITCH_OVERRUN" }, 826 { 0x00000010, "RT_WIDTH_OVERRUN" }, 827 { 0x00000020, "RT_HEIGHT_OVERRUN" }, 828 { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" }, 829 { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" }, 830 { 0x00000400, "RT_LINEAR_MISMATCH" }, 831 {} 832 }; 833 834 static void 835 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) 836 { 837 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 838 struct nvkm_device *device = subdev->device; 839 char error[128]; 840 u32 trap[4]; 841 842 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; 843 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); 844 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); 845 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); 846 847 nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]); 848 849 nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, " 850 "format = %x, storage type = %x\n", 851 gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, 852 (trap[2] >> 8) & 0x3f, trap[3] & 0xff); 853 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); 854 } 855 856 static const struct nvkm_enum gf100_mp_warp_error[] = { 857 { 0x00, "NO_ERROR" }, 858 { 0x01, "STACK_MISMATCH" }, 859 { 0x05, "MISALIGNED_PC" }, 860 { 0x08, "MISALIGNED_GPR" }, 861 { 0x09, "INVALID_OPCODE" }, 862 { 0x0d, "GPR_OUT_OF_BOUNDS" }, 863 { 0x0e, "MEM_OUT_OF_BOUNDS" }, 864 { 0x0f, "UNALIGNED_MEM_ACCESS" }, 865 { 0x11, "INVALID_PARAM" }, 866 {} 867 }; 868 869 static const struct nvkm_bitfield gf100_mp_global_error[] = { 870 { 0x00000004, "MULTIPLE_WARP_ERRORS" }, 871 { 0x00000008, "OUT_OF_STACK_SPACE" }, 872 {} 873 }; 874 875 static void 876 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) 877 { 878 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 879 struct nvkm_device *device = subdev->device; 880 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); 881 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); 882 const struct nvkm_enum *warp; 883 char glob[128]; 884 885 nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr); 886 warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff); 887 888 nvkm_error(subdev, "GPC%i/TPC%i/MP trap: " 889 "global %08x [%s] warp %04x [%s]\n", 890 gpc, tpc, gerr, glob, werr, warp ? warp->name : ""); 891 892 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); 893 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); 894 } 895 896 static void 897 gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) 898 { 899 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 900 struct nvkm_device *device = subdev->device; 901 u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); 902 903 if (stat & 0x00000001) { 904 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); 905 nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap); 906 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); 907 stat &= ~0x00000001; 908 } 909 910 if (stat & 0x00000002) { 911 gf100_gr_trap_mp(gr, gpc, tpc); 912 stat &= ~0x00000002; 913 } 914 915 if (stat & 0x00000004) { 916 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); 917 nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap); 918 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); 919 stat &= ~0x00000004; 920 } 921 922 if (stat & 0x00000008) { 923 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); 924 nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap); 925 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); 926 stat &= ~0x00000008; 927 } 928 929 if (stat) { 930 nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat); 931 } 932 } 933 934 static void 935 gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) 936 { 937 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 938 struct nvkm_device *device = subdev->device; 939 u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); 940 int tpc; 941 942 if (stat & 0x00000001) { 943 gf100_gr_trap_gpc_rop(gr, gpc); 944 stat &= ~0x00000001; 945 } 946 947 if (stat & 0x00000002) { 948 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); 949 nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap); 950 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); 951 stat &= ~0x00000002; 952 } 953 954 if (stat & 0x00000004) { 955 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); 956 nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap); 957 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); 958 stat &= ~0x00000004; 959 } 960 961 if (stat & 0x00000008) { 962 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); 963 nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap); 964 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); 965 stat &= ~0x00000009; 966 } 967 968 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { 969 u32 mask = 0x00010000 << tpc; 970 if (stat & mask) { 971 gf100_gr_trap_tpc(gr, gpc, tpc); 972 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); 973 stat &= ~mask; 974 } 975 } 976 977 if (stat) { 978 nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat); 979 } 980 } 981 982 static void 983 gf100_gr_trap_intr(struct gf100_gr *gr) 984 { 985 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 986 struct nvkm_device *device = subdev->device; 987 u32 trap = nvkm_rd32(device, 0x400108); 988 int rop, gpc; 989 990 if (trap & 0x00000001) { 991 u32 stat = nvkm_rd32(device, 0x404000); 992 nvkm_error(subdev, "DISPATCH %08x\n", stat); 993 nvkm_wr32(device, 0x404000, 0xc0000000); 994 nvkm_wr32(device, 0x400108, 0x00000001); 995 trap &= ~0x00000001; 996 } 997 998 if (trap & 0x00000002) { 999 u32 stat = nvkm_rd32(device, 0x404600); 1000 nvkm_error(subdev, "M2MF %08x\n", stat); 1001 nvkm_wr32(device, 0x404600, 0xc0000000); 1002 nvkm_wr32(device, 0x400108, 0x00000002); 1003 trap &= ~0x00000002; 1004 } 1005 1006 if (trap & 0x00000008) { 1007 u32 stat = nvkm_rd32(device, 0x408030); 1008 nvkm_error(subdev, "CCACHE %08x\n", stat); 1009 nvkm_wr32(device, 0x408030, 0xc0000000); 1010 nvkm_wr32(device, 0x400108, 0x00000008); 1011 trap &= ~0x00000008; 1012 } 1013 1014 if (trap & 0x00000010) { 1015 u32 stat = nvkm_rd32(device, 0x405840); 1016 nvkm_error(subdev, "SHADER %08x\n", stat); 1017 nvkm_wr32(device, 0x405840, 0xc0000000); 1018 nvkm_wr32(device, 0x400108, 0x00000010); 1019 trap &= ~0x00000010; 1020 } 1021 1022 if (trap & 0x00000040) { 1023 u32 stat = nvkm_rd32(device, 0x40601c); 1024 nvkm_error(subdev, "UNK6 %08x\n", stat); 1025 nvkm_wr32(device, 0x40601c, 0xc0000000); 1026 nvkm_wr32(device, 0x400108, 0x00000040); 1027 trap &= ~0x00000040; 1028 } 1029 1030 if (trap & 0x00000080) { 1031 u32 stat = nvkm_rd32(device, 0x404490); 1032 nvkm_error(subdev, "MACRO %08x\n", stat); 1033 nvkm_wr32(device, 0x404490, 0xc0000000); 1034 nvkm_wr32(device, 0x400108, 0x00000080); 1035 trap &= ~0x00000080; 1036 } 1037 1038 if (trap & 0x00000100) { 1039 u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff; 1040 char sked[128]; 1041 1042 nvkm_snprintbf(sked, sizeof(sked), gk104_sked_error, stat); 1043 nvkm_error(subdev, "SKED: %08x [%s]\n", stat, sked); 1044 1045 if (stat) 1046 nvkm_wr32(device, 0x407020, 0x40000000); 1047 nvkm_wr32(device, 0x400108, 0x00000100); 1048 trap &= ~0x00000100; 1049 } 1050 1051 if (trap & 0x01000000) { 1052 u32 stat = nvkm_rd32(device, 0x400118); 1053 for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { 1054 u32 mask = 0x00000001 << gpc; 1055 if (stat & mask) { 1056 gf100_gr_trap_gpc(gr, gpc); 1057 nvkm_wr32(device, 0x400118, mask); 1058 stat &= ~mask; 1059 } 1060 } 1061 nvkm_wr32(device, 0x400108, 0x01000000); 1062 trap &= ~0x01000000; 1063 } 1064 1065 if (trap & 0x02000000) { 1066 for (rop = 0; rop < gr->rop_nr; rop++) { 1067 u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); 1068 u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); 1069 nvkm_error(subdev, "ROP%d %08x %08x\n", 1070 rop, statz, statc); 1071 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); 1072 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); 1073 } 1074 nvkm_wr32(device, 0x400108, 0x02000000); 1075 trap &= ~0x02000000; 1076 } 1077 1078 if (trap) { 1079 nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap); 1080 nvkm_wr32(device, 0x400108, trap); 1081 } 1082 } 1083 1084 static void 1085 gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) 1086 { 1087 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1088 struct nvkm_device *device = subdev->device; 1089 nvkm_error(subdev, "%06x - done %08x\n", base, 1090 nvkm_rd32(device, base + 0x400)); 1091 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, 1092 nvkm_rd32(device, base + 0x800), 1093 nvkm_rd32(device, base + 0x804), 1094 nvkm_rd32(device, base + 0x808), 1095 nvkm_rd32(device, base + 0x80c)); 1096 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, 1097 nvkm_rd32(device, base + 0x810), 1098 nvkm_rd32(device, base + 0x814), 1099 nvkm_rd32(device, base + 0x818), 1100 nvkm_rd32(device, base + 0x81c)); 1101 } 1102 1103 void 1104 gf100_gr_ctxctl_debug(struct gf100_gr *gr) 1105 { 1106 struct nvkm_device *device = gr->base.engine.subdev.device; 1107 u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff; 1108 u32 gpc; 1109 1110 gf100_gr_ctxctl_debug_unit(gr, 0x409000); 1111 for (gpc = 0; gpc < gpcnr; gpc++) 1112 gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000)); 1113 } 1114 1115 static void 1116 gf100_gr_ctxctl_isr(struct gf100_gr *gr) 1117 { 1118 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1119 struct nvkm_device *device = subdev->device; 1120 u32 stat = nvkm_rd32(device, 0x409c18); 1121 1122 if (stat & 0x00000001) { 1123 u32 code = nvkm_rd32(device, 0x409814); 1124 if (code == E_BAD_FWMTHD) { 1125 u32 class = nvkm_rd32(device, 0x409808); 1126 u32 addr = nvkm_rd32(device, 0x40980c); 1127 u32 subc = (addr & 0x00070000) >> 16; 1128 u32 mthd = (addr & 0x00003ffc); 1129 u32 data = nvkm_rd32(device, 0x409810); 1130 1131 nvkm_error(subdev, "FECS MTHD subc %d class %04x " 1132 "mthd %04x data %08x\n", 1133 subc, class, mthd, data); 1134 1135 nvkm_wr32(device, 0x409c20, 0x00000001); 1136 stat &= ~0x00000001; 1137 } else { 1138 nvkm_error(subdev, "FECS ucode error %d\n", code); 1139 } 1140 } 1141 1142 if (stat & 0x00080000) { 1143 nvkm_error(subdev, "FECS watchdog timeout\n"); 1144 gf100_gr_ctxctl_debug(gr); 1145 nvkm_wr32(device, 0x409c20, 0x00080000); 1146 stat &= ~0x00080000; 1147 } 1148 1149 if (stat) { 1150 nvkm_error(subdev, "FECS %08x\n", stat); 1151 gf100_gr_ctxctl_debug(gr); 1152 nvkm_wr32(device, 0x409c20, stat); 1153 } 1154 } 1155 1156 static void 1157 gf100_gr_intr(struct nvkm_subdev *subdev) 1158 { 1159 struct gf100_gr *gr = (void *)subdev; 1160 struct nvkm_device *device = gr->base.engine.subdev.device; 1161 struct nvkm_fifo_chan *chan; 1162 unsigned long flags; 1163 u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; 1164 u32 stat = nvkm_rd32(device, 0x400100); 1165 u32 addr = nvkm_rd32(device, 0x400704); 1166 u32 mthd = (addr & 0x00003ffc); 1167 u32 subc = (addr & 0x00070000) >> 16; 1168 u32 data = nvkm_rd32(device, 0x400708); 1169 u32 code = nvkm_rd32(device, 0x400110); 1170 u32 class; 1171 int chid; 1172 1173 chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags); 1174 chid = chan ? chan->chid : -1; 1175 1176 if (nv_device(gr)->card_type < NV_E0 || subc < 4) 1177 class = nvkm_rd32(device, 0x404200 + (subc * 4)); 1178 else 1179 class = 0x0000; 1180 1181 if (stat & 0x00000001) { 1182 /* 1183 * notifier interrupt, only needed for cyclestats 1184 * can be safely ignored 1185 */ 1186 nvkm_wr32(device, 0x400100, 0x00000001); 1187 stat &= ~0x00000001; 1188 } 1189 1190 if (stat & 0x00000010) { 1191 if (!gf100_gr_mthd_sw(device, class, mthd, data)) { 1192 nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] " 1193 "subc %d class %04x mthd %04x data %08x\n", 1194 chid, inst << 12, nvkm_client_name(chan), 1195 subc, class, mthd, data); 1196 } 1197 nvkm_wr32(device, 0x400100, 0x00000010); 1198 stat &= ~0x00000010; 1199 } 1200 1201 if (stat & 0x00000020) { 1202 nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] " 1203 "subc %d class %04x mthd %04x data %08x\n", 1204 chid, inst << 12, nvkm_client_name(chan), subc, 1205 class, mthd, data); 1206 nvkm_wr32(device, 0x400100, 0x00000020); 1207 stat &= ~0x00000020; 1208 } 1209 1210 if (stat & 0x00100000) { 1211 const struct nvkm_enum *en = 1212 nvkm_enum_find(nv50_data_error_names, code); 1213 nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] " 1214 "subc %d class %04x mthd %04x data %08x\n", 1215 code, en ? en->name : "", chid, inst << 12, 1216 nvkm_client_name(chan), subc, class, mthd, data); 1217 nvkm_wr32(device, 0x400100, 0x00100000); 1218 stat &= ~0x00100000; 1219 } 1220 1221 if (stat & 0x00200000) { 1222 nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n", 1223 chid, inst << 12, nvkm_client_name(chan)); 1224 gf100_gr_trap_intr(gr); 1225 nvkm_wr32(device, 0x400100, 0x00200000); 1226 stat &= ~0x00200000; 1227 } 1228 1229 if (stat & 0x00080000) { 1230 gf100_gr_ctxctl_isr(gr); 1231 nvkm_wr32(device, 0x400100, 0x00080000); 1232 stat &= ~0x00080000; 1233 } 1234 1235 if (stat) { 1236 nvkm_error(subdev, "intr %08x\n", stat); 1237 nvkm_wr32(device, 0x400100, stat); 1238 } 1239 1240 nvkm_wr32(device, 0x400500, 0x00010001); 1241 nvkm_fifo_chan_put(device->fifo, flags, &chan); 1242 } 1243 1244 void 1245 gf100_gr_init_fw(struct gf100_gr *gr, u32 fuc_base, 1246 struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) 1247 { 1248 struct nvkm_device *device = gr->base.engine.subdev.device; 1249 int i; 1250 1251 nvkm_wr32(device, fuc_base + 0x01c0, 0x01000000); 1252 for (i = 0; i < data->size / 4; i++) 1253 nvkm_wr32(device, fuc_base + 0x01c4, data->data[i]); 1254 1255 nvkm_wr32(device, fuc_base + 0x0180, 0x01000000); 1256 for (i = 0; i < code->size / 4; i++) { 1257 if ((i & 0x3f) == 0) 1258 nvkm_wr32(device, fuc_base + 0x0188, i >> 6); 1259 nvkm_wr32(device, fuc_base + 0x0184, code->data[i]); 1260 } 1261 1262 /* code must be padded to 0x40 words */ 1263 for (; i & 0x3f; i++) 1264 nvkm_wr32(device, fuc_base + 0x0184, 0); 1265 } 1266 1267 static void 1268 gf100_gr_init_csdata(struct gf100_gr *gr, 1269 const struct gf100_gr_pack *pack, 1270 u32 falcon, u32 starstar, u32 base) 1271 { 1272 struct nvkm_device *device = gr->base.engine.subdev.device; 1273 const struct gf100_gr_pack *iter; 1274 const struct gf100_gr_init *init; 1275 u32 addr = ~0, prev = ~0, xfer = 0; 1276 u32 star, temp; 1277 1278 nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar); 1279 star = nvkm_rd32(device, falcon + 0x01c4); 1280 temp = nvkm_rd32(device, falcon + 0x01c4); 1281 if (temp > star) 1282 star = temp; 1283 nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star); 1284 1285 pack_for_each_init(init, iter, pack) { 1286 u32 head = init->addr - base; 1287 u32 tail = head + init->count * init->pitch; 1288 while (head < tail) { 1289 if (head != prev + 4 || xfer >= 32) { 1290 if (xfer) { 1291 u32 data = ((--xfer << 26) | addr); 1292 nvkm_wr32(device, falcon + 0x01c4, data); 1293 star += 4; 1294 } 1295 addr = head; 1296 xfer = 0; 1297 } 1298 prev = head; 1299 xfer = xfer + 1; 1300 head = head + init->pitch; 1301 } 1302 } 1303 1304 nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr); 1305 nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar); 1306 nvkm_wr32(device, falcon + 0x01c4, star + 4); 1307 } 1308 1309 int 1310 gf100_gr_init_ctxctl(struct gf100_gr *gr) 1311 { 1312 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1313 struct nvkm_device *device = subdev->device; 1314 struct gf100_gr_oclass *oclass = (void *)nv_object(gr)->oclass; 1315 struct gf100_grctx_oclass *cclass = (void *)nv_engine(gr)->cclass; 1316 int i; 1317 1318 if (gr->firmware) { 1319 /* load fuc microcode */ 1320 nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); 1321 gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, 1322 &gr->fuc409d); 1323 gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, 1324 &gr->fuc41ad); 1325 nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); 1326 1327 /* start both of them running */ 1328 nvkm_wr32(device, 0x409840, 0xffffffff); 1329 nvkm_wr32(device, 0x41a10c, 0x00000000); 1330 nvkm_wr32(device, 0x40910c, 0x00000000); 1331 nvkm_wr32(device, 0x41a100, 0x00000002); 1332 nvkm_wr32(device, 0x409100, 0x00000002); 1333 if (nvkm_msec(device, 2000, 1334 if (nvkm_rd32(device, 0x409800) & 0x00000001) 1335 break; 1336 ) < 0) 1337 return -EBUSY; 1338 1339 nvkm_wr32(device, 0x409840, 0xffffffff); 1340 nvkm_wr32(device, 0x409500, 0x7fffffff); 1341 nvkm_wr32(device, 0x409504, 0x00000021); 1342 1343 nvkm_wr32(device, 0x409840, 0xffffffff); 1344 nvkm_wr32(device, 0x409500, 0x00000000); 1345 nvkm_wr32(device, 0x409504, 0x00000010); 1346 if (nvkm_msec(device, 2000, 1347 if ((gr->size = nvkm_rd32(device, 0x409800))) 1348 break; 1349 ) < 0) 1350 return -EBUSY; 1351 1352 nvkm_wr32(device, 0x409840, 0xffffffff); 1353 nvkm_wr32(device, 0x409500, 0x00000000); 1354 nvkm_wr32(device, 0x409504, 0x00000016); 1355 if (nvkm_msec(device, 2000, 1356 if (nvkm_rd32(device, 0x409800)) 1357 break; 1358 ) < 0) 1359 return -EBUSY; 1360 1361 nvkm_wr32(device, 0x409840, 0xffffffff); 1362 nvkm_wr32(device, 0x409500, 0x00000000); 1363 nvkm_wr32(device, 0x409504, 0x00000025); 1364 if (nvkm_msec(device, 2000, 1365 if (nvkm_rd32(device, 0x409800)) 1366 break; 1367 ) < 0) 1368 return -EBUSY; 1369 1370 if (nv_device(gr)->chipset >= 0xe0) { 1371 nvkm_wr32(device, 0x409800, 0x00000000); 1372 nvkm_wr32(device, 0x409500, 0x00000001); 1373 nvkm_wr32(device, 0x409504, 0x00000030); 1374 if (nvkm_msec(device, 2000, 1375 if (nvkm_rd32(device, 0x409800)) 1376 break; 1377 ) < 0) 1378 return -EBUSY; 1379 1380 nvkm_wr32(device, 0x409810, 0xb00095c8); 1381 nvkm_wr32(device, 0x409800, 0x00000000); 1382 nvkm_wr32(device, 0x409500, 0x00000001); 1383 nvkm_wr32(device, 0x409504, 0x00000031); 1384 if (nvkm_msec(device, 2000, 1385 if (nvkm_rd32(device, 0x409800)) 1386 break; 1387 ) < 0) 1388 return -EBUSY; 1389 1390 nvkm_wr32(device, 0x409810, 0x00080420); 1391 nvkm_wr32(device, 0x409800, 0x00000000); 1392 nvkm_wr32(device, 0x409500, 0x00000001); 1393 nvkm_wr32(device, 0x409504, 0x00000032); 1394 if (nvkm_msec(device, 2000, 1395 if (nvkm_rd32(device, 0x409800)) 1396 break; 1397 ) < 0) 1398 return -EBUSY; 1399 1400 nvkm_wr32(device, 0x409614, 0x00000070); 1401 nvkm_wr32(device, 0x409614, 0x00000770); 1402 nvkm_wr32(device, 0x40802c, 0x00000001); 1403 } 1404 1405 if (gr->data == NULL) { 1406 int ret = gf100_grctx_generate(gr); 1407 if (ret) { 1408 nvkm_error(subdev, "failed to construct context\n"); 1409 return ret; 1410 } 1411 } 1412 1413 return 0; 1414 } else 1415 if (!oclass->fecs.ucode) { 1416 return -ENOSYS; 1417 } 1418 1419 /* load HUB microcode */ 1420 nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); 1421 nvkm_wr32(device, 0x4091c0, 0x01000000); 1422 for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) 1423 nvkm_wr32(device, 0x4091c4, oclass->fecs.ucode->data.data[i]); 1424 1425 nvkm_wr32(device, 0x409180, 0x01000000); 1426 for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) { 1427 if ((i & 0x3f) == 0) 1428 nvkm_wr32(device, 0x409188, i >> 6); 1429 nvkm_wr32(device, 0x409184, oclass->fecs.ucode->code.data[i]); 1430 } 1431 1432 /* load GPC microcode */ 1433 nvkm_wr32(device, 0x41a1c0, 0x01000000); 1434 for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++) 1435 nvkm_wr32(device, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); 1436 1437 nvkm_wr32(device, 0x41a180, 0x01000000); 1438 for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) { 1439 if ((i & 0x3f) == 0) 1440 nvkm_wr32(device, 0x41a188, i >> 6); 1441 nvkm_wr32(device, 0x41a184, oclass->gpccs.ucode->code.data[i]); 1442 } 1443 nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); 1444 1445 /* load register lists */ 1446 gf100_gr_init_csdata(gr, cclass->hub, 0x409000, 0x000, 0x000000); 1447 gf100_gr_init_csdata(gr, cclass->gpc, 0x41a000, 0x000, 0x418000); 1448 gf100_gr_init_csdata(gr, cclass->tpc, 0x41a000, 0x004, 0x419800); 1449 gf100_gr_init_csdata(gr, cclass->ppc, 0x41a000, 0x008, 0x41be00); 1450 1451 /* start HUB ucode running, it'll init the GPCs */ 1452 nvkm_wr32(device, 0x40910c, 0x00000000); 1453 nvkm_wr32(device, 0x409100, 0x00000002); 1454 if (nvkm_msec(device, 2000, 1455 if (nvkm_rd32(device, 0x409800) & 0x80000000) 1456 break; 1457 ) < 0) { 1458 gf100_gr_ctxctl_debug(gr); 1459 return -EBUSY; 1460 } 1461 1462 gr->size = nvkm_rd32(device, 0x409804); 1463 if (gr->data == NULL) { 1464 int ret = gf100_grctx_generate(gr); 1465 if (ret) { 1466 nvkm_error(subdev, "failed to construct context\n"); 1467 return ret; 1468 } 1469 } 1470 1471 return 0; 1472 } 1473 1474 int 1475 gf100_gr_init(struct nvkm_object *object) 1476 { 1477 struct gf100_gr *gr = (void *)object; 1478 struct nvkm_device *device = gr->base.engine.subdev.device; 1479 struct gf100_gr_oclass *oclass = (void *)object->oclass; 1480 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); 1481 u32 data[TPC_MAX / 8] = {}; 1482 u8 tpcnr[GPC_MAX]; 1483 int gpc, tpc, rop; 1484 int ret, i; 1485 1486 ret = nvkm_gr_init(&gr->base); 1487 if (ret) 1488 return ret; 1489 1490 nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); 1491 nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000); 1492 nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000); 1493 nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000); 1494 nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); 1495 nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); 1496 nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); 1497 nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); 1498 1499 gf100_gr_mmio(gr, oclass->mmio); 1500 1501 memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); 1502 for (i = 0, gpc = -1; i < gr->tpc_total; i++) { 1503 do { 1504 gpc = (gpc + 1) % gr->gpc_nr; 1505 } while (!tpcnr[gpc]); 1506 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; 1507 1508 data[i / 8] |= tpc << ((i % 8) * 4); 1509 } 1510 1511 nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); 1512 nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); 1513 nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); 1514 nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); 1515 1516 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 1517 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), 1518 gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); 1519 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | 1520 gr->tpc_total); 1521 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); 1522 } 1523 1524 if (nv_device(gr)->chipset != 0xd7) 1525 nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); 1526 else 1527 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); 1528 1529 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); 1530 1531 nvkm_wr32(device, 0x400500, 0x00010001); 1532 1533 nvkm_wr32(device, 0x400100, 0xffffffff); 1534 nvkm_wr32(device, 0x40013c, 0xffffffff); 1535 1536 nvkm_wr32(device, 0x409c24, 0x000f0000); 1537 nvkm_wr32(device, 0x404000, 0xc0000000); 1538 nvkm_wr32(device, 0x404600, 0xc0000000); 1539 nvkm_wr32(device, 0x408030, 0xc0000000); 1540 nvkm_wr32(device, 0x40601c, 0xc0000000); 1541 nvkm_wr32(device, 0x404490, 0xc0000000); 1542 nvkm_wr32(device, 0x406018, 0xc0000000); 1543 nvkm_wr32(device, 0x405840, 0xc0000000); 1544 nvkm_wr32(device, 0x405844, 0x00ffffff); 1545 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); 1546 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); 1547 1548 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 1549 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); 1550 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); 1551 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); 1552 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); 1553 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { 1554 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); 1555 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); 1556 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); 1557 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); 1558 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); 1559 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); 1560 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); 1561 } 1562 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); 1563 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); 1564 } 1565 1566 for (rop = 0; rop < gr->rop_nr; rop++) { 1567 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); 1568 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); 1569 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); 1570 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); 1571 } 1572 1573 nvkm_wr32(device, 0x400108, 0xffffffff); 1574 nvkm_wr32(device, 0x400138, 0xffffffff); 1575 nvkm_wr32(device, 0x400118, 0xffffffff); 1576 nvkm_wr32(device, 0x400130, 0xffffffff); 1577 nvkm_wr32(device, 0x40011c, 0xffffffff); 1578 nvkm_wr32(device, 0x400134, 0xffffffff); 1579 1580 nvkm_wr32(device, 0x400054, 0x34ce3464); 1581 1582 gf100_gr_zbc_init(gr); 1583 1584 return gf100_gr_init_ctxctl(gr); 1585 } 1586 1587 void 1588 gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) 1589 { 1590 kfree(fuc->data); 1591 fuc->data = NULL; 1592 } 1593 1594 int 1595 gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, 1596 struct gf100_gr_fuc *fuc) 1597 { 1598 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1599 struct nvkm_device *device = subdev->device; 1600 const struct firmware *fw; 1601 char f[64]; 1602 char cname[16]; 1603 int ret; 1604 int i; 1605 1606 /* Convert device name to lowercase */ 1607 strncpy(cname, device->chip->name, sizeof(cname)); 1608 cname[sizeof(cname) - 1] = '\0'; 1609 i = strlen(cname); 1610 while (i) { 1611 --i; 1612 cname[i] = tolower(cname[i]); 1613 } 1614 1615 snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); 1616 ret = request_firmware(&fw, f, nv_device_base(device)); 1617 if (ret) { 1618 nvkm_error(subdev, "failed to load %s\n", fwname); 1619 return ret; 1620 } 1621 1622 fuc->size = fw->size; 1623 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); 1624 release_firmware(fw); 1625 return (fuc->data != NULL) ? 0 : -ENOMEM; 1626 } 1627 1628 void 1629 gf100_gr_dtor(struct nvkm_object *object) 1630 { 1631 struct gf100_gr *gr = (void *)object; 1632 1633 kfree(gr->data); 1634 1635 gf100_gr_dtor_fw(&gr->fuc409c); 1636 gf100_gr_dtor_fw(&gr->fuc409d); 1637 gf100_gr_dtor_fw(&gr->fuc41ac); 1638 gf100_gr_dtor_fw(&gr->fuc41ad); 1639 1640 nvkm_memory_del(&gr->unk4188b8); 1641 nvkm_memory_del(&gr->unk4188b4); 1642 1643 nvkm_gr_destroy(&gr->base); 1644 } 1645 1646 int 1647 gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 1648 struct nvkm_oclass *bclass, void *data, u32 size, 1649 struct nvkm_object **pobject) 1650 { 1651 struct gf100_gr_oclass *oclass = (void *)bclass; 1652 struct nvkm_device *device = (void *)parent; 1653 struct gf100_gr *gr; 1654 bool use_ext_fw, enable; 1655 int ret, i, j; 1656 1657 use_ext_fw = nvkm_boolopt(device->cfgopt, "NvGrUseFW", 1658 oclass->fecs.ucode == NULL); 1659 enable = use_ext_fw || oclass->fecs.ucode != NULL; 1660 1661 ret = nvkm_gr_create(parent, engine, bclass, enable, &gr); 1662 *pobject = nv_object(gr); 1663 if (ret) 1664 return ret; 1665 1666 nv_subdev(gr)->unit = 0x08001000; 1667 nv_subdev(gr)->intr = gf100_gr_intr; 1668 1669 gr->base.units = gf100_gr_units; 1670 1671 if (use_ext_fw) { 1672 nvkm_info(&gr->base.engine.subdev, "using external firmware\n"); 1673 if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || 1674 gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || 1675 gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || 1676 gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) 1677 return -ENODEV; 1678 gr->firmware = true; 1679 } 1680 1681 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, 1682 &gr->unk4188b4); 1683 if (ret) 1684 return ret; 1685 1686 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, 1687 &gr->unk4188b8); 1688 if (ret) 1689 return ret; 1690 1691 nvkm_kmap(gr->unk4188b4); 1692 for (i = 0; i < 0x1000; i += 4) 1693 nvkm_wo32(gr->unk4188b4, i, 0x00000010); 1694 nvkm_done(gr->unk4188b4); 1695 1696 nvkm_kmap(gr->unk4188b8); 1697 for (i = 0; i < 0x1000; i += 4) 1698 nvkm_wo32(gr->unk4188b8, i, 0x00000010); 1699 nvkm_done(gr->unk4188b8); 1700 1701 gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; 1702 gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; 1703 for (i = 0; i < gr->gpc_nr; i++) { 1704 gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); 1705 gr->tpc_total += gr->tpc_nr[i]; 1706 gr->ppc_nr[i] = oclass->ppc_nr; 1707 for (j = 0; j < gr->ppc_nr[i]; j++) { 1708 u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); 1709 gr->ppc_tpc_nr[i][j] = hweight8(mask); 1710 } 1711 } 1712 1713 /*XXX: these need figuring out... though it might not even matter */ 1714 switch (nv_device(gr)->chipset) { 1715 case 0xc0: 1716 if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ 1717 gr->magic_not_rop_nr = 0x07; 1718 } else 1719 if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ 1720 gr->magic_not_rop_nr = 0x05; 1721 } else 1722 if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ 1723 gr->magic_not_rop_nr = 0x06; 1724 } 1725 break; 1726 case 0xc3: /* 450, 4/0/0/0, 2 */ 1727 gr->magic_not_rop_nr = 0x03; 1728 break; 1729 case 0xc4: /* 460, 3/4/0/0, 4 */ 1730 gr->magic_not_rop_nr = 0x01; 1731 break; 1732 case 0xc1: /* 2/0/0/0, 1 */ 1733 gr->magic_not_rop_nr = 0x01; 1734 break; 1735 case 0xc8: /* 4/4/3/4, 5 */ 1736 gr->magic_not_rop_nr = 0x06; 1737 break; 1738 case 0xce: /* 4/4/0/0, 4 */ 1739 gr->magic_not_rop_nr = 0x03; 1740 break; 1741 case 0xcf: /* 4/0/0/0, 3 */ 1742 gr->magic_not_rop_nr = 0x03; 1743 break; 1744 case 0xd7: 1745 case 0xd9: /* 1/0/0/0, 1 */ 1746 case 0xea: /* gk20a */ 1747 case 0x12b: /* gm20b */ 1748 gr->magic_not_rop_nr = 0x01; 1749 break; 1750 } 1751 1752 nv_engine(gr)->cclass = *oclass->cclass; 1753 nv_engine(gr)->sclass = oclass->sclass; 1754 return 0; 1755 } 1756 1757 #include "fuc/hubgf100.fuc3.h" 1758 1759 struct gf100_gr_ucode 1760 gf100_gr_fecs_ucode = { 1761 .code.data = gf100_grhub_code, 1762 .code.size = sizeof(gf100_grhub_code), 1763 .data.data = gf100_grhub_data, 1764 .data.size = sizeof(gf100_grhub_data), 1765 }; 1766 1767 #include "fuc/gpcgf100.fuc3.h" 1768 1769 struct gf100_gr_ucode 1770 gf100_gr_gpccs_ucode = { 1771 .code.data = gf100_grgpc_code, 1772 .code.size = sizeof(gf100_grgpc_code), 1773 .data.data = gf100_grgpc_data, 1774 .data.size = sizeof(gf100_grgpc_data), 1775 }; 1776 1777 struct nvkm_oclass * 1778 gf100_gr_oclass = &(struct gf100_gr_oclass) { 1779 .base.handle = NV_ENGINE(GR, 0xc0), 1780 .base.ofuncs = &(struct nvkm_ofuncs) { 1781 .ctor = gf100_gr_ctor, 1782 .dtor = gf100_gr_dtor, 1783 .init = gf100_gr_init, 1784 .fini = _nvkm_gr_fini, 1785 }, 1786 .cclass = &gf100_grctx_oclass, 1787 .sclass = gf100_gr_sclass, 1788 .mmio = gf100_gr_pack_mmio, 1789 .fecs.ucode = &gf100_gr_fecs_ucode, 1790 .gpccs.ucode = &gf100_gr_gpccs_ucode, 1791 }.base; 1792