1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "gf100.h" 25 #include "ctxgf100.h" 26 #include "fuc/os.h" 27 28 #include <core/client.h> 29 #include <core/option.h> 30 #include <subdev/fb.h> 31 #include <subdev/mc.h> 32 #include <subdev/pmu.h> 33 #include <subdev/timer.h> 34 #include <engine/fifo.h> 35 36 #include <nvif/class.h> 37 #include <nvif/cl9097.h> 38 #include <nvif/unpack.h> 39 40 /******************************************************************************* 41 * Zero Bandwidth Clear 42 ******************************************************************************/ 43 44 static void 45 gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) 46 { 47 struct nvkm_device *device = gr->base.engine.subdev.device; 48 if (gr->zbc_color[zbc].format) { 49 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); 50 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); 51 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); 52 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); 53 } 54 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); 55 nvkm_wr32(device, 0x405820, zbc); 56 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ 57 } 58 59 static int 60 gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, 61 const u32 ds[4], const u32 l2[4]) 62 { 63 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; 64 int zbc = -ENOSPC, i; 65 66 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { 67 if (gr->zbc_color[i].format) { 68 if (gr->zbc_color[i].format != format) 69 continue; 70 if (memcmp(gr->zbc_color[i].ds, ds, sizeof( 71 gr->zbc_color[i].ds))) 72 continue; 73 if (memcmp(gr->zbc_color[i].l2, l2, sizeof( 74 gr->zbc_color[i].l2))) { 75 WARN_ON(1); 76 return -EINVAL; 77 } 78 return i; 79 } else { 80 zbc = (zbc < 0) ? i : zbc; 81 } 82 } 83 84 if (zbc < 0) 85 return zbc; 86 87 memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); 88 memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); 89 gr->zbc_color[zbc].format = format; 90 nvkm_ltc_zbc_color_get(ltc, zbc, l2); 91 gf100_gr_zbc_clear_color(gr, zbc); 92 return zbc; 93 } 94 95 static void 96 gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) 97 { 98 struct nvkm_device *device = gr->base.engine.subdev.device; 99 if (gr->zbc_depth[zbc].format) 100 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); 101 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); 102 nvkm_wr32(device, 0x405820, zbc); 103 nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ 104 } 105 106 static int 107 gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, 108 const u32 ds, const u32 l2) 109 { 110 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; 111 int zbc = -ENOSPC, i; 112 113 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { 114 if (gr->zbc_depth[i].format) { 115 if (gr->zbc_depth[i].format != format) 116 continue; 117 if (gr->zbc_depth[i].ds != ds) 118 continue; 119 if (gr->zbc_depth[i].l2 != l2) { 120 WARN_ON(1); 121 return -EINVAL; 122 } 123 return i; 124 } else { 125 zbc = (zbc < 0) ? i : zbc; 126 } 127 } 128 129 if (zbc < 0) 130 return zbc; 131 132 gr->zbc_depth[zbc].format = format; 133 gr->zbc_depth[zbc].ds = ds; 134 gr->zbc_depth[zbc].l2 = l2; 135 nvkm_ltc_zbc_depth_get(ltc, zbc, l2); 136 gf100_gr_zbc_clear_depth(gr, zbc); 137 return zbc; 138 } 139 140 /******************************************************************************* 141 * Graphics object classes 142 ******************************************************************************/ 143 #define gf100_gr_object(p) container_of((p), struct gf100_gr_object, object) 144 145 struct gf100_gr_object { 146 struct nvkm_object object; 147 struct gf100_gr_chan *chan; 148 }; 149 150 static int 151 gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) 152 { 153 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); 154 union { 155 struct fermi_a_zbc_color_v0 v0; 156 } *args = data; 157 int ret = -ENOSYS; 158 159 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { 160 switch (args->v0.format) { 161 case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: 162 case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: 163 case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32: 164 case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16: 165 case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16: 166 case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16: 167 case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16: 168 case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16: 169 case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8: 170 case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8: 171 case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10: 172 case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10: 173 case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8: 174 case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8: 175 case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8: 176 case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8: 177 case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: 178 case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: 179 case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: 180 ret = gf100_gr_zbc_color_get(gr, args->v0.format, 181 args->v0.ds, 182 args->v0.l2); 183 if (ret >= 0) { 184 args->v0.index = ret; 185 return 0; 186 } 187 break; 188 default: 189 return -EINVAL; 190 } 191 } 192 193 return ret; 194 } 195 196 static int 197 gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) 198 { 199 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); 200 union { 201 struct fermi_a_zbc_depth_v0 v0; 202 } *args = data; 203 int ret = -ENOSYS; 204 205 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { 206 switch (args->v0.format) { 207 case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: 208 ret = gf100_gr_zbc_depth_get(gr, args->v0.format, 209 args->v0.ds, 210 args->v0.l2); 211 return (ret >= 0) ? 0 : -ENOSPC; 212 default: 213 return -EINVAL; 214 } 215 } 216 217 return ret; 218 } 219 220 static int 221 gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) 222 { 223 nvif_ioctl(object, "fermi mthd %08x\n", mthd); 224 switch (mthd) { 225 case FERMI_A_ZBC_COLOR: 226 return gf100_fermi_mthd_zbc_color(object, data, size); 227 case FERMI_A_ZBC_DEPTH: 228 return gf100_fermi_mthd_zbc_depth(object, data, size); 229 default: 230 break; 231 } 232 return -EINVAL; 233 } 234 235 const struct nvkm_object_func 236 gf100_fermi = { 237 .mthd = gf100_fermi_mthd, 238 }; 239 240 static void 241 gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data) 242 { 243 nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000); 244 nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000); 245 } 246 247 static bool 248 gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data) 249 { 250 switch (class & 0x00ff) { 251 case 0x97: 252 case 0xc0: 253 switch (mthd) { 254 case 0x1528: 255 gf100_gr_mthd_set_shader_exceptions(device, data); 256 return true; 257 default: 258 break; 259 } 260 break; 261 default: 262 break; 263 } 264 return false; 265 } 266 267 static const struct nvkm_object_func 268 gf100_gr_object_func = { 269 }; 270 271 static int 272 gf100_gr_object_new(const struct nvkm_oclass *oclass, void *data, u32 size, 273 struct nvkm_object **pobject) 274 { 275 struct gf100_gr_chan *chan = gf100_gr_chan(oclass->parent); 276 struct gf100_gr_object *object; 277 278 if (!(object = kzalloc(sizeof(*object), GFP_KERNEL))) 279 return -ENOMEM; 280 *pobject = &object->object; 281 282 nvkm_object_ctor(oclass->base.func ? oclass->base.func : 283 &gf100_gr_object_func, oclass, &object->object); 284 object->chan = chan; 285 return 0; 286 } 287 288 static int 289 gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass) 290 { 291 struct gf100_gr *gr = gf100_gr(base); 292 int c = 0; 293 294 while (gr->func->sclass[c].oclass) { 295 if (c++ == index) { 296 *sclass = gr->func->sclass[index]; 297 sclass->ctor = gf100_gr_object_new; 298 return index; 299 } 300 } 301 302 return c; 303 } 304 305 /******************************************************************************* 306 * PGRAPH context 307 ******************************************************************************/ 308 309 static int 310 gf100_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, 311 int align, struct nvkm_gpuobj **pgpuobj) 312 { 313 struct gf100_gr_chan *chan = gf100_gr_chan(object); 314 struct gf100_gr *gr = chan->gr; 315 int ret, i; 316 317 ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, 318 align, false, parent, pgpuobj); 319 if (ret) 320 return ret; 321 322 nvkm_kmap(*pgpuobj); 323 for (i = 0; i < gr->size; i += 4) 324 nvkm_wo32(*pgpuobj, i, gr->data[i / 4]); 325 326 if (!gr->firmware) { 327 nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2); 328 nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma.offset >> 8); 329 } else { 330 nvkm_wo32(*pgpuobj, 0xf4, 0); 331 nvkm_wo32(*pgpuobj, 0xf8, 0); 332 nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2); 333 nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma.offset)); 334 nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma.offset)); 335 nvkm_wo32(*pgpuobj, 0x1c, 1); 336 nvkm_wo32(*pgpuobj, 0x20, 0); 337 nvkm_wo32(*pgpuobj, 0x28, 0); 338 nvkm_wo32(*pgpuobj, 0x2c, 0); 339 } 340 nvkm_done(*pgpuobj); 341 return 0; 342 } 343 344 static void * 345 gf100_gr_chan_dtor(struct nvkm_object *object) 346 { 347 struct gf100_gr_chan *chan = gf100_gr_chan(object); 348 int i; 349 350 for (i = 0; i < ARRAY_SIZE(chan->data); i++) { 351 if (chan->data[i].vma.node) { 352 nvkm_vm_unmap(&chan->data[i].vma); 353 nvkm_vm_put(&chan->data[i].vma); 354 } 355 nvkm_memory_del(&chan->data[i].mem); 356 } 357 358 if (chan->mmio_vma.node) { 359 nvkm_vm_unmap(&chan->mmio_vma); 360 nvkm_vm_put(&chan->mmio_vma); 361 } 362 nvkm_memory_del(&chan->mmio); 363 return chan; 364 } 365 366 static const struct nvkm_object_func 367 gf100_gr_chan = { 368 .dtor = gf100_gr_chan_dtor, 369 .bind = gf100_gr_chan_bind, 370 }; 371 372 static int 373 gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, 374 const struct nvkm_oclass *oclass, 375 struct nvkm_object **pobject) 376 { 377 struct gf100_gr *gr = gf100_gr(base); 378 struct gf100_gr_data *data = gr->mmio_data; 379 struct gf100_gr_mmio *mmio = gr->mmio_list; 380 struct gf100_gr_chan *chan; 381 struct nvkm_device *device = gr->base.engine.subdev.device; 382 int ret, i; 383 384 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) 385 return -ENOMEM; 386 nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object); 387 chan->gr = gr; 388 *pobject = &chan->object; 389 390 /* allocate memory for a "mmio list" buffer that's used by the HUB 391 * fuc to modify some per-context register settings on first load 392 * of the context. 393 */ 394 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100, 395 false, &chan->mmio); 396 if (ret) 397 return ret; 398 399 ret = nvkm_vm_get(fifoch->vm, 0x1000, 12, NV_MEM_ACCESS_RW | 400 NV_MEM_ACCESS_SYS, &chan->mmio_vma); 401 if (ret) 402 return ret; 403 404 nvkm_memory_map(chan->mmio, &chan->mmio_vma, 0); 405 406 /* allocate buffers referenced by mmio list */ 407 for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) { 408 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 409 data->size, data->align, false, 410 &chan->data[i].mem); 411 if (ret) 412 return ret; 413 414 ret = nvkm_vm_get(fifoch->vm, 415 nvkm_memory_size(chan->data[i].mem), 12, 416 data->access, &chan->data[i].vma); 417 if (ret) 418 return ret; 419 420 nvkm_memory_map(chan->data[i].mem, &chan->data[i].vma, 0); 421 data++; 422 } 423 424 /* finally, fill in the mmio list and point the context at it */ 425 nvkm_kmap(chan->mmio); 426 for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) { 427 u32 addr = mmio->addr; 428 u32 data = mmio->data; 429 430 if (mmio->buffer >= 0) { 431 u64 info = chan->data[mmio->buffer].vma.offset; 432 data |= info >> mmio->shift; 433 } 434 435 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); 436 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data); 437 mmio++; 438 } 439 nvkm_done(chan->mmio); 440 return 0; 441 } 442 443 /******************************************************************************* 444 * PGRAPH register lists 445 ******************************************************************************/ 446 447 const struct gf100_gr_init 448 gf100_gr_init_main_0[] = { 449 { 0x400080, 1, 0x04, 0x003083c2 }, 450 { 0x400088, 1, 0x04, 0x00006fe7 }, 451 { 0x40008c, 1, 0x04, 0x00000000 }, 452 { 0x400090, 1, 0x04, 0x00000030 }, 453 { 0x40013c, 1, 0x04, 0x013901f7 }, 454 { 0x400140, 1, 0x04, 0x00000100 }, 455 { 0x400144, 1, 0x04, 0x00000000 }, 456 { 0x400148, 1, 0x04, 0x00000110 }, 457 { 0x400138, 1, 0x04, 0x00000000 }, 458 { 0x400130, 2, 0x04, 0x00000000 }, 459 { 0x400124, 1, 0x04, 0x00000002 }, 460 {} 461 }; 462 463 const struct gf100_gr_init 464 gf100_gr_init_fe_0[] = { 465 { 0x40415c, 1, 0x04, 0x00000000 }, 466 { 0x404170, 1, 0x04, 0x00000000 }, 467 {} 468 }; 469 470 const struct gf100_gr_init 471 gf100_gr_init_pri_0[] = { 472 { 0x404488, 2, 0x04, 0x00000000 }, 473 {} 474 }; 475 476 const struct gf100_gr_init 477 gf100_gr_init_rstr2d_0[] = { 478 { 0x407808, 1, 0x04, 0x00000000 }, 479 {} 480 }; 481 482 const struct gf100_gr_init 483 gf100_gr_init_pd_0[] = { 484 { 0x406024, 1, 0x04, 0x00000000 }, 485 {} 486 }; 487 488 const struct gf100_gr_init 489 gf100_gr_init_ds_0[] = { 490 { 0x405844, 1, 0x04, 0x00ffffff }, 491 { 0x405850, 1, 0x04, 0x00000000 }, 492 { 0x405908, 1, 0x04, 0x00000000 }, 493 {} 494 }; 495 496 const struct gf100_gr_init 497 gf100_gr_init_scc_0[] = { 498 { 0x40803c, 1, 0x04, 0x00000000 }, 499 {} 500 }; 501 502 const struct gf100_gr_init 503 gf100_gr_init_prop_0[] = { 504 { 0x4184a0, 1, 0x04, 0x00000000 }, 505 {} 506 }; 507 508 const struct gf100_gr_init 509 gf100_gr_init_gpc_unk_0[] = { 510 { 0x418604, 1, 0x04, 0x00000000 }, 511 { 0x418680, 1, 0x04, 0x00000000 }, 512 { 0x418714, 1, 0x04, 0x80000000 }, 513 { 0x418384, 1, 0x04, 0x00000000 }, 514 {} 515 }; 516 517 const struct gf100_gr_init 518 gf100_gr_init_setup_0[] = { 519 { 0x418814, 3, 0x04, 0x00000000 }, 520 {} 521 }; 522 523 const struct gf100_gr_init 524 gf100_gr_init_crstr_0[] = { 525 { 0x418b04, 1, 0x04, 0x00000000 }, 526 {} 527 }; 528 529 const struct gf100_gr_init 530 gf100_gr_init_setup_1[] = { 531 { 0x4188c8, 1, 0x04, 0x80000000 }, 532 { 0x4188cc, 1, 0x04, 0x00000000 }, 533 { 0x4188d0, 1, 0x04, 0x00010000 }, 534 { 0x4188d4, 1, 0x04, 0x00000001 }, 535 {} 536 }; 537 538 const struct gf100_gr_init 539 gf100_gr_init_zcull_0[] = { 540 { 0x418910, 1, 0x04, 0x00010001 }, 541 { 0x418914, 1, 0x04, 0x00000301 }, 542 { 0x418918, 1, 0x04, 0x00800000 }, 543 { 0x418980, 1, 0x04, 0x77777770 }, 544 { 0x418984, 3, 0x04, 0x77777777 }, 545 {} 546 }; 547 548 const struct gf100_gr_init 549 gf100_gr_init_gpm_0[] = { 550 { 0x418c04, 1, 0x04, 0x00000000 }, 551 { 0x418c88, 1, 0x04, 0x00000000 }, 552 {} 553 }; 554 555 const struct gf100_gr_init 556 gf100_gr_init_gpc_unk_1[] = { 557 { 0x418d00, 1, 0x04, 0x00000000 }, 558 { 0x418f08, 1, 0x04, 0x00000000 }, 559 { 0x418e00, 1, 0x04, 0x00000050 }, 560 { 0x418e08, 1, 0x04, 0x00000000 }, 561 {} 562 }; 563 564 const struct gf100_gr_init 565 gf100_gr_init_gcc_0[] = { 566 { 0x41900c, 1, 0x04, 0x00000000 }, 567 { 0x419018, 1, 0x04, 0x00000000 }, 568 {} 569 }; 570 571 const struct gf100_gr_init 572 gf100_gr_init_tpccs_0[] = { 573 { 0x419d08, 2, 0x04, 0x00000000 }, 574 { 0x419d10, 1, 0x04, 0x00000014 }, 575 {} 576 }; 577 578 const struct gf100_gr_init 579 gf100_gr_init_tex_0[] = { 580 { 0x419ab0, 1, 0x04, 0x00000000 }, 581 { 0x419ab8, 1, 0x04, 0x000000e7 }, 582 { 0x419abc, 2, 0x04, 0x00000000 }, 583 {} 584 }; 585 586 const struct gf100_gr_init 587 gf100_gr_init_pe_0[] = { 588 { 0x41980c, 3, 0x04, 0x00000000 }, 589 { 0x419844, 1, 0x04, 0x00000000 }, 590 { 0x41984c, 1, 0x04, 0x00005bc5 }, 591 { 0x419850, 4, 0x04, 0x00000000 }, 592 {} 593 }; 594 595 const struct gf100_gr_init 596 gf100_gr_init_l1c_0[] = { 597 { 0x419c98, 1, 0x04, 0x00000000 }, 598 { 0x419ca8, 1, 0x04, 0x80000000 }, 599 { 0x419cb4, 1, 0x04, 0x00000000 }, 600 { 0x419cb8, 1, 0x04, 0x00008bf4 }, 601 { 0x419cbc, 1, 0x04, 0x28137606 }, 602 { 0x419cc0, 2, 0x04, 0x00000000 }, 603 {} 604 }; 605 606 const struct gf100_gr_init 607 gf100_gr_init_wwdx_0[] = { 608 { 0x419bd4, 1, 0x04, 0x00800000 }, 609 { 0x419bdc, 1, 0x04, 0x00000000 }, 610 {} 611 }; 612 613 const struct gf100_gr_init 614 gf100_gr_init_tpccs_1[] = { 615 { 0x419d2c, 1, 0x04, 0x00000000 }, 616 {} 617 }; 618 619 const struct gf100_gr_init 620 gf100_gr_init_mpc_0[] = { 621 { 0x419c0c, 1, 0x04, 0x00000000 }, 622 {} 623 }; 624 625 static const struct gf100_gr_init 626 gf100_gr_init_sm_0[] = { 627 { 0x419e00, 1, 0x04, 0x00000000 }, 628 { 0x419ea0, 1, 0x04, 0x00000000 }, 629 { 0x419ea4, 1, 0x04, 0x00000100 }, 630 { 0x419ea8, 1, 0x04, 0x00001100 }, 631 { 0x419eac, 1, 0x04, 0x11100702 }, 632 { 0x419eb0, 1, 0x04, 0x00000003 }, 633 { 0x419eb4, 4, 0x04, 0x00000000 }, 634 { 0x419ec8, 1, 0x04, 0x06060618 }, 635 { 0x419ed0, 1, 0x04, 0x0eff0e38 }, 636 { 0x419ed4, 1, 0x04, 0x011104f1 }, 637 { 0x419edc, 1, 0x04, 0x00000000 }, 638 { 0x419f00, 1, 0x04, 0x00000000 }, 639 { 0x419f2c, 1, 0x04, 0x00000000 }, 640 {} 641 }; 642 643 const struct gf100_gr_init 644 gf100_gr_init_be_0[] = { 645 { 0x40880c, 1, 0x04, 0x00000000 }, 646 { 0x408910, 9, 0x04, 0x00000000 }, 647 { 0x408950, 1, 0x04, 0x00000000 }, 648 { 0x408954, 1, 0x04, 0x0000ffff }, 649 { 0x408984, 1, 0x04, 0x00000000 }, 650 { 0x408988, 1, 0x04, 0x08040201 }, 651 { 0x40898c, 1, 0x04, 0x80402010 }, 652 {} 653 }; 654 655 const struct gf100_gr_init 656 gf100_gr_init_fe_1[] = { 657 { 0x4040f0, 1, 0x04, 0x00000000 }, 658 {} 659 }; 660 661 const struct gf100_gr_init 662 gf100_gr_init_pe_1[] = { 663 { 0x419880, 1, 0x04, 0x00000002 }, 664 {} 665 }; 666 667 static const struct gf100_gr_pack 668 gf100_gr_pack_mmio[] = { 669 { gf100_gr_init_main_0 }, 670 { gf100_gr_init_fe_0 }, 671 { gf100_gr_init_pri_0 }, 672 { gf100_gr_init_rstr2d_0 }, 673 { gf100_gr_init_pd_0 }, 674 { gf100_gr_init_ds_0 }, 675 { gf100_gr_init_scc_0 }, 676 { gf100_gr_init_prop_0 }, 677 { gf100_gr_init_gpc_unk_0 }, 678 { gf100_gr_init_setup_0 }, 679 { gf100_gr_init_crstr_0 }, 680 { gf100_gr_init_setup_1 }, 681 { gf100_gr_init_zcull_0 }, 682 { gf100_gr_init_gpm_0 }, 683 { gf100_gr_init_gpc_unk_1 }, 684 { gf100_gr_init_gcc_0 }, 685 { gf100_gr_init_tpccs_0 }, 686 { gf100_gr_init_tex_0 }, 687 { gf100_gr_init_pe_0 }, 688 { gf100_gr_init_l1c_0 }, 689 { gf100_gr_init_wwdx_0 }, 690 { gf100_gr_init_tpccs_1 }, 691 { gf100_gr_init_mpc_0 }, 692 { gf100_gr_init_sm_0 }, 693 { gf100_gr_init_be_0 }, 694 { gf100_gr_init_fe_1 }, 695 { gf100_gr_init_pe_1 }, 696 {} 697 }; 698 699 /******************************************************************************* 700 * PGRAPH engine/subdev functions 701 ******************************************************************************/ 702 703 void 704 gf100_gr_zbc_init(struct gf100_gr *gr) 705 { 706 const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 707 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 708 const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 709 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; 710 const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 711 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 712 const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 713 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; 714 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; 715 int index; 716 717 if (!gr->zbc_color[0].format) { 718 gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); 719 gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); 720 gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); 721 gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); 722 gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); 723 gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); 724 } 725 726 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) 727 gf100_gr_zbc_clear_color(gr, index); 728 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) 729 gf100_gr_zbc_clear_depth(gr, index); 730 } 731 732 /** 733 * Wait until GR goes idle. GR is considered idle if it is disabled by the 734 * MC (0x200) register, or GR is not busy and a context switch is not in 735 * progress. 736 */ 737 int 738 gf100_gr_wait_idle(struct gf100_gr *gr) 739 { 740 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 741 struct nvkm_device *device = subdev->device; 742 unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000); 743 bool gr_enabled, ctxsw_active, gr_busy; 744 745 do { 746 /* 747 * required to make sure FIFO_ENGINE_STATUS (0x2640) is 748 * up-to-date 749 */ 750 nvkm_rd32(device, 0x400700); 751 752 gr_enabled = nvkm_rd32(device, 0x200) & 0x1000; 753 ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000; 754 gr_busy = nvkm_rd32(device, 0x40060c) & 0x1; 755 756 if (!gr_enabled || (!gr_busy && !ctxsw_active)) 757 return 0; 758 } while (time_before(jiffies, end_jiffies)); 759 760 nvkm_error(subdev, 761 "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n", 762 gr_enabled, ctxsw_active, gr_busy); 763 return -EAGAIN; 764 } 765 766 void 767 gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) 768 { 769 struct nvkm_device *device = gr->base.engine.subdev.device; 770 const struct gf100_gr_pack *pack; 771 const struct gf100_gr_init *init; 772 773 pack_for_each_init(init, pack, p) { 774 u32 next = init->addr + init->count * init->pitch; 775 u32 addr = init->addr; 776 while (addr < next) { 777 nvkm_wr32(device, addr, init->data); 778 addr += init->pitch; 779 } 780 } 781 } 782 783 void 784 gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) 785 { 786 struct nvkm_device *device = gr->base.engine.subdev.device; 787 const struct gf100_gr_pack *pack; 788 const struct gf100_gr_init *init; 789 u32 data = 0; 790 791 nvkm_wr32(device, 0x400208, 0x80000000); 792 793 pack_for_each_init(init, pack, p) { 794 u32 next = init->addr + init->count * init->pitch; 795 u32 addr = init->addr; 796 797 if ((pack == p && init == p->init) || data != init->data) { 798 nvkm_wr32(device, 0x400204, init->data); 799 data = init->data; 800 } 801 802 while (addr < next) { 803 nvkm_wr32(device, 0x400200, addr); 804 /** 805 * Wait for GR to go idle after submitting a 806 * GO_IDLE bundle 807 */ 808 if ((addr & 0xffff) == 0xe100) 809 gf100_gr_wait_idle(gr); 810 nvkm_msec(device, 2000, 811 if (!(nvkm_rd32(device, 0x400700) & 0x00000004)) 812 break; 813 ); 814 addr += init->pitch; 815 } 816 } 817 818 nvkm_wr32(device, 0x400208, 0x00000000); 819 } 820 821 void 822 gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) 823 { 824 struct nvkm_device *device = gr->base.engine.subdev.device; 825 const struct gf100_gr_pack *pack; 826 const struct gf100_gr_init *init; 827 u32 data = 0; 828 829 pack_for_each_init(init, pack, p) { 830 u32 ctrl = 0x80000000 | pack->type; 831 u32 next = init->addr + init->count * init->pitch; 832 u32 addr = init->addr; 833 834 if ((pack == p && init == p->init) || data != init->data) { 835 nvkm_wr32(device, 0x40448c, init->data); 836 data = init->data; 837 } 838 839 while (addr < next) { 840 nvkm_wr32(device, 0x404488, ctrl | (addr << 14)); 841 addr += init->pitch; 842 } 843 } 844 } 845 846 u64 847 gf100_gr_units(struct nvkm_gr *base) 848 { 849 struct gf100_gr *gr = gf100_gr(base); 850 u64 cfg; 851 852 cfg = (u32)gr->gpc_nr; 853 cfg |= (u32)gr->tpc_total << 8; 854 cfg |= (u64)gr->rop_nr << 32; 855 856 return cfg; 857 } 858 859 static const struct nvkm_bitfield gf100_dispatch_error[] = { 860 { 0x00000001, "INJECTED_BUNDLE_ERROR" }, 861 { 0x00000002, "CLASS_SUBCH_MISMATCH" }, 862 { 0x00000004, "SUBCHSW_DURING_NOTIFY" }, 863 {} 864 }; 865 866 static const struct nvkm_bitfield gf100_m2mf_error[] = { 867 { 0x00000001, "PUSH_TOO_MUCH_DATA" }, 868 { 0x00000002, "PUSH_NOT_ENOUGH_DATA" }, 869 {} 870 }; 871 872 static const struct nvkm_bitfield gf100_unk6_error[] = { 873 { 0x00000001, "TEMP_TOO_SMALL" }, 874 {} 875 }; 876 877 static const struct nvkm_bitfield gf100_ccache_error[] = { 878 { 0x00000001, "INTR" }, 879 { 0x00000002, "LDCONST_OOB" }, 880 {} 881 }; 882 883 static const struct nvkm_bitfield gf100_macro_error[] = { 884 { 0x00000001, "TOO_FEW_PARAMS" }, 885 { 0x00000002, "TOO_MANY_PARAMS" }, 886 { 0x00000004, "ILLEGAL_OPCODE" }, 887 { 0x00000008, "DOUBLE_BRANCH" }, 888 { 0x00000010, "WATCHDOG" }, 889 {} 890 }; 891 892 static const struct nvkm_bitfield gk104_sked_error[] = { 893 { 0x00000040, "CTA_RESUME" }, 894 { 0x00000080, "CONSTANT_BUFFER_SIZE" }, 895 { 0x00000200, "LOCAL_MEMORY_SIZE_POS" }, 896 { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" }, 897 { 0x00000800, "WARP_CSTACK_SIZE" }, 898 { 0x00001000, "TOTAL_TEMP_SIZE" }, 899 { 0x00002000, "REGISTER_COUNT" }, 900 { 0x00040000, "TOTAL_THREADS" }, 901 { 0x00100000, "PROGRAM_OFFSET" }, 902 { 0x00200000, "SHARED_MEMORY_SIZE" }, 903 { 0x00800000, "CTA_THREAD_DIMENSION_ZERO" }, 904 { 0x01000000, "MEMORY_WINDOW_OVERLAP" }, 905 { 0x02000000, "SHARED_CONFIG_TOO_SMALL" }, 906 { 0x04000000, "TOTAL_REGISTER_COUNT" }, 907 {} 908 }; 909 910 static const struct nvkm_bitfield gf100_gpc_rop_error[] = { 911 { 0x00000002, "RT_PITCH_OVERRUN" }, 912 { 0x00000010, "RT_WIDTH_OVERRUN" }, 913 { 0x00000020, "RT_HEIGHT_OVERRUN" }, 914 { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" }, 915 { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" }, 916 { 0x00000400, "RT_LINEAR_MISMATCH" }, 917 {} 918 }; 919 920 static void 921 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) 922 { 923 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 924 struct nvkm_device *device = subdev->device; 925 char error[128]; 926 u32 trap[4]; 927 928 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; 929 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); 930 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); 931 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); 932 933 nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]); 934 935 nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, " 936 "format = %x, storage type = %x\n", 937 gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, 938 (trap[2] >> 8) & 0x3f, trap[3] & 0xff); 939 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); 940 } 941 942 static const struct nvkm_enum gf100_mp_warp_error[] = { 943 { 0x00, "NO_ERROR" }, 944 { 0x01, "STACK_MISMATCH" }, 945 { 0x05, "MISALIGNED_PC" }, 946 { 0x08, "MISALIGNED_GPR" }, 947 { 0x09, "INVALID_OPCODE" }, 948 { 0x0d, "GPR_OUT_OF_BOUNDS" }, 949 { 0x0e, "MEM_OUT_OF_BOUNDS" }, 950 { 0x0f, "UNALIGNED_MEM_ACCESS" }, 951 { 0x10, "INVALID_ADDR_SPACE" }, 952 { 0x11, "INVALID_PARAM" }, 953 {} 954 }; 955 956 static const struct nvkm_bitfield gf100_mp_global_error[] = { 957 { 0x00000004, "MULTIPLE_WARP_ERRORS" }, 958 { 0x00000008, "OUT_OF_STACK_SPACE" }, 959 {} 960 }; 961 962 static void 963 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) 964 { 965 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 966 struct nvkm_device *device = subdev->device; 967 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); 968 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); 969 const struct nvkm_enum *warp; 970 char glob[128]; 971 972 nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr); 973 warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff); 974 975 nvkm_error(subdev, "GPC%i/TPC%i/MP trap: " 976 "global %08x [%s] warp %04x [%s]\n", 977 gpc, tpc, gerr, glob, werr, warp ? warp->name : ""); 978 979 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); 980 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); 981 } 982 983 static void 984 gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) 985 { 986 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 987 struct nvkm_device *device = subdev->device; 988 u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); 989 990 if (stat & 0x00000001) { 991 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); 992 nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap); 993 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); 994 stat &= ~0x00000001; 995 } 996 997 if (stat & 0x00000002) { 998 gf100_gr_trap_mp(gr, gpc, tpc); 999 stat &= ~0x00000002; 1000 } 1001 1002 if (stat & 0x00000004) { 1003 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); 1004 nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap); 1005 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); 1006 stat &= ~0x00000004; 1007 } 1008 1009 if (stat & 0x00000008) { 1010 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); 1011 nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap); 1012 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); 1013 stat &= ~0x00000008; 1014 } 1015 1016 if (stat) { 1017 nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat); 1018 } 1019 } 1020 1021 static void 1022 gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) 1023 { 1024 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1025 struct nvkm_device *device = subdev->device; 1026 u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); 1027 int tpc; 1028 1029 if (stat & 0x00000001) { 1030 gf100_gr_trap_gpc_rop(gr, gpc); 1031 stat &= ~0x00000001; 1032 } 1033 1034 if (stat & 0x00000002) { 1035 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); 1036 nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap); 1037 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); 1038 stat &= ~0x00000002; 1039 } 1040 1041 if (stat & 0x00000004) { 1042 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); 1043 nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap); 1044 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); 1045 stat &= ~0x00000004; 1046 } 1047 1048 if (stat & 0x00000008) { 1049 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); 1050 nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap); 1051 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); 1052 stat &= ~0x00000009; 1053 } 1054 1055 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { 1056 u32 mask = 0x00010000 << tpc; 1057 if (stat & mask) { 1058 gf100_gr_trap_tpc(gr, gpc, tpc); 1059 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); 1060 stat &= ~mask; 1061 } 1062 } 1063 1064 if (stat) { 1065 nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat); 1066 } 1067 } 1068 1069 static void 1070 gf100_gr_trap_intr(struct gf100_gr *gr) 1071 { 1072 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1073 struct nvkm_device *device = subdev->device; 1074 char error[128]; 1075 u32 trap = nvkm_rd32(device, 0x400108); 1076 int rop, gpc; 1077 1078 if (trap & 0x00000001) { 1079 u32 stat = nvkm_rd32(device, 0x404000); 1080 1081 nvkm_snprintbf(error, sizeof(error), gf100_dispatch_error, 1082 stat & 0x3fffffff); 1083 nvkm_error(subdev, "DISPATCH %08x [%s]\n", stat, error); 1084 nvkm_wr32(device, 0x404000, 0xc0000000); 1085 nvkm_wr32(device, 0x400108, 0x00000001); 1086 trap &= ~0x00000001; 1087 } 1088 1089 if (trap & 0x00000002) { 1090 u32 stat = nvkm_rd32(device, 0x404600); 1091 1092 nvkm_snprintbf(error, sizeof(error), gf100_m2mf_error, 1093 stat & 0x3fffffff); 1094 nvkm_error(subdev, "M2MF %08x [%s]\n", stat, error); 1095 1096 nvkm_wr32(device, 0x404600, 0xc0000000); 1097 nvkm_wr32(device, 0x400108, 0x00000002); 1098 trap &= ~0x00000002; 1099 } 1100 1101 if (trap & 0x00000008) { 1102 u32 stat = nvkm_rd32(device, 0x408030); 1103 1104 nvkm_snprintbf(error, sizeof(error), gf100_m2mf_error, 1105 stat & 0x3fffffff); 1106 nvkm_error(subdev, "CCACHE %08x [%s]\n", stat, error); 1107 nvkm_wr32(device, 0x408030, 0xc0000000); 1108 nvkm_wr32(device, 0x400108, 0x00000008); 1109 trap &= ~0x00000008; 1110 } 1111 1112 if (trap & 0x00000010) { 1113 u32 stat = nvkm_rd32(device, 0x405840); 1114 nvkm_error(subdev, "SHADER %08x, sph: 0x%06x, stage: 0x%02x\n", 1115 stat, stat & 0xffffff, (stat >> 24) & 0x3f); 1116 nvkm_wr32(device, 0x405840, 0xc0000000); 1117 nvkm_wr32(device, 0x400108, 0x00000010); 1118 trap &= ~0x00000010; 1119 } 1120 1121 if (trap & 0x00000040) { 1122 u32 stat = nvkm_rd32(device, 0x40601c); 1123 1124 nvkm_snprintbf(error, sizeof(error), gf100_unk6_error, 1125 stat & 0x3fffffff); 1126 nvkm_error(subdev, "UNK6 %08x [%s]\n", stat, error); 1127 1128 nvkm_wr32(device, 0x40601c, 0xc0000000); 1129 nvkm_wr32(device, 0x400108, 0x00000040); 1130 trap &= ~0x00000040; 1131 } 1132 1133 if (trap & 0x00000080) { 1134 u32 stat = nvkm_rd32(device, 0x404490); 1135 u32 pc = nvkm_rd32(device, 0x404494); 1136 u32 op = nvkm_rd32(device, 0x40449c); 1137 1138 nvkm_snprintbf(error, sizeof(error), gf100_macro_error, 1139 stat & 0x1fffffff); 1140 nvkm_error(subdev, "MACRO %08x [%s], pc: 0x%03x%s, op: 0x%08x\n", 1141 stat, error, pc & 0x7ff, 1142 (pc & 0x10000000) ? "" : " (invalid)", 1143 op); 1144 1145 nvkm_wr32(device, 0x404490, 0xc0000000); 1146 nvkm_wr32(device, 0x400108, 0x00000080); 1147 trap &= ~0x00000080; 1148 } 1149 1150 if (trap & 0x00000100) { 1151 u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff; 1152 1153 nvkm_snprintbf(error, sizeof(error), gk104_sked_error, stat); 1154 nvkm_error(subdev, "SKED: %08x [%s]\n", stat, error); 1155 1156 if (stat) 1157 nvkm_wr32(device, 0x407020, 0x40000000); 1158 nvkm_wr32(device, 0x400108, 0x00000100); 1159 trap &= ~0x00000100; 1160 } 1161 1162 if (trap & 0x01000000) { 1163 u32 stat = nvkm_rd32(device, 0x400118); 1164 for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { 1165 u32 mask = 0x00000001 << gpc; 1166 if (stat & mask) { 1167 gf100_gr_trap_gpc(gr, gpc); 1168 nvkm_wr32(device, 0x400118, mask); 1169 stat &= ~mask; 1170 } 1171 } 1172 nvkm_wr32(device, 0x400108, 0x01000000); 1173 trap &= ~0x01000000; 1174 } 1175 1176 if (trap & 0x02000000) { 1177 for (rop = 0; rop < gr->rop_nr; rop++) { 1178 u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); 1179 u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); 1180 nvkm_error(subdev, "ROP%d %08x %08x\n", 1181 rop, statz, statc); 1182 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); 1183 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); 1184 } 1185 nvkm_wr32(device, 0x400108, 0x02000000); 1186 trap &= ~0x02000000; 1187 } 1188 1189 if (trap) { 1190 nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap); 1191 nvkm_wr32(device, 0x400108, trap); 1192 } 1193 } 1194 1195 static void 1196 gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) 1197 { 1198 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1199 struct nvkm_device *device = subdev->device; 1200 nvkm_error(subdev, "%06x - done %08x\n", base, 1201 nvkm_rd32(device, base + 0x400)); 1202 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, 1203 nvkm_rd32(device, base + 0x800), 1204 nvkm_rd32(device, base + 0x804), 1205 nvkm_rd32(device, base + 0x808), 1206 nvkm_rd32(device, base + 0x80c)); 1207 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, 1208 nvkm_rd32(device, base + 0x810), 1209 nvkm_rd32(device, base + 0x814), 1210 nvkm_rd32(device, base + 0x818), 1211 nvkm_rd32(device, base + 0x81c)); 1212 } 1213 1214 void 1215 gf100_gr_ctxctl_debug(struct gf100_gr *gr) 1216 { 1217 struct nvkm_device *device = gr->base.engine.subdev.device; 1218 u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff; 1219 u32 gpc; 1220 1221 gf100_gr_ctxctl_debug_unit(gr, 0x409000); 1222 for (gpc = 0; gpc < gpcnr; gpc++) 1223 gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000)); 1224 } 1225 1226 static void 1227 gf100_gr_ctxctl_isr(struct gf100_gr *gr) 1228 { 1229 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1230 struct nvkm_device *device = subdev->device; 1231 u32 stat = nvkm_rd32(device, 0x409c18); 1232 1233 if (stat & 0x00000001) { 1234 u32 code = nvkm_rd32(device, 0x409814); 1235 if (code == E_BAD_FWMTHD) { 1236 u32 class = nvkm_rd32(device, 0x409808); 1237 u32 addr = nvkm_rd32(device, 0x40980c); 1238 u32 subc = (addr & 0x00070000) >> 16; 1239 u32 mthd = (addr & 0x00003ffc); 1240 u32 data = nvkm_rd32(device, 0x409810); 1241 1242 nvkm_error(subdev, "FECS MTHD subc %d class %04x " 1243 "mthd %04x data %08x\n", 1244 subc, class, mthd, data); 1245 1246 nvkm_wr32(device, 0x409c20, 0x00000001); 1247 stat &= ~0x00000001; 1248 } else { 1249 nvkm_error(subdev, "FECS ucode error %d\n", code); 1250 } 1251 } 1252 1253 if (stat & 0x00080000) { 1254 nvkm_error(subdev, "FECS watchdog timeout\n"); 1255 gf100_gr_ctxctl_debug(gr); 1256 nvkm_wr32(device, 0x409c20, 0x00080000); 1257 stat &= ~0x00080000; 1258 } 1259 1260 if (stat) { 1261 nvkm_error(subdev, "FECS %08x\n", stat); 1262 gf100_gr_ctxctl_debug(gr); 1263 nvkm_wr32(device, 0x409c20, stat); 1264 } 1265 } 1266 1267 static void 1268 gf100_gr_intr(struct nvkm_gr *base) 1269 { 1270 struct gf100_gr *gr = gf100_gr(base); 1271 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1272 struct nvkm_device *device = subdev->device; 1273 struct nvkm_fifo_chan *chan; 1274 unsigned long flags; 1275 u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; 1276 u32 stat = nvkm_rd32(device, 0x400100); 1277 u32 addr = nvkm_rd32(device, 0x400704); 1278 u32 mthd = (addr & 0x00003ffc); 1279 u32 subc = (addr & 0x00070000) >> 16; 1280 u32 data = nvkm_rd32(device, 0x400708); 1281 u32 code = nvkm_rd32(device, 0x400110); 1282 u32 class; 1283 const char *name = "unknown"; 1284 int chid = -1; 1285 1286 chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags); 1287 if (chan) { 1288 name = chan->object.client->name; 1289 chid = chan->chid; 1290 } 1291 1292 if (device->card_type < NV_E0 || subc < 4) 1293 class = nvkm_rd32(device, 0x404200 + (subc * 4)); 1294 else 1295 class = 0x0000; 1296 1297 if (stat & 0x00000001) { 1298 /* 1299 * notifier interrupt, only needed for cyclestats 1300 * can be safely ignored 1301 */ 1302 nvkm_wr32(device, 0x400100, 0x00000001); 1303 stat &= ~0x00000001; 1304 } 1305 1306 if (stat & 0x00000010) { 1307 if (!gf100_gr_mthd_sw(device, class, mthd, data)) { 1308 nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] " 1309 "subc %d class %04x mthd %04x data %08x\n", 1310 chid, inst << 12, name, subc, 1311 class, mthd, data); 1312 } 1313 nvkm_wr32(device, 0x400100, 0x00000010); 1314 stat &= ~0x00000010; 1315 } 1316 1317 if (stat & 0x00000020) { 1318 nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] " 1319 "subc %d class %04x mthd %04x data %08x\n", 1320 chid, inst << 12, name, subc, class, mthd, data); 1321 nvkm_wr32(device, 0x400100, 0x00000020); 1322 stat &= ~0x00000020; 1323 } 1324 1325 if (stat & 0x00100000) { 1326 const struct nvkm_enum *en = 1327 nvkm_enum_find(nv50_data_error_names, code); 1328 nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] " 1329 "subc %d class %04x mthd %04x data %08x\n", 1330 code, en ? en->name : "", chid, inst << 12, 1331 name, subc, class, mthd, data); 1332 nvkm_wr32(device, 0x400100, 0x00100000); 1333 stat &= ~0x00100000; 1334 } 1335 1336 if (stat & 0x00200000) { 1337 nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n", 1338 chid, inst << 12, name); 1339 gf100_gr_trap_intr(gr); 1340 nvkm_wr32(device, 0x400100, 0x00200000); 1341 stat &= ~0x00200000; 1342 } 1343 1344 if (stat & 0x00080000) { 1345 gf100_gr_ctxctl_isr(gr); 1346 nvkm_wr32(device, 0x400100, 0x00080000); 1347 stat &= ~0x00080000; 1348 } 1349 1350 if (stat) { 1351 nvkm_error(subdev, "intr %08x\n", stat); 1352 nvkm_wr32(device, 0x400100, stat); 1353 } 1354 1355 nvkm_wr32(device, 0x400500, 0x00010001); 1356 nvkm_fifo_chan_put(device->fifo, flags, &chan); 1357 } 1358 1359 void 1360 gf100_gr_init_fw(struct gf100_gr *gr, u32 fuc_base, 1361 struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) 1362 { 1363 struct nvkm_device *device = gr->base.engine.subdev.device; 1364 int i; 1365 1366 nvkm_wr32(device, fuc_base + 0x01c0, 0x01000000); 1367 for (i = 0; i < data->size / 4; i++) 1368 nvkm_wr32(device, fuc_base + 0x01c4, data->data[i]); 1369 1370 nvkm_wr32(device, fuc_base + 0x0180, 0x01000000); 1371 for (i = 0; i < code->size / 4; i++) { 1372 if ((i & 0x3f) == 0) 1373 nvkm_wr32(device, fuc_base + 0x0188, i >> 6); 1374 nvkm_wr32(device, fuc_base + 0x0184, code->data[i]); 1375 } 1376 1377 /* code must be padded to 0x40 words */ 1378 for (; i & 0x3f; i++) 1379 nvkm_wr32(device, fuc_base + 0x0184, 0); 1380 } 1381 1382 static void 1383 gf100_gr_init_csdata(struct gf100_gr *gr, 1384 const struct gf100_gr_pack *pack, 1385 u32 falcon, u32 starstar, u32 base) 1386 { 1387 struct nvkm_device *device = gr->base.engine.subdev.device; 1388 const struct gf100_gr_pack *iter; 1389 const struct gf100_gr_init *init; 1390 u32 addr = ~0, prev = ~0, xfer = 0; 1391 u32 star, temp; 1392 1393 nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar); 1394 star = nvkm_rd32(device, falcon + 0x01c4); 1395 temp = nvkm_rd32(device, falcon + 0x01c4); 1396 if (temp > star) 1397 star = temp; 1398 nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star); 1399 1400 pack_for_each_init(init, iter, pack) { 1401 u32 head = init->addr - base; 1402 u32 tail = head + init->count * init->pitch; 1403 while (head < tail) { 1404 if (head != prev + 4 || xfer >= 32) { 1405 if (xfer) { 1406 u32 data = ((--xfer << 26) | addr); 1407 nvkm_wr32(device, falcon + 0x01c4, data); 1408 star += 4; 1409 } 1410 addr = head; 1411 xfer = 0; 1412 } 1413 prev = head; 1414 xfer = xfer + 1; 1415 head = head + init->pitch; 1416 } 1417 } 1418 1419 nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr); 1420 nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar); 1421 nvkm_wr32(device, falcon + 0x01c4, star + 4); 1422 } 1423 1424 int 1425 gf100_gr_init_ctxctl(struct gf100_gr *gr) 1426 { 1427 const struct gf100_grctx_func *grctx = gr->func->grctx; 1428 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1429 struct nvkm_device *device = subdev->device; 1430 int i; 1431 1432 if (gr->firmware) { 1433 /* load fuc microcode */ 1434 nvkm_mc_unk260(device->mc, 0); 1435 gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, &gr->fuc409d); 1436 gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, &gr->fuc41ad); 1437 nvkm_mc_unk260(device->mc, 1); 1438 1439 /* start both of them running */ 1440 nvkm_wr32(device, 0x409840, 0xffffffff); 1441 nvkm_wr32(device, 0x41a10c, 0x00000000); 1442 nvkm_wr32(device, 0x40910c, 0x00000000); 1443 nvkm_wr32(device, 0x41a100, 0x00000002); 1444 nvkm_wr32(device, 0x409100, 0x00000002); 1445 if (nvkm_msec(device, 2000, 1446 if (nvkm_rd32(device, 0x409800) & 0x00000001) 1447 break; 1448 ) < 0) 1449 return -EBUSY; 1450 1451 nvkm_wr32(device, 0x409840, 0xffffffff); 1452 nvkm_wr32(device, 0x409500, 0x7fffffff); 1453 nvkm_wr32(device, 0x409504, 0x00000021); 1454 1455 nvkm_wr32(device, 0x409840, 0xffffffff); 1456 nvkm_wr32(device, 0x409500, 0x00000000); 1457 nvkm_wr32(device, 0x409504, 0x00000010); 1458 if (nvkm_msec(device, 2000, 1459 if ((gr->size = nvkm_rd32(device, 0x409800))) 1460 break; 1461 ) < 0) 1462 return -EBUSY; 1463 1464 nvkm_wr32(device, 0x409840, 0xffffffff); 1465 nvkm_wr32(device, 0x409500, 0x00000000); 1466 nvkm_wr32(device, 0x409504, 0x00000016); 1467 if (nvkm_msec(device, 2000, 1468 if (nvkm_rd32(device, 0x409800)) 1469 break; 1470 ) < 0) 1471 return -EBUSY; 1472 1473 nvkm_wr32(device, 0x409840, 0xffffffff); 1474 nvkm_wr32(device, 0x409500, 0x00000000); 1475 nvkm_wr32(device, 0x409504, 0x00000025); 1476 if (nvkm_msec(device, 2000, 1477 if (nvkm_rd32(device, 0x409800)) 1478 break; 1479 ) < 0) 1480 return -EBUSY; 1481 1482 if (device->chipset >= 0xe0) { 1483 nvkm_wr32(device, 0x409800, 0x00000000); 1484 nvkm_wr32(device, 0x409500, 0x00000001); 1485 nvkm_wr32(device, 0x409504, 0x00000030); 1486 if (nvkm_msec(device, 2000, 1487 if (nvkm_rd32(device, 0x409800)) 1488 break; 1489 ) < 0) 1490 return -EBUSY; 1491 1492 nvkm_wr32(device, 0x409810, 0xb00095c8); 1493 nvkm_wr32(device, 0x409800, 0x00000000); 1494 nvkm_wr32(device, 0x409500, 0x00000001); 1495 nvkm_wr32(device, 0x409504, 0x00000031); 1496 if (nvkm_msec(device, 2000, 1497 if (nvkm_rd32(device, 0x409800)) 1498 break; 1499 ) < 0) 1500 return -EBUSY; 1501 1502 nvkm_wr32(device, 0x409810, 0x00080420); 1503 nvkm_wr32(device, 0x409800, 0x00000000); 1504 nvkm_wr32(device, 0x409500, 0x00000001); 1505 nvkm_wr32(device, 0x409504, 0x00000032); 1506 if (nvkm_msec(device, 2000, 1507 if (nvkm_rd32(device, 0x409800)) 1508 break; 1509 ) < 0) 1510 return -EBUSY; 1511 1512 nvkm_wr32(device, 0x409614, 0x00000070); 1513 nvkm_wr32(device, 0x409614, 0x00000770); 1514 nvkm_wr32(device, 0x40802c, 0x00000001); 1515 } 1516 1517 if (gr->data == NULL) { 1518 int ret = gf100_grctx_generate(gr); 1519 if (ret) { 1520 nvkm_error(subdev, "failed to construct context\n"); 1521 return ret; 1522 } 1523 } 1524 1525 return 0; 1526 } else 1527 if (!gr->func->fecs.ucode) { 1528 return -ENOSYS; 1529 } 1530 1531 /* load HUB microcode */ 1532 nvkm_mc_unk260(device->mc, 0); 1533 nvkm_wr32(device, 0x4091c0, 0x01000000); 1534 for (i = 0; i < gr->func->fecs.ucode->data.size / 4; i++) 1535 nvkm_wr32(device, 0x4091c4, gr->func->fecs.ucode->data.data[i]); 1536 1537 nvkm_wr32(device, 0x409180, 0x01000000); 1538 for (i = 0; i < gr->func->fecs.ucode->code.size / 4; i++) { 1539 if ((i & 0x3f) == 0) 1540 nvkm_wr32(device, 0x409188, i >> 6); 1541 nvkm_wr32(device, 0x409184, gr->func->fecs.ucode->code.data[i]); 1542 } 1543 1544 /* load GPC microcode */ 1545 nvkm_wr32(device, 0x41a1c0, 0x01000000); 1546 for (i = 0; i < gr->func->gpccs.ucode->data.size / 4; i++) 1547 nvkm_wr32(device, 0x41a1c4, gr->func->gpccs.ucode->data.data[i]); 1548 1549 nvkm_wr32(device, 0x41a180, 0x01000000); 1550 for (i = 0; i < gr->func->gpccs.ucode->code.size / 4; i++) { 1551 if ((i & 0x3f) == 0) 1552 nvkm_wr32(device, 0x41a188, i >> 6); 1553 nvkm_wr32(device, 0x41a184, gr->func->gpccs.ucode->code.data[i]); 1554 } 1555 nvkm_mc_unk260(device->mc, 1); 1556 1557 /* load register lists */ 1558 gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000); 1559 gf100_gr_init_csdata(gr, grctx->gpc, 0x41a000, 0x000, 0x418000); 1560 gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800); 1561 gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00); 1562 1563 /* start HUB ucode running, it'll init the GPCs */ 1564 nvkm_wr32(device, 0x40910c, 0x00000000); 1565 nvkm_wr32(device, 0x409100, 0x00000002); 1566 if (nvkm_msec(device, 2000, 1567 if (nvkm_rd32(device, 0x409800) & 0x80000000) 1568 break; 1569 ) < 0) { 1570 gf100_gr_ctxctl_debug(gr); 1571 return -EBUSY; 1572 } 1573 1574 gr->size = nvkm_rd32(device, 0x409804); 1575 if (gr->data == NULL) { 1576 int ret = gf100_grctx_generate(gr); 1577 if (ret) { 1578 nvkm_error(subdev, "failed to construct context\n"); 1579 return ret; 1580 } 1581 } 1582 1583 return 0; 1584 } 1585 1586 static int 1587 gf100_gr_oneinit(struct nvkm_gr *base) 1588 { 1589 struct gf100_gr *gr = gf100_gr(base); 1590 struct nvkm_device *device = gr->base.engine.subdev.device; 1591 int ret, i, j; 1592 1593 nvkm_pmu_pgob(device->pmu, false); 1594 1595 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, 1596 &gr->unk4188b4); 1597 if (ret) 1598 return ret; 1599 1600 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, 1601 &gr->unk4188b8); 1602 if (ret) 1603 return ret; 1604 1605 nvkm_kmap(gr->unk4188b4); 1606 for (i = 0; i < 0x1000; i += 4) 1607 nvkm_wo32(gr->unk4188b4, i, 0x00000010); 1608 nvkm_done(gr->unk4188b4); 1609 1610 nvkm_kmap(gr->unk4188b8); 1611 for (i = 0; i < 0x1000; i += 4) 1612 nvkm_wo32(gr->unk4188b8, i, 0x00000010); 1613 nvkm_done(gr->unk4188b8); 1614 1615 gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; 1616 gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; 1617 for (i = 0; i < gr->gpc_nr; i++) { 1618 gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); 1619 gr->tpc_total += gr->tpc_nr[i]; 1620 gr->ppc_nr[i] = gr->func->ppc_nr; 1621 for (j = 0; j < gr->ppc_nr[i]; j++) { 1622 u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); 1623 if (mask) 1624 gr->ppc_mask[i] |= (1 << j); 1625 gr->ppc_tpc_nr[i][j] = hweight8(mask); 1626 } 1627 } 1628 1629 /*XXX: these need figuring out... though it might not even matter */ 1630 switch (device->chipset) { 1631 case 0xc0: 1632 if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ 1633 gr->magic_not_rop_nr = 0x07; 1634 } else 1635 if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ 1636 gr->magic_not_rop_nr = 0x05; 1637 } else 1638 if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ 1639 gr->magic_not_rop_nr = 0x06; 1640 } 1641 break; 1642 case 0xc3: /* 450, 4/0/0/0, 2 */ 1643 gr->magic_not_rop_nr = 0x03; 1644 break; 1645 case 0xc4: /* 460, 3/4/0/0, 4 */ 1646 gr->magic_not_rop_nr = 0x01; 1647 break; 1648 case 0xc1: /* 2/0/0/0, 1 */ 1649 gr->magic_not_rop_nr = 0x01; 1650 break; 1651 case 0xc8: /* 4/4/3/4, 5 */ 1652 gr->magic_not_rop_nr = 0x06; 1653 break; 1654 case 0xce: /* 4/4/0/0, 4 */ 1655 gr->magic_not_rop_nr = 0x03; 1656 break; 1657 case 0xcf: /* 4/0/0/0, 3 */ 1658 gr->magic_not_rop_nr = 0x03; 1659 break; 1660 case 0xd7: 1661 case 0xd9: /* 1/0/0/0, 1 */ 1662 case 0xea: /* gk20a */ 1663 case 0x12b: /* gm20b */ 1664 gr->magic_not_rop_nr = 0x01; 1665 break; 1666 } 1667 1668 return 0; 1669 } 1670 1671 int 1672 gf100_gr_init_(struct nvkm_gr *base) 1673 { 1674 struct gf100_gr *gr = gf100_gr(base); 1675 nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); 1676 return gr->func->init(gr); 1677 } 1678 1679 void 1680 gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) 1681 { 1682 kfree(fuc->data); 1683 fuc->data = NULL; 1684 } 1685 1686 void * 1687 gf100_gr_dtor(struct nvkm_gr *base) 1688 { 1689 struct gf100_gr *gr = gf100_gr(base); 1690 1691 if (gr->func->dtor) 1692 gr->func->dtor(gr); 1693 kfree(gr->data); 1694 1695 gf100_gr_dtor_fw(&gr->fuc409c); 1696 gf100_gr_dtor_fw(&gr->fuc409d); 1697 gf100_gr_dtor_fw(&gr->fuc41ac); 1698 gf100_gr_dtor_fw(&gr->fuc41ad); 1699 1700 nvkm_memory_del(&gr->unk4188b8); 1701 nvkm_memory_del(&gr->unk4188b4); 1702 return gr; 1703 } 1704 1705 static const struct nvkm_gr_func 1706 gf100_gr_ = { 1707 .dtor = gf100_gr_dtor, 1708 .oneinit = gf100_gr_oneinit, 1709 .init = gf100_gr_init_, 1710 .intr = gf100_gr_intr, 1711 .units = gf100_gr_units, 1712 .chan_new = gf100_gr_chan_new, 1713 .object_get = gf100_gr_object_get, 1714 }; 1715 1716 int 1717 gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, 1718 struct gf100_gr_fuc *fuc) 1719 { 1720 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1721 struct nvkm_device *device = subdev->device; 1722 const struct firmware *fw; 1723 char f[64]; 1724 char cname[16]; 1725 int ret; 1726 int i; 1727 1728 /* Convert device name to lowercase */ 1729 strncpy(cname, device->chip->name, sizeof(cname)); 1730 cname[sizeof(cname) - 1] = '\0'; 1731 i = strlen(cname); 1732 while (i) { 1733 --i; 1734 cname[i] = tolower(cname[i]); 1735 } 1736 1737 snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); 1738 ret = request_firmware(&fw, f, device->dev); 1739 if (ret) { 1740 nvkm_error(subdev, "failed to load %s\n", fwname); 1741 return ret; 1742 } 1743 1744 fuc->size = fw->size; 1745 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); 1746 release_firmware(fw); 1747 return (fuc->data != NULL) ? 0 : -ENOMEM; 1748 } 1749 1750 int 1751 gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device, 1752 int index, struct gf100_gr *gr) 1753 { 1754 int ret; 1755 1756 gr->func = func; 1757 gr->firmware = nvkm_boolopt(device->cfgopt, "NvGrUseFW", 1758 func->fecs.ucode == NULL); 1759 1760 ret = nvkm_gr_ctor(&gf100_gr_, device, index, 0x08001000, 1761 gr->firmware || func->fecs.ucode != NULL, 1762 &gr->base); 1763 if (ret) 1764 return ret; 1765 1766 if (gr->firmware) { 1767 nvkm_info(&gr->base.engine.subdev, "using external firmware\n"); 1768 if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || 1769 gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || 1770 gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || 1771 gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) 1772 return -ENODEV; 1773 } 1774 1775 return 0; 1776 } 1777 1778 int 1779 gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device, 1780 int index, struct nvkm_gr **pgr) 1781 { 1782 struct gf100_gr *gr; 1783 if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) 1784 return -ENOMEM; 1785 *pgr = &gr->base; 1786 return gf100_gr_ctor(func, device, index, gr); 1787 } 1788 1789 int 1790 gf100_gr_init(struct gf100_gr *gr) 1791 { 1792 struct nvkm_device *device = gr->base.engine.subdev.device; 1793 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); 1794 u32 data[TPC_MAX / 8] = {}; 1795 u8 tpcnr[GPC_MAX]; 1796 int gpc, tpc, rop; 1797 int i; 1798 1799 nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); 1800 nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000); 1801 nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000); 1802 nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000); 1803 nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); 1804 nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); 1805 nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); 1806 nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); 1807 1808 gf100_gr_mmio(gr, gr->func->mmio); 1809 1810 memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); 1811 for (i = 0, gpc = -1; i < gr->tpc_total; i++) { 1812 do { 1813 gpc = (gpc + 1) % gr->gpc_nr; 1814 } while (!tpcnr[gpc]); 1815 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; 1816 1817 data[i / 8] |= tpc << ((i % 8) * 4); 1818 } 1819 1820 nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); 1821 nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); 1822 nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); 1823 nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); 1824 1825 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 1826 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), 1827 gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); 1828 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | 1829 gr->tpc_total); 1830 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); 1831 } 1832 1833 if (device->chipset != 0xd7) 1834 nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); 1835 else 1836 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); 1837 1838 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); 1839 1840 nvkm_wr32(device, 0x400500, 0x00010001); 1841 1842 nvkm_wr32(device, 0x400100, 0xffffffff); 1843 nvkm_wr32(device, 0x40013c, 0xffffffff); 1844 1845 nvkm_wr32(device, 0x409c24, 0x000f0000); 1846 nvkm_wr32(device, 0x404000, 0xc0000000); 1847 nvkm_wr32(device, 0x404600, 0xc0000000); 1848 nvkm_wr32(device, 0x408030, 0xc0000000); 1849 nvkm_wr32(device, 0x40601c, 0xc0000000); 1850 nvkm_wr32(device, 0x404490, 0xc0000000); 1851 nvkm_wr32(device, 0x406018, 0xc0000000); 1852 nvkm_wr32(device, 0x405840, 0xc0000000); 1853 nvkm_wr32(device, 0x405844, 0x00ffffff); 1854 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); 1855 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); 1856 1857 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 1858 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); 1859 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); 1860 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); 1861 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); 1862 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { 1863 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); 1864 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); 1865 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); 1866 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); 1867 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); 1868 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); 1869 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); 1870 } 1871 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); 1872 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); 1873 } 1874 1875 for (rop = 0; rop < gr->rop_nr; rop++) { 1876 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); 1877 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); 1878 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); 1879 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); 1880 } 1881 1882 nvkm_wr32(device, 0x400108, 0xffffffff); 1883 nvkm_wr32(device, 0x400138, 0xffffffff); 1884 nvkm_wr32(device, 0x400118, 0xffffffff); 1885 nvkm_wr32(device, 0x400130, 0xffffffff); 1886 nvkm_wr32(device, 0x40011c, 0xffffffff); 1887 nvkm_wr32(device, 0x400134, 0xffffffff); 1888 1889 nvkm_wr32(device, 0x400054, 0x34ce3464); 1890 1891 gf100_gr_zbc_init(gr); 1892 1893 return gf100_gr_init_ctxctl(gr); 1894 } 1895 1896 #include "fuc/hubgf100.fuc3.h" 1897 1898 struct gf100_gr_ucode 1899 gf100_gr_fecs_ucode = { 1900 .code.data = gf100_grhub_code, 1901 .code.size = sizeof(gf100_grhub_code), 1902 .data.data = gf100_grhub_data, 1903 .data.size = sizeof(gf100_grhub_data), 1904 }; 1905 1906 #include "fuc/gpcgf100.fuc3.h" 1907 1908 struct gf100_gr_ucode 1909 gf100_gr_gpccs_ucode = { 1910 .code.data = gf100_grgpc_code, 1911 .code.size = sizeof(gf100_grgpc_code), 1912 .data.data = gf100_grgpc_data, 1913 .data.size = sizeof(gf100_grgpc_data), 1914 }; 1915 1916 static const struct gf100_gr_func 1917 gf100_gr = { 1918 .init = gf100_gr_init, 1919 .mmio = gf100_gr_pack_mmio, 1920 .fecs.ucode = &gf100_gr_fecs_ucode, 1921 .gpccs.ucode = &gf100_gr_gpccs_ucode, 1922 .grctx = &gf100_grctx, 1923 .sclass = { 1924 { -1, -1, FERMI_TWOD_A }, 1925 { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A }, 1926 { -1, -1, FERMI_A, &gf100_fermi }, 1927 { -1, -1, FERMI_COMPUTE_A }, 1928 {} 1929 } 1930 }; 1931 1932 int 1933 gf100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) 1934 { 1935 return gf100_gr_new_(&gf100_gr, device, index, pgr); 1936 } 1937