1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "gf100.h" 25 #include "ctxgf100.h" 26 #include "fuc/os.h" 27 28 #include <core/client.h> 29 #include <core/option.h> 30 #include <subdev/fb.h> 31 #include <subdev/mc.h> 32 #include <subdev/timer.h> 33 #include <engine/fifo.h> 34 35 #include <nvif/class.h> 36 #include <nvif/unpack.h> 37 38 /******************************************************************************* 39 * Zero Bandwidth Clear 40 ******************************************************************************/ 41 42 static void 43 gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) 44 { 45 struct nvkm_device *device = gr->base.engine.subdev.device; 46 if (gr->zbc_color[zbc].format) { 47 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); 48 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); 49 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); 50 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); 51 } 52 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); 53 nvkm_wr32(device, 0x405820, zbc); 54 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ 55 } 56 57 static int 58 gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, 59 const u32 ds[4], const u32 l2[4]) 60 { 61 struct nvkm_ltc *ltc = nvkm_ltc(gr); 62 int zbc = -ENOSPC, i; 63 64 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { 65 if (gr->zbc_color[i].format) { 66 if (gr->zbc_color[i].format != format) 67 continue; 68 if (memcmp(gr->zbc_color[i].ds, ds, sizeof( 69 gr->zbc_color[i].ds))) 70 continue; 71 if (memcmp(gr->zbc_color[i].l2, l2, sizeof( 72 gr->zbc_color[i].l2))) { 73 WARN_ON(1); 74 return -EINVAL; 75 } 76 return i; 77 } else { 78 zbc = (zbc < 0) ? i : zbc; 79 } 80 } 81 82 if (zbc < 0) 83 return zbc; 84 85 memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); 86 memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); 87 gr->zbc_color[zbc].format = format; 88 ltc->zbc_color_get(ltc, zbc, l2); 89 gf100_gr_zbc_clear_color(gr, zbc); 90 return zbc; 91 } 92 93 static void 94 gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) 95 { 96 struct nvkm_device *device = gr->base.engine.subdev.device; 97 if (gr->zbc_depth[zbc].format) 98 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); 99 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); 100 nvkm_wr32(device, 0x405820, zbc); 101 nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ 102 } 103 104 static int 105 gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, 106 const u32 ds, const u32 l2) 107 { 108 struct nvkm_ltc *ltc = nvkm_ltc(gr); 109 int zbc = -ENOSPC, i; 110 111 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { 112 if (gr->zbc_depth[i].format) { 113 if (gr->zbc_depth[i].format != format) 114 continue; 115 if (gr->zbc_depth[i].ds != ds) 116 continue; 117 if (gr->zbc_depth[i].l2 != l2) { 118 WARN_ON(1); 119 return -EINVAL; 120 } 121 return i; 122 } else { 123 zbc = (zbc < 0) ? i : zbc; 124 } 125 } 126 127 if (zbc < 0) 128 return zbc; 129 130 gr->zbc_depth[zbc].format = format; 131 gr->zbc_depth[zbc].ds = ds; 132 gr->zbc_depth[zbc].l2 = l2; 133 ltc->zbc_depth_get(ltc, zbc, l2); 134 gf100_gr_zbc_clear_depth(gr, zbc); 135 return zbc; 136 } 137 138 /******************************************************************************* 139 * Graphics object classes 140 ******************************************************************************/ 141 142 static int 143 gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) 144 { 145 struct gf100_gr *gr = (void *)object->engine; 146 union { 147 struct fermi_a_zbc_color_v0 v0; 148 } *args = data; 149 int ret; 150 151 if (nvif_unpack(args->v0, 0, 0, false)) { 152 switch (args->v0.format) { 153 case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: 154 case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: 155 case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32: 156 case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16: 157 case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16: 158 case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16: 159 case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16: 160 case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16: 161 case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8: 162 case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8: 163 case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10: 164 case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10: 165 case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8: 166 case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8: 167 case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8: 168 case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8: 169 case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: 170 case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: 171 case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: 172 ret = gf100_gr_zbc_color_get(gr, args->v0.format, 173 args->v0.ds, 174 args->v0.l2); 175 if (ret >= 0) { 176 args->v0.index = ret; 177 return 0; 178 } 179 break; 180 default: 181 return -EINVAL; 182 } 183 } 184 185 return ret; 186 } 187 188 static int 189 gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) 190 { 191 struct gf100_gr *gr = (void *)object->engine; 192 union { 193 struct fermi_a_zbc_depth_v0 v0; 194 } *args = data; 195 int ret; 196 197 if (nvif_unpack(args->v0, 0, 0, false)) { 198 switch (args->v0.format) { 199 case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: 200 ret = gf100_gr_zbc_depth_get(gr, args->v0.format, 201 args->v0.ds, 202 args->v0.l2); 203 return (ret >= 0) ? 0 : -ENOSPC; 204 default: 205 return -EINVAL; 206 } 207 } 208 209 return ret; 210 } 211 212 static int 213 gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) 214 { 215 switch (mthd) { 216 case FERMI_A_ZBC_COLOR: 217 return gf100_fermi_mthd_zbc_color(object, data, size); 218 case FERMI_A_ZBC_DEPTH: 219 return gf100_fermi_mthd_zbc_depth(object, data, size); 220 default: 221 break; 222 } 223 return -EINVAL; 224 } 225 226 const struct nvkm_object_func 227 gf100_fermi = { 228 .mthd = gf100_fermi_mthd, 229 }; 230 231 static void 232 gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data) 233 { 234 nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000); 235 nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000); 236 } 237 238 static bool 239 gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data) 240 { 241 switch (class & 0x00ff) { 242 case 0x97: 243 case 0xc0: 244 switch (mthd) { 245 case 0x1528: 246 gf100_gr_mthd_set_shader_exceptions(device, data); 247 return true; 248 default: 249 break; 250 } 251 break; 252 default: 253 break; 254 } 255 return false; 256 } 257 258 static int 259 gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass) 260 { 261 struct gf100_gr *gr = gf100_gr(base); 262 int c = 0; 263 264 while (gr->func->sclass[c].oclass) { 265 if (c++ == index) { 266 *sclass = gr->func->sclass[index]; 267 return index; 268 } 269 } 270 271 return c; 272 } 273 274 /******************************************************************************* 275 * PGRAPH context 276 ******************************************************************************/ 277 278 static int 279 gf100_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, 280 int align, struct nvkm_gpuobj **pgpuobj) 281 { 282 struct gf100_gr_chan *chan = gf100_gr_chan(object); 283 struct gf100_gr *gr = chan->gr; 284 int ret, i; 285 286 ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, 287 align, false, parent, pgpuobj); 288 if (ret) 289 return ret; 290 291 nvkm_kmap(*pgpuobj); 292 for (i = 0; i < gr->size; i += 4) 293 nvkm_wo32(*pgpuobj, i, gr->data[i / 4]); 294 295 if (!gr->firmware) { 296 nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2); 297 nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma.offset >> 8); 298 } else { 299 nvkm_wo32(*pgpuobj, 0xf4, 0); 300 nvkm_wo32(*pgpuobj, 0xf8, 0); 301 nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2); 302 nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma.offset)); 303 nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma.offset)); 304 nvkm_wo32(*pgpuobj, 0x1c, 1); 305 nvkm_wo32(*pgpuobj, 0x20, 0); 306 nvkm_wo32(*pgpuobj, 0x28, 0); 307 nvkm_wo32(*pgpuobj, 0x2c, 0); 308 } 309 nvkm_done(*pgpuobj); 310 return 0; 311 } 312 313 static void * 314 gf100_gr_chan_dtor(struct nvkm_object *object) 315 { 316 struct gf100_gr_chan *chan = gf100_gr_chan(object); 317 int i; 318 319 for (i = 0; i < ARRAY_SIZE(chan->data); i++) { 320 if (chan->data[i].vma.node) { 321 nvkm_vm_unmap(&chan->data[i].vma); 322 nvkm_vm_put(&chan->data[i].vma); 323 } 324 nvkm_memory_del(&chan->data[i].mem); 325 } 326 327 if (chan->mmio_vma.node) { 328 nvkm_vm_unmap(&chan->mmio_vma); 329 nvkm_vm_put(&chan->mmio_vma); 330 } 331 nvkm_memory_del(&chan->mmio); 332 return chan; 333 } 334 335 static const struct nvkm_object_func 336 gf100_gr_chan = { 337 .dtor = gf100_gr_chan_dtor, 338 .bind = gf100_gr_chan_bind, 339 }; 340 341 static int 342 gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, 343 const struct nvkm_oclass *oclass, 344 struct nvkm_object **pobject) 345 { 346 struct gf100_gr *gr = gf100_gr(base); 347 struct gf100_gr_data *data = gr->mmio_data; 348 struct gf100_gr_mmio *mmio = gr->mmio_list; 349 struct gf100_gr_chan *chan; 350 struct nvkm_device *device = gr->base.engine.subdev.device; 351 int ret, i; 352 353 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) 354 return -ENOMEM; 355 nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object); 356 chan->gr = gr; 357 *pobject = &chan->object; 358 359 /* allocate memory for a "mmio list" buffer that's used by the HUB 360 * fuc to modify some per-context register settings on first load 361 * of the context. 362 */ 363 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100, 364 false, &chan->mmio); 365 if (ret) 366 return ret; 367 368 ret = nvkm_vm_get(fifoch->vm, 0x1000, 12, NV_MEM_ACCESS_RW | 369 NV_MEM_ACCESS_SYS, &chan->mmio_vma); 370 if (ret) 371 return ret; 372 373 nvkm_memory_map(chan->mmio, &chan->mmio_vma, 0); 374 375 /* allocate buffers referenced by mmio list */ 376 for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) { 377 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 378 data->size, data->align, false, 379 &chan->data[i].mem); 380 if (ret) 381 return ret; 382 383 ret = nvkm_vm_get(fifoch->vm, 384 nvkm_memory_size(chan->data[i].mem), 12, 385 data->access, &chan->data[i].vma); 386 if (ret) 387 return ret; 388 389 nvkm_memory_map(chan->data[i].mem, &chan->data[i].vma, 0); 390 data++; 391 } 392 393 /* finally, fill in the mmio list and point the context at it */ 394 nvkm_kmap(chan->mmio); 395 for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) { 396 u32 addr = mmio->addr; 397 u32 data = mmio->data; 398 399 if (mmio->buffer >= 0) { 400 u64 info = chan->data[mmio->buffer].vma.offset; 401 data |= info >> mmio->shift; 402 } 403 404 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); 405 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data); 406 mmio++; 407 } 408 nvkm_done(chan->mmio); 409 return 0; 410 } 411 412 /******************************************************************************* 413 * PGRAPH register lists 414 ******************************************************************************/ 415 416 const struct gf100_gr_init 417 gf100_gr_init_main_0[] = { 418 { 0x400080, 1, 0x04, 0x003083c2 }, 419 { 0x400088, 1, 0x04, 0x00006fe7 }, 420 { 0x40008c, 1, 0x04, 0x00000000 }, 421 { 0x400090, 1, 0x04, 0x00000030 }, 422 { 0x40013c, 1, 0x04, 0x013901f7 }, 423 { 0x400140, 1, 0x04, 0x00000100 }, 424 { 0x400144, 1, 0x04, 0x00000000 }, 425 { 0x400148, 1, 0x04, 0x00000110 }, 426 { 0x400138, 1, 0x04, 0x00000000 }, 427 { 0x400130, 2, 0x04, 0x00000000 }, 428 { 0x400124, 1, 0x04, 0x00000002 }, 429 {} 430 }; 431 432 const struct gf100_gr_init 433 gf100_gr_init_fe_0[] = { 434 { 0x40415c, 1, 0x04, 0x00000000 }, 435 { 0x404170, 1, 0x04, 0x00000000 }, 436 {} 437 }; 438 439 const struct gf100_gr_init 440 gf100_gr_init_pri_0[] = { 441 { 0x404488, 2, 0x04, 0x00000000 }, 442 {} 443 }; 444 445 const struct gf100_gr_init 446 gf100_gr_init_rstr2d_0[] = { 447 { 0x407808, 1, 0x04, 0x00000000 }, 448 {} 449 }; 450 451 const struct gf100_gr_init 452 gf100_gr_init_pd_0[] = { 453 { 0x406024, 1, 0x04, 0x00000000 }, 454 {} 455 }; 456 457 const struct gf100_gr_init 458 gf100_gr_init_ds_0[] = { 459 { 0x405844, 1, 0x04, 0x00ffffff }, 460 { 0x405850, 1, 0x04, 0x00000000 }, 461 { 0x405908, 1, 0x04, 0x00000000 }, 462 {} 463 }; 464 465 const struct gf100_gr_init 466 gf100_gr_init_scc_0[] = { 467 { 0x40803c, 1, 0x04, 0x00000000 }, 468 {} 469 }; 470 471 const struct gf100_gr_init 472 gf100_gr_init_prop_0[] = { 473 { 0x4184a0, 1, 0x04, 0x00000000 }, 474 {} 475 }; 476 477 const struct gf100_gr_init 478 gf100_gr_init_gpc_unk_0[] = { 479 { 0x418604, 1, 0x04, 0x00000000 }, 480 { 0x418680, 1, 0x04, 0x00000000 }, 481 { 0x418714, 1, 0x04, 0x80000000 }, 482 { 0x418384, 1, 0x04, 0x00000000 }, 483 {} 484 }; 485 486 const struct gf100_gr_init 487 gf100_gr_init_setup_0[] = { 488 { 0x418814, 3, 0x04, 0x00000000 }, 489 {} 490 }; 491 492 const struct gf100_gr_init 493 gf100_gr_init_crstr_0[] = { 494 { 0x418b04, 1, 0x04, 0x00000000 }, 495 {} 496 }; 497 498 const struct gf100_gr_init 499 gf100_gr_init_setup_1[] = { 500 { 0x4188c8, 1, 0x04, 0x80000000 }, 501 { 0x4188cc, 1, 0x04, 0x00000000 }, 502 { 0x4188d0, 1, 0x04, 0x00010000 }, 503 { 0x4188d4, 1, 0x04, 0x00000001 }, 504 {} 505 }; 506 507 const struct gf100_gr_init 508 gf100_gr_init_zcull_0[] = { 509 { 0x418910, 1, 0x04, 0x00010001 }, 510 { 0x418914, 1, 0x04, 0x00000301 }, 511 { 0x418918, 1, 0x04, 0x00800000 }, 512 { 0x418980, 1, 0x04, 0x77777770 }, 513 { 0x418984, 3, 0x04, 0x77777777 }, 514 {} 515 }; 516 517 const struct gf100_gr_init 518 gf100_gr_init_gpm_0[] = { 519 { 0x418c04, 1, 0x04, 0x00000000 }, 520 { 0x418c88, 1, 0x04, 0x00000000 }, 521 {} 522 }; 523 524 const struct gf100_gr_init 525 gf100_gr_init_gpc_unk_1[] = { 526 { 0x418d00, 1, 0x04, 0x00000000 }, 527 { 0x418f08, 1, 0x04, 0x00000000 }, 528 { 0x418e00, 1, 0x04, 0x00000050 }, 529 { 0x418e08, 1, 0x04, 0x00000000 }, 530 {} 531 }; 532 533 const struct gf100_gr_init 534 gf100_gr_init_gcc_0[] = { 535 { 0x41900c, 1, 0x04, 0x00000000 }, 536 { 0x419018, 1, 0x04, 0x00000000 }, 537 {} 538 }; 539 540 const struct gf100_gr_init 541 gf100_gr_init_tpccs_0[] = { 542 { 0x419d08, 2, 0x04, 0x00000000 }, 543 { 0x419d10, 1, 0x04, 0x00000014 }, 544 {} 545 }; 546 547 const struct gf100_gr_init 548 gf100_gr_init_tex_0[] = { 549 { 0x419ab0, 1, 0x04, 0x00000000 }, 550 { 0x419ab8, 1, 0x04, 0x000000e7 }, 551 { 0x419abc, 2, 0x04, 0x00000000 }, 552 {} 553 }; 554 555 const struct gf100_gr_init 556 gf100_gr_init_pe_0[] = { 557 { 0x41980c, 3, 0x04, 0x00000000 }, 558 { 0x419844, 1, 0x04, 0x00000000 }, 559 { 0x41984c, 1, 0x04, 0x00005bc5 }, 560 { 0x419850, 4, 0x04, 0x00000000 }, 561 {} 562 }; 563 564 const struct gf100_gr_init 565 gf100_gr_init_l1c_0[] = { 566 { 0x419c98, 1, 0x04, 0x00000000 }, 567 { 0x419ca8, 1, 0x04, 0x80000000 }, 568 { 0x419cb4, 1, 0x04, 0x00000000 }, 569 { 0x419cb8, 1, 0x04, 0x00008bf4 }, 570 { 0x419cbc, 1, 0x04, 0x28137606 }, 571 { 0x419cc0, 2, 0x04, 0x00000000 }, 572 {} 573 }; 574 575 const struct gf100_gr_init 576 gf100_gr_init_wwdx_0[] = { 577 { 0x419bd4, 1, 0x04, 0x00800000 }, 578 { 0x419bdc, 1, 0x04, 0x00000000 }, 579 {} 580 }; 581 582 const struct gf100_gr_init 583 gf100_gr_init_tpccs_1[] = { 584 { 0x419d2c, 1, 0x04, 0x00000000 }, 585 {} 586 }; 587 588 const struct gf100_gr_init 589 gf100_gr_init_mpc_0[] = { 590 { 0x419c0c, 1, 0x04, 0x00000000 }, 591 {} 592 }; 593 594 static const struct gf100_gr_init 595 gf100_gr_init_sm_0[] = { 596 { 0x419e00, 1, 0x04, 0x00000000 }, 597 { 0x419ea0, 1, 0x04, 0x00000000 }, 598 { 0x419ea4, 1, 0x04, 0x00000100 }, 599 { 0x419ea8, 1, 0x04, 0x00001100 }, 600 { 0x419eac, 1, 0x04, 0x11100702 }, 601 { 0x419eb0, 1, 0x04, 0x00000003 }, 602 { 0x419eb4, 4, 0x04, 0x00000000 }, 603 { 0x419ec8, 1, 0x04, 0x06060618 }, 604 { 0x419ed0, 1, 0x04, 0x0eff0e38 }, 605 { 0x419ed4, 1, 0x04, 0x011104f1 }, 606 { 0x419edc, 1, 0x04, 0x00000000 }, 607 { 0x419f00, 1, 0x04, 0x00000000 }, 608 { 0x419f2c, 1, 0x04, 0x00000000 }, 609 {} 610 }; 611 612 const struct gf100_gr_init 613 gf100_gr_init_be_0[] = { 614 { 0x40880c, 1, 0x04, 0x00000000 }, 615 { 0x408910, 9, 0x04, 0x00000000 }, 616 { 0x408950, 1, 0x04, 0x00000000 }, 617 { 0x408954, 1, 0x04, 0x0000ffff }, 618 { 0x408984, 1, 0x04, 0x00000000 }, 619 { 0x408988, 1, 0x04, 0x08040201 }, 620 { 0x40898c, 1, 0x04, 0x80402010 }, 621 {} 622 }; 623 624 const struct gf100_gr_init 625 gf100_gr_init_fe_1[] = { 626 { 0x4040f0, 1, 0x04, 0x00000000 }, 627 {} 628 }; 629 630 const struct gf100_gr_init 631 gf100_gr_init_pe_1[] = { 632 { 0x419880, 1, 0x04, 0x00000002 }, 633 {} 634 }; 635 636 static const struct gf100_gr_pack 637 gf100_gr_pack_mmio[] = { 638 { gf100_gr_init_main_0 }, 639 { gf100_gr_init_fe_0 }, 640 { gf100_gr_init_pri_0 }, 641 { gf100_gr_init_rstr2d_0 }, 642 { gf100_gr_init_pd_0 }, 643 { gf100_gr_init_ds_0 }, 644 { gf100_gr_init_scc_0 }, 645 { gf100_gr_init_prop_0 }, 646 { gf100_gr_init_gpc_unk_0 }, 647 { gf100_gr_init_setup_0 }, 648 { gf100_gr_init_crstr_0 }, 649 { gf100_gr_init_setup_1 }, 650 { gf100_gr_init_zcull_0 }, 651 { gf100_gr_init_gpm_0 }, 652 { gf100_gr_init_gpc_unk_1 }, 653 { gf100_gr_init_gcc_0 }, 654 { gf100_gr_init_tpccs_0 }, 655 { gf100_gr_init_tex_0 }, 656 { gf100_gr_init_pe_0 }, 657 { gf100_gr_init_l1c_0 }, 658 { gf100_gr_init_wwdx_0 }, 659 { gf100_gr_init_tpccs_1 }, 660 { gf100_gr_init_mpc_0 }, 661 { gf100_gr_init_sm_0 }, 662 { gf100_gr_init_be_0 }, 663 { gf100_gr_init_fe_1 }, 664 { gf100_gr_init_pe_1 }, 665 {} 666 }; 667 668 /******************************************************************************* 669 * PGRAPH engine/subdev functions 670 ******************************************************************************/ 671 672 void 673 gf100_gr_zbc_init(struct gf100_gr *gr) 674 { 675 const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 676 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 677 const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 678 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; 679 const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 680 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 681 const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 682 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; 683 struct nvkm_ltc *ltc = nvkm_ltc(gr); 684 int index; 685 686 if (!gr->zbc_color[0].format) { 687 gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); 688 gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); 689 gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); 690 gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); 691 gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); 692 gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); 693 } 694 695 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) 696 gf100_gr_zbc_clear_color(gr, index); 697 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) 698 gf100_gr_zbc_clear_depth(gr, index); 699 } 700 701 /** 702 * Wait until GR goes idle. GR is considered idle if it is disabled by the 703 * MC (0x200) register, or GR is not busy and a context switch is not in 704 * progress. 705 */ 706 int 707 gf100_gr_wait_idle(struct gf100_gr *gr) 708 { 709 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 710 struct nvkm_device *device = subdev->device; 711 unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000); 712 bool gr_enabled, ctxsw_active, gr_busy; 713 714 do { 715 /* 716 * required to make sure FIFO_ENGINE_STATUS (0x2640) is 717 * up-to-date 718 */ 719 nvkm_rd32(device, 0x400700); 720 721 gr_enabled = nvkm_rd32(device, 0x200) & 0x1000; 722 ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000; 723 gr_busy = nvkm_rd32(device, 0x40060c) & 0x1; 724 725 if (!gr_enabled || (!gr_busy && !ctxsw_active)) 726 return 0; 727 } while (time_before(jiffies, end_jiffies)); 728 729 nvkm_error(subdev, 730 "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n", 731 gr_enabled, ctxsw_active, gr_busy); 732 return -EAGAIN; 733 } 734 735 void 736 gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) 737 { 738 struct nvkm_device *device = gr->base.engine.subdev.device; 739 const struct gf100_gr_pack *pack; 740 const struct gf100_gr_init *init; 741 742 pack_for_each_init(init, pack, p) { 743 u32 next = init->addr + init->count * init->pitch; 744 u32 addr = init->addr; 745 while (addr < next) { 746 nvkm_wr32(device, addr, init->data); 747 addr += init->pitch; 748 } 749 } 750 } 751 752 void 753 gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) 754 { 755 struct nvkm_device *device = gr->base.engine.subdev.device; 756 const struct gf100_gr_pack *pack; 757 const struct gf100_gr_init *init; 758 u32 data = 0; 759 760 nvkm_wr32(device, 0x400208, 0x80000000); 761 762 pack_for_each_init(init, pack, p) { 763 u32 next = init->addr + init->count * init->pitch; 764 u32 addr = init->addr; 765 766 if ((pack == p && init == p->init) || data != init->data) { 767 nvkm_wr32(device, 0x400204, init->data); 768 data = init->data; 769 } 770 771 while (addr < next) { 772 nvkm_wr32(device, 0x400200, addr); 773 /** 774 * Wait for GR to go idle after submitting a 775 * GO_IDLE bundle 776 */ 777 if ((addr & 0xffff) == 0xe100) 778 gf100_gr_wait_idle(gr); 779 nvkm_msec(device, 2000, 780 if (!(nvkm_rd32(device, 0x400700) & 0x00000004)) 781 break; 782 ); 783 addr += init->pitch; 784 } 785 } 786 787 nvkm_wr32(device, 0x400208, 0x00000000); 788 } 789 790 void 791 gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) 792 { 793 struct nvkm_device *device = gr->base.engine.subdev.device; 794 const struct gf100_gr_pack *pack; 795 const struct gf100_gr_init *init; 796 u32 data = 0; 797 798 pack_for_each_init(init, pack, p) { 799 u32 ctrl = 0x80000000 | pack->type; 800 u32 next = init->addr + init->count * init->pitch; 801 u32 addr = init->addr; 802 803 if ((pack == p && init == p->init) || data != init->data) { 804 nvkm_wr32(device, 0x40448c, init->data); 805 data = init->data; 806 } 807 808 while (addr < next) { 809 nvkm_wr32(device, 0x404488, ctrl | (addr << 14)); 810 addr += init->pitch; 811 } 812 } 813 } 814 815 u64 816 gf100_gr_units(struct nvkm_gr *obj) 817 { 818 struct gf100_gr *gr = container_of(obj, typeof(*gr), base); 819 u64 cfg; 820 821 cfg = (u32)gr->gpc_nr; 822 cfg |= (u32)gr->tpc_total << 8; 823 cfg |= (u64)gr->rop_nr << 32; 824 825 return cfg; 826 } 827 828 static const struct nvkm_bitfield gk104_sked_error[] = { 829 { 0x00000080, "CONSTANT_BUFFER_SIZE" }, 830 { 0x00000200, "LOCAL_MEMORY_SIZE_POS" }, 831 { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" }, 832 { 0x00000800, "WARP_CSTACK_SIZE" }, 833 { 0x00001000, "TOTAL_TEMP_SIZE" }, 834 { 0x00002000, "REGISTER_COUNT" }, 835 { 0x00040000, "TOTAL_THREADS" }, 836 { 0x00100000, "PROGRAM_OFFSET" }, 837 { 0x00200000, "SHARED_MEMORY_SIZE" }, 838 { 0x02000000, "SHARED_CONFIG_TOO_SMALL" }, 839 { 0x04000000, "TOTAL_REGISTER_COUNT" }, 840 {} 841 }; 842 843 static const struct nvkm_bitfield gf100_gpc_rop_error[] = { 844 { 0x00000002, "RT_PITCH_OVERRUN" }, 845 { 0x00000010, "RT_WIDTH_OVERRUN" }, 846 { 0x00000020, "RT_HEIGHT_OVERRUN" }, 847 { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" }, 848 { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" }, 849 { 0x00000400, "RT_LINEAR_MISMATCH" }, 850 {} 851 }; 852 853 static void 854 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) 855 { 856 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 857 struct nvkm_device *device = subdev->device; 858 char error[128]; 859 u32 trap[4]; 860 861 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; 862 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); 863 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); 864 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); 865 866 nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]); 867 868 nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, " 869 "format = %x, storage type = %x\n", 870 gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, 871 (trap[2] >> 8) & 0x3f, trap[3] & 0xff); 872 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); 873 } 874 875 static const struct nvkm_enum gf100_mp_warp_error[] = { 876 { 0x00, "NO_ERROR" }, 877 { 0x01, "STACK_MISMATCH" }, 878 { 0x05, "MISALIGNED_PC" }, 879 { 0x08, "MISALIGNED_GPR" }, 880 { 0x09, "INVALID_OPCODE" }, 881 { 0x0d, "GPR_OUT_OF_BOUNDS" }, 882 { 0x0e, "MEM_OUT_OF_BOUNDS" }, 883 { 0x0f, "UNALIGNED_MEM_ACCESS" }, 884 { 0x11, "INVALID_PARAM" }, 885 {} 886 }; 887 888 static const struct nvkm_bitfield gf100_mp_global_error[] = { 889 { 0x00000004, "MULTIPLE_WARP_ERRORS" }, 890 { 0x00000008, "OUT_OF_STACK_SPACE" }, 891 {} 892 }; 893 894 static void 895 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) 896 { 897 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 898 struct nvkm_device *device = subdev->device; 899 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); 900 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); 901 const struct nvkm_enum *warp; 902 char glob[128]; 903 904 nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr); 905 warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff); 906 907 nvkm_error(subdev, "GPC%i/TPC%i/MP trap: " 908 "global %08x [%s] warp %04x [%s]\n", 909 gpc, tpc, gerr, glob, werr, warp ? warp->name : ""); 910 911 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); 912 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); 913 } 914 915 static void 916 gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) 917 { 918 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 919 struct nvkm_device *device = subdev->device; 920 u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); 921 922 if (stat & 0x00000001) { 923 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); 924 nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap); 925 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); 926 stat &= ~0x00000001; 927 } 928 929 if (stat & 0x00000002) { 930 gf100_gr_trap_mp(gr, gpc, tpc); 931 stat &= ~0x00000002; 932 } 933 934 if (stat & 0x00000004) { 935 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); 936 nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap); 937 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); 938 stat &= ~0x00000004; 939 } 940 941 if (stat & 0x00000008) { 942 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); 943 nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap); 944 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); 945 stat &= ~0x00000008; 946 } 947 948 if (stat) { 949 nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat); 950 } 951 } 952 953 static void 954 gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) 955 { 956 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 957 struct nvkm_device *device = subdev->device; 958 u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); 959 int tpc; 960 961 if (stat & 0x00000001) { 962 gf100_gr_trap_gpc_rop(gr, gpc); 963 stat &= ~0x00000001; 964 } 965 966 if (stat & 0x00000002) { 967 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); 968 nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap); 969 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); 970 stat &= ~0x00000002; 971 } 972 973 if (stat & 0x00000004) { 974 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); 975 nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap); 976 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); 977 stat &= ~0x00000004; 978 } 979 980 if (stat & 0x00000008) { 981 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); 982 nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap); 983 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); 984 stat &= ~0x00000009; 985 } 986 987 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { 988 u32 mask = 0x00010000 << tpc; 989 if (stat & mask) { 990 gf100_gr_trap_tpc(gr, gpc, tpc); 991 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); 992 stat &= ~mask; 993 } 994 } 995 996 if (stat) { 997 nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat); 998 } 999 } 1000 1001 static void 1002 gf100_gr_trap_intr(struct gf100_gr *gr) 1003 { 1004 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1005 struct nvkm_device *device = subdev->device; 1006 u32 trap = nvkm_rd32(device, 0x400108); 1007 int rop, gpc; 1008 1009 if (trap & 0x00000001) { 1010 u32 stat = nvkm_rd32(device, 0x404000); 1011 nvkm_error(subdev, "DISPATCH %08x\n", stat); 1012 nvkm_wr32(device, 0x404000, 0xc0000000); 1013 nvkm_wr32(device, 0x400108, 0x00000001); 1014 trap &= ~0x00000001; 1015 } 1016 1017 if (trap & 0x00000002) { 1018 u32 stat = nvkm_rd32(device, 0x404600); 1019 nvkm_error(subdev, "M2MF %08x\n", stat); 1020 nvkm_wr32(device, 0x404600, 0xc0000000); 1021 nvkm_wr32(device, 0x400108, 0x00000002); 1022 trap &= ~0x00000002; 1023 } 1024 1025 if (trap & 0x00000008) { 1026 u32 stat = nvkm_rd32(device, 0x408030); 1027 nvkm_error(subdev, "CCACHE %08x\n", stat); 1028 nvkm_wr32(device, 0x408030, 0xc0000000); 1029 nvkm_wr32(device, 0x400108, 0x00000008); 1030 trap &= ~0x00000008; 1031 } 1032 1033 if (trap & 0x00000010) { 1034 u32 stat = nvkm_rd32(device, 0x405840); 1035 nvkm_error(subdev, "SHADER %08x\n", stat); 1036 nvkm_wr32(device, 0x405840, 0xc0000000); 1037 nvkm_wr32(device, 0x400108, 0x00000010); 1038 trap &= ~0x00000010; 1039 } 1040 1041 if (trap & 0x00000040) { 1042 u32 stat = nvkm_rd32(device, 0x40601c); 1043 nvkm_error(subdev, "UNK6 %08x\n", stat); 1044 nvkm_wr32(device, 0x40601c, 0xc0000000); 1045 nvkm_wr32(device, 0x400108, 0x00000040); 1046 trap &= ~0x00000040; 1047 } 1048 1049 if (trap & 0x00000080) { 1050 u32 stat = nvkm_rd32(device, 0x404490); 1051 nvkm_error(subdev, "MACRO %08x\n", stat); 1052 nvkm_wr32(device, 0x404490, 0xc0000000); 1053 nvkm_wr32(device, 0x400108, 0x00000080); 1054 trap &= ~0x00000080; 1055 } 1056 1057 if (trap & 0x00000100) { 1058 u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff; 1059 char sked[128]; 1060 1061 nvkm_snprintbf(sked, sizeof(sked), gk104_sked_error, stat); 1062 nvkm_error(subdev, "SKED: %08x [%s]\n", stat, sked); 1063 1064 if (stat) 1065 nvkm_wr32(device, 0x407020, 0x40000000); 1066 nvkm_wr32(device, 0x400108, 0x00000100); 1067 trap &= ~0x00000100; 1068 } 1069 1070 if (trap & 0x01000000) { 1071 u32 stat = nvkm_rd32(device, 0x400118); 1072 for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { 1073 u32 mask = 0x00000001 << gpc; 1074 if (stat & mask) { 1075 gf100_gr_trap_gpc(gr, gpc); 1076 nvkm_wr32(device, 0x400118, mask); 1077 stat &= ~mask; 1078 } 1079 } 1080 nvkm_wr32(device, 0x400108, 0x01000000); 1081 trap &= ~0x01000000; 1082 } 1083 1084 if (trap & 0x02000000) { 1085 for (rop = 0; rop < gr->rop_nr; rop++) { 1086 u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); 1087 u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); 1088 nvkm_error(subdev, "ROP%d %08x %08x\n", 1089 rop, statz, statc); 1090 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); 1091 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); 1092 } 1093 nvkm_wr32(device, 0x400108, 0x02000000); 1094 trap &= ~0x02000000; 1095 } 1096 1097 if (trap) { 1098 nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap); 1099 nvkm_wr32(device, 0x400108, trap); 1100 } 1101 } 1102 1103 static void 1104 gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) 1105 { 1106 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1107 struct nvkm_device *device = subdev->device; 1108 nvkm_error(subdev, "%06x - done %08x\n", base, 1109 nvkm_rd32(device, base + 0x400)); 1110 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, 1111 nvkm_rd32(device, base + 0x800), 1112 nvkm_rd32(device, base + 0x804), 1113 nvkm_rd32(device, base + 0x808), 1114 nvkm_rd32(device, base + 0x80c)); 1115 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, 1116 nvkm_rd32(device, base + 0x810), 1117 nvkm_rd32(device, base + 0x814), 1118 nvkm_rd32(device, base + 0x818), 1119 nvkm_rd32(device, base + 0x81c)); 1120 } 1121 1122 void 1123 gf100_gr_ctxctl_debug(struct gf100_gr *gr) 1124 { 1125 struct nvkm_device *device = gr->base.engine.subdev.device; 1126 u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff; 1127 u32 gpc; 1128 1129 gf100_gr_ctxctl_debug_unit(gr, 0x409000); 1130 for (gpc = 0; gpc < gpcnr; gpc++) 1131 gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000)); 1132 } 1133 1134 static void 1135 gf100_gr_ctxctl_isr(struct gf100_gr *gr) 1136 { 1137 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1138 struct nvkm_device *device = subdev->device; 1139 u32 stat = nvkm_rd32(device, 0x409c18); 1140 1141 if (stat & 0x00000001) { 1142 u32 code = nvkm_rd32(device, 0x409814); 1143 if (code == E_BAD_FWMTHD) { 1144 u32 class = nvkm_rd32(device, 0x409808); 1145 u32 addr = nvkm_rd32(device, 0x40980c); 1146 u32 subc = (addr & 0x00070000) >> 16; 1147 u32 mthd = (addr & 0x00003ffc); 1148 u32 data = nvkm_rd32(device, 0x409810); 1149 1150 nvkm_error(subdev, "FECS MTHD subc %d class %04x " 1151 "mthd %04x data %08x\n", 1152 subc, class, mthd, data); 1153 1154 nvkm_wr32(device, 0x409c20, 0x00000001); 1155 stat &= ~0x00000001; 1156 } else { 1157 nvkm_error(subdev, "FECS ucode error %d\n", code); 1158 } 1159 } 1160 1161 if (stat & 0x00080000) { 1162 nvkm_error(subdev, "FECS watchdog timeout\n"); 1163 gf100_gr_ctxctl_debug(gr); 1164 nvkm_wr32(device, 0x409c20, 0x00080000); 1165 stat &= ~0x00080000; 1166 } 1167 1168 if (stat) { 1169 nvkm_error(subdev, "FECS %08x\n", stat); 1170 gf100_gr_ctxctl_debug(gr); 1171 nvkm_wr32(device, 0x409c20, stat); 1172 } 1173 } 1174 1175 static void 1176 gf100_gr_intr(struct nvkm_subdev *subdev) 1177 { 1178 struct gf100_gr *gr = (void *)subdev; 1179 struct nvkm_device *device = gr->base.engine.subdev.device; 1180 struct nvkm_fifo_chan *chan; 1181 unsigned long flags; 1182 u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; 1183 u32 stat = nvkm_rd32(device, 0x400100); 1184 u32 addr = nvkm_rd32(device, 0x400704); 1185 u32 mthd = (addr & 0x00003ffc); 1186 u32 subc = (addr & 0x00070000) >> 16; 1187 u32 data = nvkm_rd32(device, 0x400708); 1188 u32 code = nvkm_rd32(device, 0x400110); 1189 u32 class; 1190 const char *name = "unknown"; 1191 int chid = -1; 1192 1193 chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags); 1194 if (chan) { 1195 name = chan->object.client->name; 1196 chid = chan->chid; 1197 } 1198 1199 if (nv_device(gr)->card_type < NV_E0 || subc < 4) 1200 class = nvkm_rd32(device, 0x404200 + (subc * 4)); 1201 else 1202 class = 0x0000; 1203 1204 if (stat & 0x00000001) { 1205 /* 1206 * notifier interrupt, only needed for cyclestats 1207 * can be safely ignored 1208 */ 1209 nvkm_wr32(device, 0x400100, 0x00000001); 1210 stat &= ~0x00000001; 1211 } 1212 1213 if (stat & 0x00000010) { 1214 if (!gf100_gr_mthd_sw(device, class, mthd, data)) { 1215 nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] " 1216 "subc %d class %04x mthd %04x data %08x\n", 1217 chid, inst << 12, name, subc, 1218 class, mthd, data); 1219 } 1220 nvkm_wr32(device, 0x400100, 0x00000010); 1221 stat &= ~0x00000010; 1222 } 1223 1224 if (stat & 0x00000020) { 1225 nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] " 1226 "subc %d class %04x mthd %04x data %08x\n", 1227 chid, inst << 12, name, subc, class, mthd, data); 1228 nvkm_wr32(device, 0x400100, 0x00000020); 1229 stat &= ~0x00000020; 1230 } 1231 1232 if (stat & 0x00100000) { 1233 const struct nvkm_enum *en = 1234 nvkm_enum_find(nv50_data_error_names, code); 1235 nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] " 1236 "subc %d class %04x mthd %04x data %08x\n", 1237 code, en ? en->name : "", chid, inst << 12, 1238 name, subc, class, mthd, data); 1239 nvkm_wr32(device, 0x400100, 0x00100000); 1240 stat &= ~0x00100000; 1241 } 1242 1243 if (stat & 0x00200000) { 1244 nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n", 1245 chid, inst << 12, name); 1246 gf100_gr_trap_intr(gr); 1247 nvkm_wr32(device, 0x400100, 0x00200000); 1248 stat &= ~0x00200000; 1249 } 1250 1251 if (stat & 0x00080000) { 1252 gf100_gr_ctxctl_isr(gr); 1253 nvkm_wr32(device, 0x400100, 0x00080000); 1254 stat &= ~0x00080000; 1255 } 1256 1257 if (stat) { 1258 nvkm_error(subdev, "intr %08x\n", stat); 1259 nvkm_wr32(device, 0x400100, stat); 1260 } 1261 1262 nvkm_wr32(device, 0x400500, 0x00010001); 1263 nvkm_fifo_chan_put(device->fifo, flags, &chan); 1264 } 1265 1266 void 1267 gf100_gr_init_fw(struct gf100_gr *gr, u32 fuc_base, 1268 struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) 1269 { 1270 struct nvkm_device *device = gr->base.engine.subdev.device; 1271 int i; 1272 1273 nvkm_wr32(device, fuc_base + 0x01c0, 0x01000000); 1274 for (i = 0; i < data->size / 4; i++) 1275 nvkm_wr32(device, fuc_base + 0x01c4, data->data[i]); 1276 1277 nvkm_wr32(device, fuc_base + 0x0180, 0x01000000); 1278 for (i = 0; i < code->size / 4; i++) { 1279 if ((i & 0x3f) == 0) 1280 nvkm_wr32(device, fuc_base + 0x0188, i >> 6); 1281 nvkm_wr32(device, fuc_base + 0x0184, code->data[i]); 1282 } 1283 1284 /* code must be padded to 0x40 words */ 1285 for (; i & 0x3f; i++) 1286 nvkm_wr32(device, fuc_base + 0x0184, 0); 1287 } 1288 1289 static void 1290 gf100_gr_init_csdata(struct gf100_gr *gr, 1291 const struct gf100_gr_pack *pack, 1292 u32 falcon, u32 starstar, u32 base) 1293 { 1294 struct nvkm_device *device = gr->base.engine.subdev.device; 1295 const struct gf100_gr_pack *iter; 1296 const struct gf100_gr_init *init; 1297 u32 addr = ~0, prev = ~0, xfer = 0; 1298 u32 star, temp; 1299 1300 nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar); 1301 star = nvkm_rd32(device, falcon + 0x01c4); 1302 temp = nvkm_rd32(device, falcon + 0x01c4); 1303 if (temp > star) 1304 star = temp; 1305 nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star); 1306 1307 pack_for_each_init(init, iter, pack) { 1308 u32 head = init->addr - base; 1309 u32 tail = head + init->count * init->pitch; 1310 while (head < tail) { 1311 if (head != prev + 4 || xfer >= 32) { 1312 if (xfer) { 1313 u32 data = ((--xfer << 26) | addr); 1314 nvkm_wr32(device, falcon + 0x01c4, data); 1315 star += 4; 1316 } 1317 addr = head; 1318 xfer = 0; 1319 } 1320 prev = head; 1321 xfer = xfer + 1; 1322 head = head + init->pitch; 1323 } 1324 } 1325 1326 nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr); 1327 nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar); 1328 nvkm_wr32(device, falcon + 0x01c4, star + 4); 1329 } 1330 1331 int 1332 gf100_gr_init_ctxctl(struct gf100_gr *gr) 1333 { 1334 const struct gf100_grctx_func *grctx = gr->func->grctx; 1335 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1336 struct nvkm_device *device = subdev->device; 1337 struct gf100_gr_oclass *oclass = (void *)nv_object(gr)->oclass; 1338 int i; 1339 1340 if (gr->firmware) { 1341 /* load fuc microcode */ 1342 nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); 1343 gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, 1344 &gr->fuc409d); 1345 gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, 1346 &gr->fuc41ad); 1347 nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); 1348 1349 /* start both of them running */ 1350 nvkm_wr32(device, 0x409840, 0xffffffff); 1351 nvkm_wr32(device, 0x41a10c, 0x00000000); 1352 nvkm_wr32(device, 0x40910c, 0x00000000); 1353 nvkm_wr32(device, 0x41a100, 0x00000002); 1354 nvkm_wr32(device, 0x409100, 0x00000002); 1355 if (nvkm_msec(device, 2000, 1356 if (nvkm_rd32(device, 0x409800) & 0x00000001) 1357 break; 1358 ) < 0) 1359 return -EBUSY; 1360 1361 nvkm_wr32(device, 0x409840, 0xffffffff); 1362 nvkm_wr32(device, 0x409500, 0x7fffffff); 1363 nvkm_wr32(device, 0x409504, 0x00000021); 1364 1365 nvkm_wr32(device, 0x409840, 0xffffffff); 1366 nvkm_wr32(device, 0x409500, 0x00000000); 1367 nvkm_wr32(device, 0x409504, 0x00000010); 1368 if (nvkm_msec(device, 2000, 1369 if ((gr->size = nvkm_rd32(device, 0x409800))) 1370 break; 1371 ) < 0) 1372 return -EBUSY; 1373 1374 nvkm_wr32(device, 0x409840, 0xffffffff); 1375 nvkm_wr32(device, 0x409500, 0x00000000); 1376 nvkm_wr32(device, 0x409504, 0x00000016); 1377 if (nvkm_msec(device, 2000, 1378 if (nvkm_rd32(device, 0x409800)) 1379 break; 1380 ) < 0) 1381 return -EBUSY; 1382 1383 nvkm_wr32(device, 0x409840, 0xffffffff); 1384 nvkm_wr32(device, 0x409500, 0x00000000); 1385 nvkm_wr32(device, 0x409504, 0x00000025); 1386 if (nvkm_msec(device, 2000, 1387 if (nvkm_rd32(device, 0x409800)) 1388 break; 1389 ) < 0) 1390 return -EBUSY; 1391 1392 if (nv_device(gr)->chipset >= 0xe0) { 1393 nvkm_wr32(device, 0x409800, 0x00000000); 1394 nvkm_wr32(device, 0x409500, 0x00000001); 1395 nvkm_wr32(device, 0x409504, 0x00000030); 1396 if (nvkm_msec(device, 2000, 1397 if (nvkm_rd32(device, 0x409800)) 1398 break; 1399 ) < 0) 1400 return -EBUSY; 1401 1402 nvkm_wr32(device, 0x409810, 0xb00095c8); 1403 nvkm_wr32(device, 0x409800, 0x00000000); 1404 nvkm_wr32(device, 0x409500, 0x00000001); 1405 nvkm_wr32(device, 0x409504, 0x00000031); 1406 if (nvkm_msec(device, 2000, 1407 if (nvkm_rd32(device, 0x409800)) 1408 break; 1409 ) < 0) 1410 return -EBUSY; 1411 1412 nvkm_wr32(device, 0x409810, 0x00080420); 1413 nvkm_wr32(device, 0x409800, 0x00000000); 1414 nvkm_wr32(device, 0x409500, 0x00000001); 1415 nvkm_wr32(device, 0x409504, 0x00000032); 1416 if (nvkm_msec(device, 2000, 1417 if (nvkm_rd32(device, 0x409800)) 1418 break; 1419 ) < 0) 1420 return -EBUSY; 1421 1422 nvkm_wr32(device, 0x409614, 0x00000070); 1423 nvkm_wr32(device, 0x409614, 0x00000770); 1424 nvkm_wr32(device, 0x40802c, 0x00000001); 1425 } 1426 1427 if (gr->data == NULL) { 1428 int ret = gf100_grctx_generate(gr); 1429 if (ret) { 1430 nvkm_error(subdev, "failed to construct context\n"); 1431 return ret; 1432 } 1433 } 1434 1435 return 0; 1436 } else 1437 if (!oclass->fecs.ucode) { 1438 return -ENOSYS; 1439 } 1440 1441 /* load HUB microcode */ 1442 nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); 1443 nvkm_wr32(device, 0x4091c0, 0x01000000); 1444 for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) 1445 nvkm_wr32(device, 0x4091c4, oclass->fecs.ucode->data.data[i]); 1446 1447 nvkm_wr32(device, 0x409180, 0x01000000); 1448 for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) { 1449 if ((i & 0x3f) == 0) 1450 nvkm_wr32(device, 0x409188, i >> 6); 1451 nvkm_wr32(device, 0x409184, oclass->fecs.ucode->code.data[i]); 1452 } 1453 1454 /* load GPC microcode */ 1455 nvkm_wr32(device, 0x41a1c0, 0x01000000); 1456 for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++) 1457 nvkm_wr32(device, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); 1458 1459 nvkm_wr32(device, 0x41a180, 0x01000000); 1460 for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) { 1461 if ((i & 0x3f) == 0) 1462 nvkm_wr32(device, 0x41a188, i >> 6); 1463 nvkm_wr32(device, 0x41a184, oclass->gpccs.ucode->code.data[i]); 1464 } 1465 nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); 1466 1467 /* load register lists */ 1468 gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000); 1469 gf100_gr_init_csdata(gr, grctx->gpc, 0x41a000, 0x000, 0x418000); 1470 gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800); 1471 gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00); 1472 1473 /* start HUB ucode running, it'll init the GPCs */ 1474 nvkm_wr32(device, 0x40910c, 0x00000000); 1475 nvkm_wr32(device, 0x409100, 0x00000002); 1476 if (nvkm_msec(device, 2000, 1477 if (nvkm_rd32(device, 0x409800) & 0x80000000) 1478 break; 1479 ) < 0) { 1480 gf100_gr_ctxctl_debug(gr); 1481 return -EBUSY; 1482 } 1483 1484 gr->size = nvkm_rd32(device, 0x409804); 1485 if (gr->data == NULL) { 1486 int ret = gf100_grctx_generate(gr); 1487 if (ret) { 1488 nvkm_error(subdev, "failed to construct context\n"); 1489 return ret; 1490 } 1491 } 1492 1493 return 0; 1494 } 1495 1496 int 1497 gf100_gr_init(struct nvkm_object *object) 1498 { 1499 struct gf100_gr *gr = (void *)object; 1500 struct nvkm_device *device = gr->base.engine.subdev.device; 1501 struct gf100_gr_oclass *oclass = (void *)object->oclass; 1502 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); 1503 u32 data[TPC_MAX / 8] = {}; 1504 u8 tpcnr[GPC_MAX]; 1505 int gpc, tpc, rop; 1506 int ret, i; 1507 1508 ret = nvkm_gr_init(&gr->base); 1509 if (ret) 1510 return ret; 1511 1512 nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); 1513 nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000); 1514 nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000); 1515 nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000); 1516 nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); 1517 nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); 1518 nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); 1519 nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); 1520 1521 gf100_gr_mmio(gr, oclass->mmio); 1522 1523 memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); 1524 for (i = 0, gpc = -1; i < gr->tpc_total; i++) { 1525 do { 1526 gpc = (gpc + 1) % gr->gpc_nr; 1527 } while (!tpcnr[gpc]); 1528 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; 1529 1530 data[i / 8] |= tpc << ((i % 8) * 4); 1531 } 1532 1533 nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); 1534 nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); 1535 nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); 1536 nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); 1537 1538 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 1539 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), 1540 gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); 1541 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | 1542 gr->tpc_total); 1543 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); 1544 } 1545 1546 if (nv_device(gr)->chipset != 0xd7) 1547 nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); 1548 else 1549 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); 1550 1551 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); 1552 1553 nvkm_wr32(device, 0x400500, 0x00010001); 1554 1555 nvkm_wr32(device, 0x400100, 0xffffffff); 1556 nvkm_wr32(device, 0x40013c, 0xffffffff); 1557 1558 nvkm_wr32(device, 0x409c24, 0x000f0000); 1559 nvkm_wr32(device, 0x404000, 0xc0000000); 1560 nvkm_wr32(device, 0x404600, 0xc0000000); 1561 nvkm_wr32(device, 0x408030, 0xc0000000); 1562 nvkm_wr32(device, 0x40601c, 0xc0000000); 1563 nvkm_wr32(device, 0x404490, 0xc0000000); 1564 nvkm_wr32(device, 0x406018, 0xc0000000); 1565 nvkm_wr32(device, 0x405840, 0xc0000000); 1566 nvkm_wr32(device, 0x405844, 0x00ffffff); 1567 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); 1568 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); 1569 1570 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 1571 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); 1572 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); 1573 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); 1574 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); 1575 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { 1576 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); 1577 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); 1578 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); 1579 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); 1580 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); 1581 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); 1582 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); 1583 } 1584 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); 1585 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); 1586 } 1587 1588 for (rop = 0; rop < gr->rop_nr; rop++) { 1589 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); 1590 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); 1591 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); 1592 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); 1593 } 1594 1595 nvkm_wr32(device, 0x400108, 0xffffffff); 1596 nvkm_wr32(device, 0x400138, 0xffffffff); 1597 nvkm_wr32(device, 0x400118, 0xffffffff); 1598 nvkm_wr32(device, 0x400130, 0xffffffff); 1599 nvkm_wr32(device, 0x40011c, 0xffffffff); 1600 nvkm_wr32(device, 0x400134, 0xffffffff); 1601 1602 nvkm_wr32(device, 0x400054, 0x34ce3464); 1603 1604 gf100_gr_zbc_init(gr); 1605 1606 return gf100_gr_init_ctxctl(gr); 1607 } 1608 1609 void 1610 gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) 1611 { 1612 kfree(fuc->data); 1613 fuc->data = NULL; 1614 } 1615 1616 int 1617 gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, 1618 struct gf100_gr_fuc *fuc) 1619 { 1620 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 1621 struct nvkm_device *device = subdev->device; 1622 const struct firmware *fw; 1623 char f[64]; 1624 char cname[16]; 1625 int ret; 1626 int i; 1627 1628 /* Convert device name to lowercase */ 1629 strncpy(cname, device->chip->name, sizeof(cname)); 1630 cname[sizeof(cname) - 1] = '\0'; 1631 i = strlen(cname); 1632 while (i) { 1633 --i; 1634 cname[i] = tolower(cname[i]); 1635 } 1636 1637 snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); 1638 ret = request_firmware(&fw, f, nv_device_base(device)); 1639 if (ret) { 1640 nvkm_error(subdev, "failed to load %s\n", fwname); 1641 return ret; 1642 } 1643 1644 fuc->size = fw->size; 1645 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); 1646 release_firmware(fw); 1647 return (fuc->data != NULL) ? 0 : -ENOMEM; 1648 } 1649 1650 void 1651 gf100_gr_dtor(struct nvkm_object *object) 1652 { 1653 struct gf100_gr *gr = (void *)object; 1654 1655 kfree(gr->data); 1656 1657 gf100_gr_dtor_fw(&gr->fuc409c); 1658 gf100_gr_dtor_fw(&gr->fuc409d); 1659 gf100_gr_dtor_fw(&gr->fuc41ac); 1660 gf100_gr_dtor_fw(&gr->fuc41ad); 1661 1662 nvkm_memory_del(&gr->unk4188b8); 1663 nvkm_memory_del(&gr->unk4188b4); 1664 1665 nvkm_gr_destroy(&gr->base); 1666 } 1667 1668 static const struct nvkm_gr_func 1669 gf100_gr_ = { 1670 .chan_new = gf100_gr_chan_new, 1671 .object_get = gf100_gr_object_get, 1672 }; 1673 1674 int 1675 gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 1676 struct nvkm_oclass *bclass, void *data, u32 size, 1677 struct nvkm_object **pobject) 1678 { 1679 struct gf100_gr_oclass *oclass = (void *)bclass; 1680 struct nvkm_device *device = (void *)parent; 1681 struct gf100_gr *gr; 1682 bool use_ext_fw, enable; 1683 int ret, i, j; 1684 1685 use_ext_fw = nvkm_boolopt(device->cfgopt, "NvGrUseFW", 1686 oclass->fecs.ucode == NULL); 1687 enable = use_ext_fw || oclass->fecs.ucode != NULL; 1688 1689 ret = nvkm_gr_create(parent, engine, bclass, enable, &gr); 1690 *pobject = nv_object(gr); 1691 if (ret) 1692 return ret; 1693 1694 gr->func = oclass->func; 1695 gr->base.func = &gf100_gr_; 1696 nv_subdev(gr)->unit = 0x08001000; 1697 nv_subdev(gr)->intr = gf100_gr_intr; 1698 1699 gr->base.units = gf100_gr_units; 1700 1701 if (use_ext_fw) { 1702 nvkm_info(&gr->base.engine.subdev, "using external firmware\n"); 1703 if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || 1704 gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || 1705 gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || 1706 gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) 1707 return -ENODEV; 1708 gr->firmware = true; 1709 } 1710 1711 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, 1712 &gr->unk4188b4); 1713 if (ret) 1714 return ret; 1715 1716 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, 1717 &gr->unk4188b8); 1718 if (ret) 1719 return ret; 1720 1721 nvkm_kmap(gr->unk4188b4); 1722 for (i = 0; i < 0x1000; i += 4) 1723 nvkm_wo32(gr->unk4188b4, i, 0x00000010); 1724 nvkm_done(gr->unk4188b4); 1725 1726 nvkm_kmap(gr->unk4188b8); 1727 for (i = 0; i < 0x1000; i += 4) 1728 nvkm_wo32(gr->unk4188b8, i, 0x00000010); 1729 nvkm_done(gr->unk4188b8); 1730 1731 gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; 1732 gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; 1733 for (i = 0; i < gr->gpc_nr; i++) { 1734 gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); 1735 gr->tpc_total += gr->tpc_nr[i]; 1736 gr->ppc_nr[i] = oclass->ppc_nr; 1737 for (j = 0; j < gr->ppc_nr[i]; j++) { 1738 u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); 1739 gr->ppc_tpc_nr[i][j] = hweight8(mask); 1740 } 1741 } 1742 1743 /*XXX: these need figuring out... though it might not even matter */ 1744 switch (nv_device(gr)->chipset) { 1745 case 0xc0: 1746 if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ 1747 gr->magic_not_rop_nr = 0x07; 1748 } else 1749 if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ 1750 gr->magic_not_rop_nr = 0x05; 1751 } else 1752 if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ 1753 gr->magic_not_rop_nr = 0x06; 1754 } 1755 break; 1756 case 0xc3: /* 450, 4/0/0/0, 2 */ 1757 gr->magic_not_rop_nr = 0x03; 1758 break; 1759 case 0xc4: /* 460, 3/4/0/0, 4 */ 1760 gr->magic_not_rop_nr = 0x01; 1761 break; 1762 case 0xc1: /* 2/0/0/0, 1 */ 1763 gr->magic_not_rop_nr = 0x01; 1764 break; 1765 case 0xc8: /* 4/4/3/4, 5 */ 1766 gr->magic_not_rop_nr = 0x06; 1767 break; 1768 case 0xce: /* 4/4/0/0, 4 */ 1769 gr->magic_not_rop_nr = 0x03; 1770 break; 1771 case 0xcf: /* 4/0/0/0, 3 */ 1772 gr->magic_not_rop_nr = 0x03; 1773 break; 1774 case 0xd7: 1775 case 0xd9: /* 1/0/0/0, 1 */ 1776 case 0xea: /* gk20a */ 1777 case 0x12b: /* gm20b */ 1778 gr->magic_not_rop_nr = 0x01; 1779 break; 1780 } 1781 1782 return 0; 1783 } 1784 1785 #include "fuc/hubgf100.fuc3.h" 1786 1787 struct gf100_gr_ucode 1788 gf100_gr_fecs_ucode = { 1789 .code.data = gf100_grhub_code, 1790 .code.size = sizeof(gf100_grhub_code), 1791 .data.data = gf100_grhub_data, 1792 .data.size = sizeof(gf100_grhub_data), 1793 }; 1794 1795 #include "fuc/gpcgf100.fuc3.h" 1796 1797 struct gf100_gr_ucode 1798 gf100_gr_gpccs_ucode = { 1799 .code.data = gf100_grgpc_code, 1800 .code.size = sizeof(gf100_grgpc_code), 1801 .data.data = gf100_grgpc_data, 1802 .data.size = sizeof(gf100_grgpc_data), 1803 }; 1804 1805 static const struct gf100_gr_func 1806 gf100_gr = { 1807 .grctx = &gf100_grctx, 1808 .sclass = { 1809 { -1, -1, FERMI_TWOD_A }, 1810 { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A }, 1811 { -1, -1, FERMI_A, &gf100_fermi }, 1812 { -1, -1, FERMI_COMPUTE_A }, 1813 {} 1814 } 1815 }; 1816 1817 struct nvkm_oclass * 1818 gf100_gr_oclass = &(struct gf100_gr_oclass) { 1819 .base.handle = NV_ENGINE(GR, 0xc0), 1820 .base.ofuncs = &(struct nvkm_ofuncs) { 1821 .ctor = gf100_gr_ctor, 1822 .dtor = gf100_gr_dtor, 1823 .init = gf100_gr_init, 1824 .fini = _nvkm_gr_fini, 1825 }, 1826 .func = &gf100_gr, 1827 .mmio = gf100_gr_pack_mmio, 1828 .fecs.ucode = &gf100_gr_fecs_ucode, 1829 .gpccs.ucode = &gf100_gr_gpccs_ucode, 1830 }.base; 1831