1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "gf100.h" 25 #include "ctxgf100.h" 26 #include "fuc/os.h" 27 28 #include <core/client.h> 29 #include <core/handle.h> 30 #include <core/option.h> 31 #include <engine/fifo.h> 32 #include <subdev/fb.h> 33 #include <subdev/mc.h> 34 #include <subdev/timer.h> 35 36 #include <nvif/class.h> 37 #include <nvif/unpack.h> 38 39 /******************************************************************************* 40 * Zero Bandwidth Clear 41 ******************************************************************************/ 42 43 static void 44 gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) 45 { 46 struct nvkm_device *device = gr->base.engine.subdev.device; 47 if (gr->zbc_color[zbc].format) { 48 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); 49 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); 50 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); 51 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); 52 } 53 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); 54 nvkm_wr32(device, 0x405820, zbc); 55 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ 56 } 57 58 static int 59 gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, 60 const u32 ds[4], const u32 l2[4]) 61 { 62 struct nvkm_ltc *ltc = nvkm_ltc(gr); 63 int zbc = -ENOSPC, i; 64 65 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { 66 if (gr->zbc_color[i].format) { 67 if (gr->zbc_color[i].format != format) 68 continue; 69 if (memcmp(gr->zbc_color[i].ds, ds, sizeof( 70 gr->zbc_color[i].ds))) 71 continue; 72 if (memcmp(gr->zbc_color[i].l2, l2, sizeof( 73 gr->zbc_color[i].l2))) { 74 WARN_ON(1); 75 return -EINVAL; 76 } 77 return i; 78 } else { 79 zbc = (zbc < 0) ? i : zbc; 80 } 81 } 82 83 if (zbc < 0) 84 return zbc; 85 86 memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); 87 memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); 88 gr->zbc_color[zbc].format = format; 89 ltc->zbc_color_get(ltc, zbc, l2); 90 gf100_gr_zbc_clear_color(gr, zbc); 91 return zbc; 92 } 93 94 static void 95 gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) 96 { 97 struct nvkm_device *device = gr->base.engine.subdev.device; 98 if (gr->zbc_depth[zbc].format) 99 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); 100 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); 101 nvkm_wr32(device, 0x405820, zbc); 102 nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ 103 } 104 105 static int 106 gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, 107 const u32 ds, const u32 l2) 108 { 109 struct nvkm_ltc *ltc = nvkm_ltc(gr); 110 int zbc = -ENOSPC, i; 111 112 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { 113 if (gr->zbc_depth[i].format) { 114 if (gr->zbc_depth[i].format != format) 115 continue; 116 if (gr->zbc_depth[i].ds != ds) 117 continue; 118 if (gr->zbc_depth[i].l2 != l2) { 119 WARN_ON(1); 120 return -EINVAL; 121 } 122 return i; 123 } else { 124 zbc = (zbc < 0) ? i : zbc; 125 } 126 } 127 128 if (zbc < 0) 129 return zbc; 130 131 gr->zbc_depth[zbc].format = format; 132 gr->zbc_depth[zbc].ds = ds; 133 gr->zbc_depth[zbc].l2 = l2; 134 ltc->zbc_depth_get(ltc, zbc, l2); 135 gf100_gr_zbc_clear_depth(gr, zbc); 136 return zbc; 137 } 138 139 /******************************************************************************* 140 * Graphics object classes 141 ******************************************************************************/ 142 143 static int 144 gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) 145 { 146 struct gf100_gr *gr = (void *)object->engine; 147 union { 148 struct fermi_a_zbc_color_v0 v0; 149 } *args = data; 150 int ret; 151 152 if (nvif_unpack(args->v0, 0, 0, false)) { 153 switch (args->v0.format) { 154 case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: 155 case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: 156 case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32: 157 case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16: 158 case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16: 159 case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16: 160 case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16: 161 case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16: 162 case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8: 163 case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8: 164 case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10: 165 case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10: 166 case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8: 167 case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8: 168 case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8: 169 case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8: 170 case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: 171 case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: 172 case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: 173 ret = gf100_gr_zbc_color_get(gr, args->v0.format, 174 args->v0.ds, 175 args->v0.l2); 176 if (ret >= 0) { 177 args->v0.index = ret; 178 return 0; 179 } 180 break; 181 default: 182 return -EINVAL; 183 } 184 } 185 186 return ret; 187 } 188 189 static int 190 gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) 191 { 192 struct gf100_gr *gr = (void *)object->engine; 193 union { 194 struct fermi_a_zbc_depth_v0 v0; 195 } *args = data; 196 int ret; 197 198 if (nvif_unpack(args->v0, 0, 0, false)) { 199 switch (args->v0.format) { 200 case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: 201 ret = gf100_gr_zbc_depth_get(gr, args->v0.format, 202 args->v0.ds, 203 args->v0.l2); 204 return (ret >= 0) ? 0 : -ENOSPC; 205 default: 206 return -EINVAL; 207 } 208 } 209 210 return ret; 211 } 212 213 static int 214 gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) 215 { 216 switch (mthd) { 217 case FERMI_A_ZBC_COLOR: 218 return gf100_fermi_mthd_zbc_color(object, data, size); 219 case FERMI_A_ZBC_DEPTH: 220 return gf100_fermi_mthd_zbc_depth(object, data, size); 221 default: 222 break; 223 } 224 return -EINVAL; 225 } 226 227 struct nvkm_ofuncs 228 gf100_fermi_ofuncs = { 229 .ctor = _nvkm_object_ctor, 230 .dtor = nvkm_object_destroy, 231 .init = nvkm_object_init, 232 .fini = nvkm_object_fini, 233 .mthd = gf100_fermi_mthd, 234 }; 235 236 static int 237 gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd, 238 void *pdata, u32 size) 239 { 240 struct gf100_gr *gr = (void *)object->engine; 241 struct nvkm_device *device = gr->base.engine.subdev.device; 242 if (size >= sizeof(u32)) { 243 u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000; 244 nvkm_wr32(device, 0x419e44, data); 245 nvkm_wr32(device, 0x419e4c, data); 246 return 0; 247 } 248 return -EINVAL; 249 } 250 251 struct nvkm_omthds 252 gf100_gr_9097_omthds[] = { 253 { 0x1528, 0x1528, gf100_gr_set_shader_exceptions }, 254 {} 255 }; 256 257 struct nvkm_omthds 258 gf100_gr_90c0_omthds[] = { 259 { 0x1528, 0x1528, gf100_gr_set_shader_exceptions }, 260 {} 261 }; 262 263 struct nvkm_oclass 264 gf100_gr_sclass[] = { 265 { FERMI_TWOD_A, &nvkm_object_ofuncs }, 266 { FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs }, 267 { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, 268 { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, 269 {} 270 }; 271 272 /******************************************************************************* 273 * PGRAPH context 274 ******************************************************************************/ 275 276 int 277 gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 278 struct nvkm_oclass *oclass, void *args, u32 size, 279 struct nvkm_object **pobject) 280 { 281 struct nvkm_vm *vm = nvkm_client(parent)->vm; 282 struct gf100_gr *gr = (void *)engine; 283 struct gf100_gr_data *data = gr->mmio_data; 284 struct gf100_gr_mmio *mmio = gr->mmio_list; 285 struct gf100_gr_chan *chan; 286 int ret, i; 287 288 /* allocate memory for context, and fill with default values */ 289 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 290 gr->size, 0x100, 291 NVOBJ_FLAG_ZERO_ALLOC, &chan); 292 *pobject = nv_object(chan); 293 if (ret) 294 return ret; 295 296 /* allocate memory for a "mmio list" buffer that's used by the HUB 297 * fuc to modify some per-context register settings on first load 298 * of the context. 299 */ 300 ret = nvkm_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0, 301 &chan->mmio); 302 if (ret) 303 return ret; 304 305 ret = nvkm_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm, 306 NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS, 307 &chan->mmio_vma); 308 if (ret) 309 return ret; 310 311 /* allocate buffers referenced by mmio list */ 312 for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) { 313 ret = nvkm_gpuobj_new(nv_object(chan), NULL, data->size, 314 data->align, 0, &chan->data[i].mem); 315 if (ret) 316 return ret; 317 318 ret = nvkm_gpuobj_map_vm(chan->data[i].mem, vm, data->access, 319 &chan->data[i].vma); 320 if (ret) 321 return ret; 322 323 data++; 324 } 325 326 /* finally, fill in the mmio list and point the context at it */ 327 for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) { 328 u32 addr = mmio->addr; 329 u32 data = mmio->data; 330 331 if (mmio->buffer >= 0) { 332 u64 info = chan->data[mmio->buffer].vma.offset; 333 data |= info >> mmio->shift; 334 } 335 336 nv_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); 337 nv_wo32(chan->mmio, chan->mmio_nr++ * 4, data); 338 mmio++; 339 } 340 341 for (i = 0; i < gr->size; i += 4) 342 nv_wo32(chan, i, gr->data[i / 4]); 343 344 if (!gr->firmware) { 345 nv_wo32(chan, 0x00, chan->mmio_nr / 2); 346 nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8); 347 } else { 348 nv_wo32(chan, 0xf4, 0); 349 nv_wo32(chan, 0xf8, 0); 350 nv_wo32(chan, 0x10, chan->mmio_nr / 2); 351 nv_wo32(chan, 0x14, lower_32_bits(chan->mmio_vma.offset)); 352 nv_wo32(chan, 0x18, upper_32_bits(chan->mmio_vma.offset)); 353 nv_wo32(chan, 0x1c, 1); 354 nv_wo32(chan, 0x20, 0); 355 nv_wo32(chan, 0x28, 0); 356 nv_wo32(chan, 0x2c, 0); 357 } 358 359 return 0; 360 } 361 362 void 363 gf100_gr_context_dtor(struct nvkm_object *object) 364 { 365 struct gf100_gr_chan *chan = (void *)object; 366 int i; 367 368 for (i = 0; i < ARRAY_SIZE(chan->data); i++) { 369 nvkm_gpuobj_unmap(&chan->data[i].vma); 370 nvkm_gpuobj_ref(NULL, &chan->data[i].mem); 371 } 372 373 nvkm_gpuobj_unmap(&chan->mmio_vma); 374 nvkm_gpuobj_ref(NULL, &chan->mmio); 375 376 nvkm_gr_context_destroy(&chan->base); 377 } 378 379 /******************************************************************************* 380 * PGRAPH register lists 381 ******************************************************************************/ 382 383 const struct gf100_gr_init 384 gf100_gr_init_main_0[] = { 385 { 0x400080, 1, 0x04, 0x003083c2 }, 386 { 0x400088, 1, 0x04, 0x00006fe7 }, 387 { 0x40008c, 1, 0x04, 0x00000000 }, 388 { 0x400090, 1, 0x04, 0x00000030 }, 389 { 0x40013c, 1, 0x04, 0x013901f7 }, 390 { 0x400140, 1, 0x04, 0x00000100 }, 391 { 0x400144, 1, 0x04, 0x00000000 }, 392 { 0x400148, 1, 0x04, 0x00000110 }, 393 { 0x400138, 1, 0x04, 0x00000000 }, 394 { 0x400130, 2, 0x04, 0x00000000 }, 395 { 0x400124, 1, 0x04, 0x00000002 }, 396 {} 397 }; 398 399 const struct gf100_gr_init 400 gf100_gr_init_fe_0[] = { 401 { 0x40415c, 1, 0x04, 0x00000000 }, 402 { 0x404170, 1, 0x04, 0x00000000 }, 403 {} 404 }; 405 406 const struct gf100_gr_init 407 gf100_gr_init_pri_0[] = { 408 { 0x404488, 2, 0x04, 0x00000000 }, 409 {} 410 }; 411 412 const struct gf100_gr_init 413 gf100_gr_init_rstr2d_0[] = { 414 { 0x407808, 1, 0x04, 0x00000000 }, 415 {} 416 }; 417 418 const struct gf100_gr_init 419 gf100_gr_init_pd_0[] = { 420 { 0x406024, 1, 0x04, 0x00000000 }, 421 {} 422 }; 423 424 const struct gf100_gr_init 425 gf100_gr_init_ds_0[] = { 426 { 0x405844, 1, 0x04, 0x00ffffff }, 427 { 0x405850, 1, 0x04, 0x00000000 }, 428 { 0x405908, 1, 0x04, 0x00000000 }, 429 {} 430 }; 431 432 const struct gf100_gr_init 433 gf100_gr_init_scc_0[] = { 434 { 0x40803c, 1, 0x04, 0x00000000 }, 435 {} 436 }; 437 438 const struct gf100_gr_init 439 gf100_gr_init_prop_0[] = { 440 { 0x4184a0, 1, 0x04, 0x00000000 }, 441 {} 442 }; 443 444 const struct gf100_gr_init 445 gf100_gr_init_gpc_unk_0[] = { 446 { 0x418604, 1, 0x04, 0x00000000 }, 447 { 0x418680, 1, 0x04, 0x00000000 }, 448 { 0x418714, 1, 0x04, 0x80000000 }, 449 { 0x418384, 1, 0x04, 0x00000000 }, 450 {} 451 }; 452 453 const struct gf100_gr_init 454 gf100_gr_init_setup_0[] = { 455 { 0x418814, 3, 0x04, 0x00000000 }, 456 {} 457 }; 458 459 const struct gf100_gr_init 460 gf100_gr_init_crstr_0[] = { 461 { 0x418b04, 1, 0x04, 0x00000000 }, 462 {} 463 }; 464 465 const struct gf100_gr_init 466 gf100_gr_init_setup_1[] = { 467 { 0x4188c8, 1, 0x04, 0x80000000 }, 468 { 0x4188cc, 1, 0x04, 0x00000000 }, 469 { 0x4188d0, 1, 0x04, 0x00010000 }, 470 { 0x4188d4, 1, 0x04, 0x00000001 }, 471 {} 472 }; 473 474 const struct gf100_gr_init 475 gf100_gr_init_zcull_0[] = { 476 { 0x418910, 1, 0x04, 0x00010001 }, 477 { 0x418914, 1, 0x04, 0x00000301 }, 478 { 0x418918, 1, 0x04, 0x00800000 }, 479 { 0x418980, 1, 0x04, 0x77777770 }, 480 { 0x418984, 3, 0x04, 0x77777777 }, 481 {} 482 }; 483 484 const struct gf100_gr_init 485 gf100_gr_init_gpm_0[] = { 486 { 0x418c04, 1, 0x04, 0x00000000 }, 487 { 0x418c88, 1, 0x04, 0x00000000 }, 488 {} 489 }; 490 491 const struct gf100_gr_init 492 gf100_gr_init_gpc_unk_1[] = { 493 { 0x418d00, 1, 0x04, 0x00000000 }, 494 { 0x418f08, 1, 0x04, 0x00000000 }, 495 { 0x418e00, 1, 0x04, 0x00000050 }, 496 { 0x418e08, 1, 0x04, 0x00000000 }, 497 {} 498 }; 499 500 const struct gf100_gr_init 501 gf100_gr_init_gcc_0[] = { 502 { 0x41900c, 1, 0x04, 0x00000000 }, 503 { 0x419018, 1, 0x04, 0x00000000 }, 504 {} 505 }; 506 507 const struct gf100_gr_init 508 gf100_gr_init_tpccs_0[] = { 509 { 0x419d08, 2, 0x04, 0x00000000 }, 510 { 0x419d10, 1, 0x04, 0x00000014 }, 511 {} 512 }; 513 514 const struct gf100_gr_init 515 gf100_gr_init_tex_0[] = { 516 { 0x419ab0, 1, 0x04, 0x00000000 }, 517 { 0x419ab8, 1, 0x04, 0x000000e7 }, 518 { 0x419abc, 2, 0x04, 0x00000000 }, 519 {} 520 }; 521 522 const struct gf100_gr_init 523 gf100_gr_init_pe_0[] = { 524 { 0x41980c, 3, 0x04, 0x00000000 }, 525 { 0x419844, 1, 0x04, 0x00000000 }, 526 { 0x41984c, 1, 0x04, 0x00005bc5 }, 527 { 0x419850, 4, 0x04, 0x00000000 }, 528 {} 529 }; 530 531 const struct gf100_gr_init 532 gf100_gr_init_l1c_0[] = { 533 { 0x419c98, 1, 0x04, 0x00000000 }, 534 { 0x419ca8, 1, 0x04, 0x80000000 }, 535 { 0x419cb4, 1, 0x04, 0x00000000 }, 536 { 0x419cb8, 1, 0x04, 0x00008bf4 }, 537 { 0x419cbc, 1, 0x04, 0x28137606 }, 538 { 0x419cc0, 2, 0x04, 0x00000000 }, 539 {} 540 }; 541 542 const struct gf100_gr_init 543 gf100_gr_init_wwdx_0[] = { 544 { 0x419bd4, 1, 0x04, 0x00800000 }, 545 { 0x419bdc, 1, 0x04, 0x00000000 }, 546 {} 547 }; 548 549 const struct gf100_gr_init 550 gf100_gr_init_tpccs_1[] = { 551 { 0x419d2c, 1, 0x04, 0x00000000 }, 552 {} 553 }; 554 555 const struct gf100_gr_init 556 gf100_gr_init_mpc_0[] = { 557 { 0x419c0c, 1, 0x04, 0x00000000 }, 558 {} 559 }; 560 561 static const struct gf100_gr_init 562 gf100_gr_init_sm_0[] = { 563 { 0x419e00, 1, 0x04, 0x00000000 }, 564 { 0x419ea0, 1, 0x04, 0x00000000 }, 565 { 0x419ea4, 1, 0x04, 0x00000100 }, 566 { 0x419ea8, 1, 0x04, 0x00001100 }, 567 { 0x419eac, 1, 0x04, 0x11100702 }, 568 { 0x419eb0, 1, 0x04, 0x00000003 }, 569 { 0x419eb4, 4, 0x04, 0x00000000 }, 570 { 0x419ec8, 1, 0x04, 0x06060618 }, 571 { 0x419ed0, 1, 0x04, 0x0eff0e38 }, 572 { 0x419ed4, 1, 0x04, 0x011104f1 }, 573 { 0x419edc, 1, 0x04, 0x00000000 }, 574 { 0x419f00, 1, 0x04, 0x00000000 }, 575 { 0x419f2c, 1, 0x04, 0x00000000 }, 576 {} 577 }; 578 579 const struct gf100_gr_init 580 gf100_gr_init_be_0[] = { 581 { 0x40880c, 1, 0x04, 0x00000000 }, 582 { 0x408910, 9, 0x04, 0x00000000 }, 583 { 0x408950, 1, 0x04, 0x00000000 }, 584 { 0x408954, 1, 0x04, 0x0000ffff }, 585 { 0x408984, 1, 0x04, 0x00000000 }, 586 { 0x408988, 1, 0x04, 0x08040201 }, 587 { 0x40898c, 1, 0x04, 0x80402010 }, 588 {} 589 }; 590 591 const struct gf100_gr_init 592 gf100_gr_init_fe_1[] = { 593 { 0x4040f0, 1, 0x04, 0x00000000 }, 594 {} 595 }; 596 597 const struct gf100_gr_init 598 gf100_gr_init_pe_1[] = { 599 { 0x419880, 1, 0x04, 0x00000002 }, 600 {} 601 }; 602 603 static const struct gf100_gr_pack 604 gf100_gr_pack_mmio[] = { 605 { gf100_gr_init_main_0 }, 606 { gf100_gr_init_fe_0 }, 607 { gf100_gr_init_pri_0 }, 608 { gf100_gr_init_rstr2d_0 }, 609 { gf100_gr_init_pd_0 }, 610 { gf100_gr_init_ds_0 }, 611 { gf100_gr_init_scc_0 }, 612 { gf100_gr_init_prop_0 }, 613 { gf100_gr_init_gpc_unk_0 }, 614 { gf100_gr_init_setup_0 }, 615 { gf100_gr_init_crstr_0 }, 616 { gf100_gr_init_setup_1 }, 617 { gf100_gr_init_zcull_0 }, 618 { gf100_gr_init_gpm_0 }, 619 { gf100_gr_init_gpc_unk_1 }, 620 { gf100_gr_init_gcc_0 }, 621 { gf100_gr_init_tpccs_0 }, 622 { gf100_gr_init_tex_0 }, 623 { gf100_gr_init_pe_0 }, 624 { gf100_gr_init_l1c_0 }, 625 { gf100_gr_init_wwdx_0 }, 626 { gf100_gr_init_tpccs_1 }, 627 { gf100_gr_init_mpc_0 }, 628 { gf100_gr_init_sm_0 }, 629 { gf100_gr_init_be_0 }, 630 { gf100_gr_init_fe_1 }, 631 { gf100_gr_init_pe_1 }, 632 {} 633 }; 634 635 /******************************************************************************* 636 * PGRAPH engine/subdev functions 637 ******************************************************************************/ 638 639 void 640 gf100_gr_zbc_init(struct gf100_gr *gr) 641 { 642 const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 643 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 644 const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 645 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; 646 const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 647 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 648 const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 649 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; 650 struct nvkm_ltc *ltc = nvkm_ltc(gr); 651 int index; 652 653 if (!gr->zbc_color[0].format) { 654 gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); 655 gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); 656 gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); 657 gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); 658 gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); 659 gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); 660 } 661 662 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) 663 gf100_gr_zbc_clear_color(gr, index); 664 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) 665 gf100_gr_zbc_clear_depth(gr, index); 666 } 667 668 /** 669 * Wait until GR goes idle. GR is considered idle if it is disabled by the 670 * MC (0x200) register, or GR is not busy and a context switch is not in 671 * progress. 672 */ 673 int 674 gf100_gr_wait_idle(struct gf100_gr *gr) 675 { 676 struct nvkm_device *device = gr->base.engine.subdev.device; 677 unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000); 678 bool gr_enabled, ctxsw_active, gr_busy; 679 680 do { 681 /* 682 * required to make sure FIFO_ENGINE_STATUS (0x2640) is 683 * up-to-date 684 */ 685 nvkm_rd32(device, 0x400700); 686 687 gr_enabled = nvkm_rd32(device, 0x200) & 0x1000; 688 ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000; 689 gr_busy = nvkm_rd32(device, 0x40060c) & 0x1; 690 691 if (!gr_enabled || (!gr_busy && !ctxsw_active)) 692 return 0; 693 } while (time_before(jiffies, end_jiffies)); 694 695 nv_error(gr, "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n", 696 gr_enabled, ctxsw_active, gr_busy); 697 return -EAGAIN; 698 } 699 700 void 701 gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) 702 { 703 struct nvkm_device *device = gr->base.engine.subdev.device; 704 const struct gf100_gr_pack *pack; 705 const struct gf100_gr_init *init; 706 707 pack_for_each_init(init, pack, p) { 708 u32 next = init->addr + init->count * init->pitch; 709 u32 addr = init->addr; 710 while (addr < next) { 711 nvkm_wr32(device, addr, init->data); 712 addr += init->pitch; 713 } 714 } 715 } 716 717 void 718 gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) 719 { 720 struct nvkm_device *device = gr->base.engine.subdev.device; 721 const struct gf100_gr_pack *pack; 722 const struct gf100_gr_init *init; 723 u32 data = 0; 724 725 nvkm_wr32(device, 0x400208, 0x80000000); 726 727 pack_for_each_init(init, pack, p) { 728 u32 next = init->addr + init->count * init->pitch; 729 u32 addr = init->addr; 730 731 if ((pack == p && init == p->init) || data != init->data) { 732 nvkm_wr32(device, 0x400204, init->data); 733 data = init->data; 734 } 735 736 while (addr < next) { 737 nvkm_wr32(device, 0x400200, addr); 738 /** 739 * Wait for GR to go idle after submitting a 740 * GO_IDLE bundle 741 */ 742 if ((addr & 0xffff) == 0xe100) 743 gf100_gr_wait_idle(gr); 744 nv_wait(gr, 0x400700, 0x00000004, 0x00000000); 745 addr += init->pitch; 746 } 747 } 748 749 nvkm_wr32(device, 0x400208, 0x00000000); 750 } 751 752 void 753 gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) 754 { 755 struct nvkm_device *device = gr->base.engine.subdev.device; 756 const struct gf100_gr_pack *pack; 757 const struct gf100_gr_init *init; 758 u32 data = 0; 759 760 pack_for_each_init(init, pack, p) { 761 u32 ctrl = 0x80000000 | pack->type; 762 u32 next = init->addr + init->count * init->pitch; 763 u32 addr = init->addr; 764 765 if ((pack == p && init == p->init) || data != init->data) { 766 nvkm_wr32(device, 0x40448c, init->data); 767 data = init->data; 768 } 769 770 while (addr < next) { 771 nvkm_wr32(device, 0x404488, ctrl | (addr << 14)); 772 addr += init->pitch; 773 } 774 } 775 } 776 777 u64 778 gf100_gr_units(struct nvkm_gr *obj) 779 { 780 struct gf100_gr *gr = container_of(obj, typeof(*gr), base); 781 u64 cfg; 782 783 cfg = (u32)gr->gpc_nr; 784 cfg |= (u32)gr->tpc_total << 8; 785 cfg |= (u64)gr->rop_nr << 32; 786 787 return cfg; 788 } 789 790 static const struct nvkm_enum gk104_sked_error[] = { 791 { 7, "CONSTANT_BUFFER_SIZE" }, 792 { 9, "LOCAL_MEMORY_SIZE_POS" }, 793 { 10, "LOCAL_MEMORY_SIZE_NEG" }, 794 { 11, "WARP_CSTACK_SIZE" }, 795 { 12, "TOTAL_TEMP_SIZE" }, 796 { 13, "REGISTER_COUNT" }, 797 { 18, "TOTAL_THREADS" }, 798 { 20, "PROGRAM_OFFSET" }, 799 { 21, "SHARED_MEMORY_SIZE" }, 800 { 25, "SHARED_CONFIG_TOO_SMALL" }, 801 { 26, "TOTAL_REGISTER_COUNT" }, 802 {} 803 }; 804 805 static const struct nvkm_enum gf100_gpc_rop_error[] = { 806 { 1, "RT_PITCH_OVERRUN" }, 807 { 4, "RT_WIDTH_OVERRUN" }, 808 { 5, "RT_HEIGHT_OVERRUN" }, 809 { 7, "ZETA_STORAGE_TYPE_MISMATCH" }, 810 { 8, "RT_STORAGE_TYPE_MISMATCH" }, 811 { 10, "RT_LINEAR_MISMATCH" }, 812 {} 813 }; 814 815 static void 816 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) 817 { 818 struct nvkm_device *device = gr->base.engine.subdev.device; 819 u32 trap[4]; 820 int i; 821 822 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)); 823 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); 824 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); 825 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); 826 827 nv_error(gr, "GPC%d/PROP trap:", gpc); 828 for (i = 0; i <= 29; ++i) { 829 if (!(trap[0] & (1 << i))) 830 continue; 831 pr_cont(" "); 832 nvkm_enum_print(gf100_gpc_rop_error, i); 833 } 834 pr_cont("\n"); 835 836 nv_error(gr, "x = %u, y = %u, format = %x, storage type = %x\n", 837 trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f, 838 trap[3] & 0xff); 839 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); 840 } 841 842 static const struct nvkm_enum gf100_mp_warp_error[] = { 843 { 0x00, "NO_ERROR" }, 844 { 0x01, "STACK_MISMATCH" }, 845 { 0x05, "MISALIGNED_PC" }, 846 { 0x08, "MISALIGNED_GPR" }, 847 { 0x09, "INVALID_OPCODE" }, 848 { 0x0d, "GPR_OUT_OF_BOUNDS" }, 849 { 0x0e, "MEM_OUT_OF_BOUNDS" }, 850 { 0x0f, "UNALIGNED_MEM_ACCESS" }, 851 { 0x11, "INVALID_PARAM" }, 852 {} 853 }; 854 855 static const struct nvkm_bitfield gf100_mp_global_error[] = { 856 { 0x00000004, "MULTIPLE_WARP_ERRORS" }, 857 { 0x00000008, "OUT_OF_STACK_SPACE" }, 858 {} 859 }; 860 861 static void 862 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) 863 { 864 struct nvkm_device *device = gr->base.engine.subdev.device; 865 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); 866 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); 867 868 nv_error(gr, "GPC%i/TPC%i/MP trap:", gpc, tpc); 869 nvkm_bitfield_print(gf100_mp_global_error, gerr); 870 if (werr) { 871 pr_cont(" "); 872 nvkm_enum_print(gf100_mp_warp_error, werr & 0xffff); 873 } 874 pr_cont("\n"); 875 876 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); 877 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); 878 } 879 880 static void 881 gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) 882 { 883 struct nvkm_device *device = gr->base.engine.subdev.device; 884 u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); 885 886 if (stat & 0x00000001) { 887 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); 888 nv_error(gr, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap); 889 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); 890 stat &= ~0x00000001; 891 } 892 893 if (stat & 0x00000002) { 894 gf100_gr_trap_mp(gr, gpc, tpc); 895 stat &= ~0x00000002; 896 } 897 898 if (stat & 0x00000004) { 899 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); 900 nv_error(gr, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap); 901 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); 902 stat &= ~0x00000004; 903 } 904 905 if (stat & 0x00000008) { 906 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); 907 nv_error(gr, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap); 908 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); 909 stat &= ~0x00000008; 910 } 911 912 if (stat) { 913 nv_error(gr, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat); 914 } 915 } 916 917 static void 918 gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) 919 { 920 struct nvkm_device *device = gr->base.engine.subdev.device; 921 u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); 922 int tpc; 923 924 if (stat & 0x00000001) { 925 gf100_gr_trap_gpc_rop(gr, gpc); 926 stat &= ~0x00000001; 927 } 928 929 if (stat & 0x00000002) { 930 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); 931 nv_error(gr, "GPC%d/ZCULL: 0x%08x\n", gpc, trap); 932 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); 933 stat &= ~0x00000002; 934 } 935 936 if (stat & 0x00000004) { 937 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); 938 nv_error(gr, "GPC%d/CCACHE: 0x%08x\n", gpc, trap); 939 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); 940 stat &= ~0x00000004; 941 } 942 943 if (stat & 0x00000008) { 944 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); 945 nv_error(gr, "GPC%d/ESETUP: 0x%08x\n", gpc, trap); 946 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); 947 stat &= ~0x00000009; 948 } 949 950 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { 951 u32 mask = 0x00010000 << tpc; 952 if (stat & mask) { 953 gf100_gr_trap_tpc(gr, gpc, tpc); 954 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); 955 stat &= ~mask; 956 } 957 } 958 959 if (stat) { 960 nv_error(gr, "GPC%d/0x%08x: unknown\n", gpc, stat); 961 } 962 } 963 964 static void 965 gf100_gr_trap_intr(struct gf100_gr *gr) 966 { 967 struct nvkm_device *device = gr->base.engine.subdev.device; 968 u32 trap = nvkm_rd32(device, 0x400108); 969 int rop, gpc, i; 970 971 if (trap & 0x00000001) { 972 u32 stat = nvkm_rd32(device, 0x404000); 973 nv_error(gr, "DISPATCH 0x%08x\n", stat); 974 nvkm_wr32(device, 0x404000, 0xc0000000); 975 nvkm_wr32(device, 0x400108, 0x00000001); 976 trap &= ~0x00000001; 977 } 978 979 if (trap & 0x00000002) { 980 u32 stat = nvkm_rd32(device, 0x404600); 981 nv_error(gr, "M2MF 0x%08x\n", stat); 982 nvkm_wr32(device, 0x404600, 0xc0000000); 983 nvkm_wr32(device, 0x400108, 0x00000002); 984 trap &= ~0x00000002; 985 } 986 987 if (trap & 0x00000008) { 988 u32 stat = nvkm_rd32(device, 0x408030); 989 nv_error(gr, "CCACHE 0x%08x\n", stat); 990 nvkm_wr32(device, 0x408030, 0xc0000000); 991 nvkm_wr32(device, 0x400108, 0x00000008); 992 trap &= ~0x00000008; 993 } 994 995 if (trap & 0x00000010) { 996 u32 stat = nvkm_rd32(device, 0x405840); 997 nv_error(gr, "SHADER 0x%08x\n", stat); 998 nvkm_wr32(device, 0x405840, 0xc0000000); 999 nvkm_wr32(device, 0x400108, 0x00000010); 1000 trap &= ~0x00000010; 1001 } 1002 1003 if (trap & 0x00000040) { 1004 u32 stat = nvkm_rd32(device, 0x40601c); 1005 nv_error(gr, "UNK6 0x%08x\n", stat); 1006 nvkm_wr32(device, 0x40601c, 0xc0000000); 1007 nvkm_wr32(device, 0x400108, 0x00000040); 1008 trap &= ~0x00000040; 1009 } 1010 1011 if (trap & 0x00000080) { 1012 u32 stat = nvkm_rd32(device, 0x404490); 1013 nv_error(gr, "MACRO 0x%08x\n", stat); 1014 nvkm_wr32(device, 0x404490, 0xc0000000); 1015 nvkm_wr32(device, 0x400108, 0x00000080); 1016 trap &= ~0x00000080; 1017 } 1018 1019 if (trap & 0x00000100) { 1020 u32 stat = nvkm_rd32(device, 0x407020); 1021 1022 nv_error(gr, "SKED:"); 1023 for (i = 0; i <= 29; ++i) { 1024 if (!(stat & (1 << i))) 1025 continue; 1026 pr_cont(" "); 1027 nvkm_enum_print(gk104_sked_error, i); 1028 } 1029 pr_cont("\n"); 1030 1031 if (stat & 0x3fffffff) 1032 nvkm_wr32(device, 0x407020, 0x40000000); 1033 nvkm_wr32(device, 0x400108, 0x00000100); 1034 trap &= ~0x00000100; 1035 } 1036 1037 if (trap & 0x01000000) { 1038 u32 stat = nvkm_rd32(device, 0x400118); 1039 for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { 1040 u32 mask = 0x00000001 << gpc; 1041 if (stat & mask) { 1042 gf100_gr_trap_gpc(gr, gpc); 1043 nvkm_wr32(device, 0x400118, mask); 1044 stat &= ~mask; 1045 } 1046 } 1047 nvkm_wr32(device, 0x400108, 0x01000000); 1048 trap &= ~0x01000000; 1049 } 1050 1051 if (trap & 0x02000000) { 1052 for (rop = 0; rop < gr->rop_nr; rop++) { 1053 u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); 1054 u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); 1055 nv_error(gr, "ROP%d 0x%08x 0x%08x\n", 1056 rop, statz, statc); 1057 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); 1058 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); 1059 } 1060 nvkm_wr32(device, 0x400108, 0x02000000); 1061 trap &= ~0x02000000; 1062 } 1063 1064 if (trap) { 1065 nv_error(gr, "TRAP UNHANDLED 0x%08x\n", trap); 1066 nvkm_wr32(device, 0x400108, trap); 1067 } 1068 } 1069 1070 static void 1071 gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) 1072 { 1073 struct nvkm_device *device = gr->base.engine.subdev.device; 1074 nv_error(gr, "%06x - done 0x%08x\n", base, 1075 nvkm_rd32(device, base + 0x400)); 1076 nv_error(gr, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, 1077 nvkm_rd32(device, base + 0x800), nvkm_rd32(device, base + 0x804), 1078 nvkm_rd32(device, base + 0x808), nvkm_rd32(device, base + 0x80c)); 1079 nv_error(gr, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, 1080 nvkm_rd32(device, base + 0x810), nvkm_rd32(device, base + 0x814), 1081 nvkm_rd32(device, base + 0x818), nvkm_rd32(device, base + 0x81c)); 1082 } 1083 1084 void 1085 gf100_gr_ctxctl_debug(struct gf100_gr *gr) 1086 { 1087 struct nvkm_device *device = gr->base.engine.subdev.device; 1088 u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff; 1089 u32 gpc; 1090 1091 gf100_gr_ctxctl_debug_unit(gr, 0x409000); 1092 for (gpc = 0; gpc < gpcnr; gpc++) 1093 gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000)); 1094 } 1095 1096 static void 1097 gf100_gr_ctxctl_isr(struct gf100_gr *gr) 1098 { 1099 struct nvkm_device *device = gr->base.engine.subdev.device; 1100 u32 stat = nvkm_rd32(device, 0x409c18); 1101 1102 if (stat & 0x00000001) { 1103 u32 code = nvkm_rd32(device, 0x409814); 1104 if (code == E_BAD_FWMTHD) { 1105 u32 class = nvkm_rd32(device, 0x409808); 1106 u32 addr = nvkm_rd32(device, 0x40980c); 1107 u32 subc = (addr & 0x00070000) >> 16; 1108 u32 mthd = (addr & 0x00003ffc); 1109 u32 data = nvkm_rd32(device, 0x409810); 1110 1111 nv_error(gr, "FECS MTHD subc %d class 0x%04x " 1112 "mthd 0x%04x data 0x%08x\n", 1113 subc, class, mthd, data); 1114 1115 nvkm_wr32(device, 0x409c20, 0x00000001); 1116 stat &= ~0x00000001; 1117 } else { 1118 nv_error(gr, "FECS ucode error %d\n", code); 1119 } 1120 } 1121 1122 if (stat & 0x00080000) { 1123 nv_error(gr, "FECS watchdog timeout\n"); 1124 gf100_gr_ctxctl_debug(gr); 1125 nvkm_wr32(device, 0x409c20, 0x00080000); 1126 stat &= ~0x00080000; 1127 } 1128 1129 if (stat) { 1130 nv_error(gr, "FECS 0x%08x\n", stat); 1131 gf100_gr_ctxctl_debug(gr); 1132 nvkm_wr32(device, 0x409c20, stat); 1133 } 1134 } 1135 1136 static void 1137 gf100_gr_intr(struct nvkm_subdev *subdev) 1138 { 1139 struct gf100_gr *gr = (void *)subdev; 1140 struct nvkm_device *device = gr->base.engine.subdev.device; 1141 struct nvkm_fifo *fifo = device->fifo; 1142 struct nvkm_engine *engine = nv_engine(subdev); 1143 struct nvkm_object *engctx; 1144 struct nvkm_handle *handle; 1145 u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; 1146 u32 stat = nvkm_rd32(device, 0x400100); 1147 u32 addr = nvkm_rd32(device, 0x400704); 1148 u32 mthd = (addr & 0x00003ffc); 1149 u32 subc = (addr & 0x00070000) >> 16; 1150 u32 data = nvkm_rd32(device, 0x400708); 1151 u32 code = nvkm_rd32(device, 0x400110); 1152 u32 class; 1153 int chid; 1154 1155 if (nv_device(gr)->card_type < NV_E0 || subc < 4) 1156 class = nvkm_rd32(device, 0x404200 + (subc * 4)); 1157 else 1158 class = 0x0000; 1159 1160 engctx = nvkm_engctx_get(engine, inst); 1161 chid = fifo->chid(fifo, engctx); 1162 1163 if (stat & 0x00000001) { 1164 /* 1165 * notifier interrupt, only needed for cyclestats 1166 * can be safely ignored 1167 */ 1168 nvkm_wr32(device, 0x400100, 0x00000001); 1169 stat &= ~0x00000001; 1170 } 1171 1172 if (stat & 0x00000010) { 1173 handle = nvkm_handle_get_class(engctx, class); 1174 if (!handle || nv_call(handle->object, mthd, data)) { 1175 nv_error(gr, 1176 "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", 1177 chid, inst << 12, nvkm_client_name(engctx), 1178 subc, class, mthd, data); 1179 } 1180 nvkm_handle_put(handle); 1181 nvkm_wr32(device, 0x400100, 0x00000010); 1182 stat &= ~0x00000010; 1183 } 1184 1185 if (stat & 0x00000020) { 1186 nv_error(gr, 1187 "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", 1188 chid, inst << 12, nvkm_client_name(engctx), subc, 1189 class, mthd, data); 1190 nvkm_wr32(device, 0x400100, 0x00000020); 1191 stat &= ~0x00000020; 1192 } 1193 1194 if (stat & 0x00100000) { 1195 nv_error(gr, "DATA_ERROR ["); 1196 nvkm_enum_print(nv50_data_error_names, code); 1197 pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", 1198 chid, inst << 12, nvkm_client_name(engctx), subc, 1199 class, mthd, data); 1200 nvkm_wr32(device, 0x400100, 0x00100000); 1201 stat &= ~0x00100000; 1202 } 1203 1204 if (stat & 0x00200000) { 1205 nv_error(gr, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12, 1206 nvkm_client_name(engctx)); 1207 gf100_gr_trap_intr(gr); 1208 nvkm_wr32(device, 0x400100, 0x00200000); 1209 stat &= ~0x00200000; 1210 } 1211 1212 if (stat & 0x00080000) { 1213 gf100_gr_ctxctl_isr(gr); 1214 nvkm_wr32(device, 0x400100, 0x00080000); 1215 stat &= ~0x00080000; 1216 } 1217 1218 if (stat) { 1219 nv_error(gr, "unknown stat 0x%08x\n", stat); 1220 nvkm_wr32(device, 0x400100, stat); 1221 } 1222 1223 nvkm_wr32(device, 0x400500, 0x00010001); 1224 nvkm_engctx_put(engctx); 1225 } 1226 1227 void 1228 gf100_gr_init_fw(struct gf100_gr *gr, u32 fuc_base, 1229 struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) 1230 { 1231 struct nvkm_device *device = gr->base.engine.subdev.device; 1232 int i; 1233 1234 nvkm_wr32(device, fuc_base + 0x01c0, 0x01000000); 1235 for (i = 0; i < data->size / 4; i++) 1236 nvkm_wr32(device, fuc_base + 0x01c4, data->data[i]); 1237 1238 nvkm_wr32(device, fuc_base + 0x0180, 0x01000000); 1239 for (i = 0; i < code->size / 4; i++) { 1240 if ((i & 0x3f) == 0) 1241 nvkm_wr32(device, fuc_base + 0x0188, i >> 6); 1242 nvkm_wr32(device, fuc_base + 0x0184, code->data[i]); 1243 } 1244 1245 /* code must be padded to 0x40 words */ 1246 for (; i & 0x3f; i++) 1247 nvkm_wr32(device, fuc_base + 0x0184, 0); 1248 } 1249 1250 static void 1251 gf100_gr_init_csdata(struct gf100_gr *gr, 1252 const struct gf100_gr_pack *pack, 1253 u32 falcon, u32 starstar, u32 base) 1254 { 1255 struct nvkm_device *device = gr->base.engine.subdev.device; 1256 const struct gf100_gr_pack *iter; 1257 const struct gf100_gr_init *init; 1258 u32 addr = ~0, prev = ~0, xfer = 0; 1259 u32 star, temp; 1260 1261 nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar); 1262 star = nvkm_rd32(device, falcon + 0x01c4); 1263 temp = nvkm_rd32(device, falcon + 0x01c4); 1264 if (temp > star) 1265 star = temp; 1266 nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star); 1267 1268 pack_for_each_init(init, iter, pack) { 1269 u32 head = init->addr - base; 1270 u32 tail = head + init->count * init->pitch; 1271 while (head < tail) { 1272 if (head != prev + 4 || xfer >= 32) { 1273 if (xfer) { 1274 u32 data = ((--xfer << 26) | addr); 1275 nvkm_wr32(device, falcon + 0x01c4, data); 1276 star += 4; 1277 } 1278 addr = head; 1279 xfer = 0; 1280 } 1281 prev = head; 1282 xfer = xfer + 1; 1283 head = head + init->pitch; 1284 } 1285 } 1286 1287 nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr); 1288 nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar); 1289 nvkm_wr32(device, falcon + 0x01c4, star + 4); 1290 } 1291 1292 int 1293 gf100_gr_init_ctxctl(struct gf100_gr *gr) 1294 { 1295 struct nvkm_device *device = gr->base.engine.subdev.device; 1296 struct gf100_gr_oclass *oclass = (void *)nv_object(gr)->oclass; 1297 struct gf100_grctx_oclass *cclass = (void *)nv_engine(gr)->cclass; 1298 int i; 1299 1300 if (gr->firmware) { 1301 /* load fuc microcode */ 1302 nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); 1303 gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, 1304 &gr->fuc409d); 1305 gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, 1306 &gr->fuc41ad); 1307 nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); 1308 1309 /* start both of them running */ 1310 nvkm_wr32(device, 0x409840, 0xffffffff); 1311 nvkm_wr32(device, 0x41a10c, 0x00000000); 1312 nvkm_wr32(device, 0x40910c, 0x00000000); 1313 nvkm_wr32(device, 0x41a100, 0x00000002); 1314 nvkm_wr32(device, 0x409100, 0x00000002); 1315 if (!nv_wait(gr, 0x409800, 0x00000001, 0x00000001)) 1316 nv_warn(gr, "0x409800 wait failed\n"); 1317 1318 nvkm_wr32(device, 0x409840, 0xffffffff); 1319 nvkm_wr32(device, 0x409500, 0x7fffffff); 1320 nvkm_wr32(device, 0x409504, 0x00000021); 1321 1322 nvkm_wr32(device, 0x409840, 0xffffffff); 1323 nvkm_wr32(device, 0x409500, 0x00000000); 1324 nvkm_wr32(device, 0x409504, 0x00000010); 1325 if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { 1326 nv_error(gr, "fuc09 req 0x10 timeout\n"); 1327 return -EBUSY; 1328 } 1329 gr->size = nvkm_rd32(device, 0x409800); 1330 1331 nvkm_wr32(device, 0x409840, 0xffffffff); 1332 nvkm_wr32(device, 0x409500, 0x00000000); 1333 nvkm_wr32(device, 0x409504, 0x00000016); 1334 if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { 1335 nv_error(gr, "fuc09 req 0x16 timeout\n"); 1336 return -EBUSY; 1337 } 1338 1339 nvkm_wr32(device, 0x409840, 0xffffffff); 1340 nvkm_wr32(device, 0x409500, 0x00000000); 1341 nvkm_wr32(device, 0x409504, 0x00000025); 1342 if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { 1343 nv_error(gr, "fuc09 req 0x25 timeout\n"); 1344 return -EBUSY; 1345 } 1346 1347 if (nv_device(gr)->chipset >= 0xe0) { 1348 nvkm_wr32(device, 0x409800, 0x00000000); 1349 nvkm_wr32(device, 0x409500, 0x00000001); 1350 nvkm_wr32(device, 0x409504, 0x00000030); 1351 if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { 1352 nv_error(gr, "fuc09 req 0x30 timeout\n"); 1353 return -EBUSY; 1354 } 1355 1356 nvkm_wr32(device, 0x409810, 0xb00095c8); 1357 nvkm_wr32(device, 0x409800, 0x00000000); 1358 nvkm_wr32(device, 0x409500, 0x00000001); 1359 nvkm_wr32(device, 0x409504, 0x00000031); 1360 if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { 1361 nv_error(gr, "fuc09 req 0x31 timeout\n"); 1362 return -EBUSY; 1363 } 1364 1365 nvkm_wr32(device, 0x409810, 0x00080420); 1366 nvkm_wr32(device, 0x409800, 0x00000000); 1367 nvkm_wr32(device, 0x409500, 0x00000001); 1368 nvkm_wr32(device, 0x409504, 0x00000032); 1369 if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { 1370 nv_error(gr, "fuc09 req 0x32 timeout\n"); 1371 return -EBUSY; 1372 } 1373 1374 nvkm_wr32(device, 0x409614, 0x00000070); 1375 nvkm_wr32(device, 0x409614, 0x00000770); 1376 nvkm_wr32(device, 0x40802c, 0x00000001); 1377 } 1378 1379 if (gr->data == NULL) { 1380 int ret = gf100_grctx_generate(gr); 1381 if (ret) { 1382 nv_error(gr, "failed to construct context\n"); 1383 return ret; 1384 } 1385 } 1386 1387 return 0; 1388 } else 1389 if (!oclass->fecs.ucode) { 1390 return -ENOSYS; 1391 } 1392 1393 /* load HUB microcode */ 1394 nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); 1395 nvkm_wr32(device, 0x4091c0, 0x01000000); 1396 for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) 1397 nvkm_wr32(device, 0x4091c4, oclass->fecs.ucode->data.data[i]); 1398 1399 nvkm_wr32(device, 0x409180, 0x01000000); 1400 for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) { 1401 if ((i & 0x3f) == 0) 1402 nvkm_wr32(device, 0x409188, i >> 6); 1403 nvkm_wr32(device, 0x409184, oclass->fecs.ucode->code.data[i]); 1404 } 1405 1406 /* load GPC microcode */ 1407 nvkm_wr32(device, 0x41a1c0, 0x01000000); 1408 for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++) 1409 nvkm_wr32(device, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); 1410 1411 nvkm_wr32(device, 0x41a180, 0x01000000); 1412 for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) { 1413 if ((i & 0x3f) == 0) 1414 nvkm_wr32(device, 0x41a188, i >> 6); 1415 nvkm_wr32(device, 0x41a184, oclass->gpccs.ucode->code.data[i]); 1416 } 1417 nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); 1418 1419 /* load register lists */ 1420 gf100_gr_init_csdata(gr, cclass->hub, 0x409000, 0x000, 0x000000); 1421 gf100_gr_init_csdata(gr, cclass->gpc, 0x41a000, 0x000, 0x418000); 1422 gf100_gr_init_csdata(gr, cclass->tpc, 0x41a000, 0x004, 0x419800); 1423 gf100_gr_init_csdata(gr, cclass->ppc, 0x41a000, 0x008, 0x41be00); 1424 1425 /* start HUB ucode running, it'll init the GPCs */ 1426 nvkm_wr32(device, 0x40910c, 0x00000000); 1427 nvkm_wr32(device, 0x409100, 0x00000002); 1428 if (!nv_wait(gr, 0x409800, 0x80000000, 0x80000000)) { 1429 nv_error(gr, "HUB_INIT timed out\n"); 1430 gf100_gr_ctxctl_debug(gr); 1431 return -EBUSY; 1432 } 1433 1434 gr->size = nvkm_rd32(device, 0x409804); 1435 if (gr->data == NULL) { 1436 int ret = gf100_grctx_generate(gr); 1437 if (ret) { 1438 nv_error(gr, "failed to construct context\n"); 1439 return ret; 1440 } 1441 } 1442 1443 return 0; 1444 } 1445 1446 int 1447 gf100_gr_init(struct nvkm_object *object) 1448 { 1449 struct gf100_gr *gr = (void *)object; 1450 struct nvkm_device *device = gr->base.engine.subdev.device; 1451 struct gf100_gr_oclass *oclass = (void *)object->oclass; 1452 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); 1453 u32 data[TPC_MAX / 8] = {}; 1454 u8 tpcnr[GPC_MAX]; 1455 int gpc, tpc, rop; 1456 int ret, i; 1457 1458 ret = nvkm_gr_init(&gr->base); 1459 if (ret) 1460 return ret; 1461 1462 nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); 1463 nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000); 1464 nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000); 1465 nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000); 1466 nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); 1467 nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); 1468 nvkm_wr32(device, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8); 1469 nvkm_wr32(device, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8); 1470 1471 gf100_gr_mmio(gr, oclass->mmio); 1472 1473 memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); 1474 for (i = 0, gpc = -1; i < gr->tpc_total; i++) { 1475 do { 1476 gpc = (gpc + 1) % gr->gpc_nr; 1477 } while (!tpcnr[gpc]); 1478 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; 1479 1480 data[i / 8] |= tpc << ((i % 8) * 4); 1481 } 1482 1483 nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); 1484 nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); 1485 nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); 1486 nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); 1487 1488 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 1489 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), 1490 gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); 1491 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | 1492 gr->tpc_total); 1493 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); 1494 } 1495 1496 if (nv_device(gr)->chipset != 0xd7) 1497 nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); 1498 else 1499 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); 1500 1501 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); 1502 1503 nvkm_wr32(device, 0x400500, 0x00010001); 1504 1505 nvkm_wr32(device, 0x400100, 0xffffffff); 1506 nvkm_wr32(device, 0x40013c, 0xffffffff); 1507 1508 nvkm_wr32(device, 0x409c24, 0x000f0000); 1509 nvkm_wr32(device, 0x404000, 0xc0000000); 1510 nvkm_wr32(device, 0x404600, 0xc0000000); 1511 nvkm_wr32(device, 0x408030, 0xc0000000); 1512 nvkm_wr32(device, 0x40601c, 0xc0000000); 1513 nvkm_wr32(device, 0x404490, 0xc0000000); 1514 nvkm_wr32(device, 0x406018, 0xc0000000); 1515 nvkm_wr32(device, 0x405840, 0xc0000000); 1516 nvkm_wr32(device, 0x405844, 0x00ffffff); 1517 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); 1518 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); 1519 1520 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 1521 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); 1522 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); 1523 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); 1524 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); 1525 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { 1526 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); 1527 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); 1528 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); 1529 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); 1530 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); 1531 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); 1532 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); 1533 } 1534 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); 1535 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); 1536 } 1537 1538 for (rop = 0; rop < gr->rop_nr; rop++) { 1539 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); 1540 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); 1541 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); 1542 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); 1543 } 1544 1545 nvkm_wr32(device, 0x400108, 0xffffffff); 1546 nvkm_wr32(device, 0x400138, 0xffffffff); 1547 nvkm_wr32(device, 0x400118, 0xffffffff); 1548 nvkm_wr32(device, 0x400130, 0xffffffff); 1549 nvkm_wr32(device, 0x40011c, 0xffffffff); 1550 nvkm_wr32(device, 0x400134, 0xffffffff); 1551 1552 nvkm_wr32(device, 0x400054, 0x34ce3464); 1553 1554 gf100_gr_zbc_init(gr); 1555 1556 return gf100_gr_init_ctxctl(gr); 1557 } 1558 1559 void 1560 gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) 1561 { 1562 kfree(fuc->data); 1563 fuc->data = NULL; 1564 } 1565 1566 int 1567 gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, 1568 struct gf100_gr_fuc *fuc) 1569 { 1570 struct nvkm_device *device = nv_device(gr); 1571 const struct firmware *fw; 1572 char f[64]; 1573 char cname[16]; 1574 int ret; 1575 int i; 1576 1577 /* Convert device name to lowercase */ 1578 strncpy(cname, device->cname, sizeof(cname)); 1579 cname[sizeof(cname) - 1] = '\0'; 1580 i = strlen(cname); 1581 while (i) { 1582 --i; 1583 cname[i] = tolower(cname[i]); 1584 } 1585 1586 snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); 1587 ret = request_firmware(&fw, f, nv_device_base(device)); 1588 if (ret) { 1589 nv_error(gr, "failed to load %s\n", fwname); 1590 return ret; 1591 } 1592 1593 fuc->size = fw->size; 1594 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); 1595 release_firmware(fw); 1596 return (fuc->data != NULL) ? 0 : -ENOMEM; 1597 } 1598 1599 void 1600 gf100_gr_dtor(struct nvkm_object *object) 1601 { 1602 struct gf100_gr *gr = (void *)object; 1603 1604 kfree(gr->data); 1605 1606 gf100_gr_dtor_fw(&gr->fuc409c); 1607 gf100_gr_dtor_fw(&gr->fuc409d); 1608 gf100_gr_dtor_fw(&gr->fuc41ac); 1609 gf100_gr_dtor_fw(&gr->fuc41ad); 1610 1611 nvkm_gpuobj_ref(NULL, &gr->unk4188b8); 1612 nvkm_gpuobj_ref(NULL, &gr->unk4188b4); 1613 1614 nvkm_gr_destroy(&gr->base); 1615 } 1616 1617 int 1618 gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 1619 struct nvkm_oclass *bclass, void *data, u32 size, 1620 struct nvkm_object **pobject) 1621 { 1622 struct gf100_gr_oclass *oclass = (void *)bclass; 1623 struct nvkm_device *device = nv_device(parent); 1624 struct gf100_gr *gr; 1625 bool use_ext_fw, enable; 1626 int ret, i, j; 1627 1628 use_ext_fw = nvkm_boolopt(device->cfgopt, "NvGrUseFW", 1629 oclass->fecs.ucode == NULL); 1630 enable = use_ext_fw || oclass->fecs.ucode != NULL; 1631 1632 ret = nvkm_gr_create(parent, engine, bclass, enable, &gr); 1633 *pobject = nv_object(gr); 1634 if (ret) 1635 return ret; 1636 1637 nv_subdev(gr)->unit = 0x08001000; 1638 nv_subdev(gr)->intr = gf100_gr_intr; 1639 1640 gr->base.units = gf100_gr_units; 1641 1642 if (use_ext_fw) { 1643 nv_info(gr, "using external firmware\n"); 1644 if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || 1645 gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || 1646 gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || 1647 gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) 1648 return -ENODEV; 1649 gr->firmware = true; 1650 } 1651 1652 ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x1000, 256, 0, 1653 &gr->unk4188b4); 1654 if (ret) 1655 return ret; 1656 1657 ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x1000, 256, 0, 1658 &gr->unk4188b8); 1659 if (ret) 1660 return ret; 1661 1662 for (i = 0; i < 0x1000; i += 4) { 1663 nv_wo32(gr->unk4188b4, i, 0x00000010); 1664 nv_wo32(gr->unk4188b8, i, 0x00000010); 1665 } 1666 1667 gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; 1668 gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; 1669 for (i = 0; i < gr->gpc_nr; i++) { 1670 gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); 1671 gr->tpc_total += gr->tpc_nr[i]; 1672 gr->ppc_nr[i] = oclass->ppc_nr; 1673 for (j = 0; j < gr->ppc_nr[i]; j++) { 1674 u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); 1675 gr->ppc_tpc_nr[i][j] = hweight8(mask); 1676 } 1677 } 1678 1679 /*XXX: these need figuring out... though it might not even matter */ 1680 switch (nv_device(gr)->chipset) { 1681 case 0xc0: 1682 if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ 1683 gr->magic_not_rop_nr = 0x07; 1684 } else 1685 if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ 1686 gr->magic_not_rop_nr = 0x05; 1687 } else 1688 if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ 1689 gr->magic_not_rop_nr = 0x06; 1690 } 1691 break; 1692 case 0xc3: /* 450, 4/0/0/0, 2 */ 1693 gr->magic_not_rop_nr = 0x03; 1694 break; 1695 case 0xc4: /* 460, 3/4/0/0, 4 */ 1696 gr->magic_not_rop_nr = 0x01; 1697 break; 1698 case 0xc1: /* 2/0/0/0, 1 */ 1699 gr->magic_not_rop_nr = 0x01; 1700 break; 1701 case 0xc8: /* 4/4/3/4, 5 */ 1702 gr->magic_not_rop_nr = 0x06; 1703 break; 1704 case 0xce: /* 4/4/0/0, 4 */ 1705 gr->magic_not_rop_nr = 0x03; 1706 break; 1707 case 0xcf: /* 4/0/0/0, 3 */ 1708 gr->magic_not_rop_nr = 0x03; 1709 break; 1710 case 0xd7: 1711 case 0xd9: /* 1/0/0/0, 1 */ 1712 case 0xea: /* gk20a */ 1713 case 0x12b: /* gm20b */ 1714 gr->magic_not_rop_nr = 0x01; 1715 break; 1716 } 1717 1718 nv_engine(gr)->cclass = *oclass->cclass; 1719 nv_engine(gr)->sclass = oclass->sclass; 1720 return 0; 1721 } 1722 1723 #include "fuc/hubgf100.fuc3.h" 1724 1725 struct gf100_gr_ucode 1726 gf100_gr_fecs_ucode = { 1727 .code.data = gf100_grhub_code, 1728 .code.size = sizeof(gf100_grhub_code), 1729 .data.data = gf100_grhub_data, 1730 .data.size = sizeof(gf100_grhub_data), 1731 }; 1732 1733 #include "fuc/gpcgf100.fuc3.h" 1734 1735 struct gf100_gr_ucode 1736 gf100_gr_gpccs_ucode = { 1737 .code.data = gf100_grgpc_code, 1738 .code.size = sizeof(gf100_grgpc_code), 1739 .data.data = gf100_grgpc_data, 1740 .data.size = sizeof(gf100_grgpc_data), 1741 }; 1742 1743 struct nvkm_oclass * 1744 gf100_gr_oclass = &(struct gf100_gr_oclass) { 1745 .base.handle = NV_ENGINE(GR, 0xc0), 1746 .base.ofuncs = &(struct nvkm_ofuncs) { 1747 .ctor = gf100_gr_ctor, 1748 .dtor = gf100_gr_dtor, 1749 .init = gf100_gr_init, 1750 .fini = _nvkm_gr_fini, 1751 }, 1752 .cclass = &gf100_grctx_oclass, 1753 .sclass = gf100_gr_sclass, 1754 .mmio = gf100_gr_pack_mmio, 1755 .fecs.ucode = &gf100_gr_fecs_ucode, 1756 .gpccs.ucode = &gf100_gr_gpccs_ucode, 1757 }.base; 1758