1 /* 2 * Copyright 2009 Marcin Kościelnicki 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <core/device.h> 24 #include <core/gpuobj.h> 25 26 #define CP_FLAG_CLEAR 0 27 #define CP_FLAG_SET 1 28 #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) 29 #define CP_FLAG_SWAP_DIRECTION_LOAD 0 30 #define CP_FLAG_SWAP_DIRECTION_SAVE 1 31 #define CP_FLAG_UNK01 ((0 * 32) + 1) 32 #define CP_FLAG_UNK01_CLEAR 0 33 #define CP_FLAG_UNK01_SET 1 34 #define CP_FLAG_UNK03 ((0 * 32) + 3) 35 #define CP_FLAG_UNK03_CLEAR 0 36 #define CP_FLAG_UNK03_SET 1 37 #define CP_FLAG_USER_SAVE ((0 * 32) + 5) 38 #define CP_FLAG_USER_SAVE_NOT_PENDING 0 39 #define CP_FLAG_USER_SAVE_PENDING 1 40 #define CP_FLAG_USER_LOAD ((0 * 32) + 6) 41 #define CP_FLAG_USER_LOAD_NOT_PENDING 0 42 #define CP_FLAG_USER_LOAD_PENDING 1 43 #define CP_FLAG_UNK0B ((0 * 32) + 0xb) 44 #define CP_FLAG_UNK0B_CLEAR 0 45 #define CP_FLAG_UNK0B_SET 1 46 #define CP_FLAG_XFER_SWITCH ((0 * 32) + 0xe) 47 #define CP_FLAG_XFER_SWITCH_DISABLE 0 48 #define CP_FLAG_XFER_SWITCH_ENABLE 1 49 #define CP_FLAG_STATE ((0 * 32) + 0x1c) 50 #define CP_FLAG_STATE_STOPPED 0 51 #define CP_FLAG_STATE_RUNNING 1 52 #define CP_FLAG_UNK1D ((0 * 32) + 0x1d) 53 #define CP_FLAG_UNK1D_CLEAR 0 54 #define CP_FLAG_UNK1D_SET 1 55 #define CP_FLAG_UNK20 ((1 * 32) + 0) 56 #define CP_FLAG_UNK20_CLEAR 0 57 #define CP_FLAG_UNK20_SET 1 58 #define CP_FLAG_STATUS ((2 * 32) + 0) 59 #define CP_FLAG_STATUS_BUSY 0 60 #define CP_FLAG_STATUS_IDLE 1 61 #define CP_FLAG_AUTO_SAVE ((2 * 32) + 4) 62 #define CP_FLAG_AUTO_SAVE_NOT_PENDING 0 63 #define CP_FLAG_AUTO_SAVE_PENDING 1 64 #define CP_FLAG_AUTO_LOAD ((2 * 32) + 5) 65 #define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 66 #define CP_FLAG_AUTO_LOAD_PENDING 1 67 #define CP_FLAG_NEWCTX ((2 * 32) + 10) 68 #define CP_FLAG_NEWCTX_BUSY 0 69 #define CP_FLAG_NEWCTX_DONE 1 70 #define CP_FLAG_XFER ((2 * 32) + 11) 71 #define CP_FLAG_XFER_IDLE 0 72 #define CP_FLAG_XFER_BUSY 1 73 #define CP_FLAG_ALWAYS ((2 * 32) + 13) 74 #define CP_FLAG_ALWAYS_FALSE 0 75 #define CP_FLAG_ALWAYS_TRUE 1 76 #define CP_FLAG_INTR ((2 * 32) + 15) 77 #define CP_FLAG_INTR_NOT_PENDING 0 78 #define CP_FLAG_INTR_PENDING 1 79 80 #define CP_CTX 0x00100000 81 #define CP_CTX_COUNT 0x000f0000 82 #define CP_CTX_COUNT_SHIFT 16 83 #define CP_CTX_REG 0x00003fff 84 #define CP_LOAD_SR 0x00200000 85 #define CP_LOAD_SR_VALUE 0x000fffff 86 #define CP_BRA 0x00400000 87 #define CP_BRA_IP 0x0001ff00 88 #define CP_BRA_IP_SHIFT 8 89 #define CP_BRA_IF_CLEAR 0x00000080 90 #define CP_BRA_FLAG 0x0000007f 91 #define CP_WAIT 0x00500000 92 #define CP_WAIT_SET 0x00000080 93 #define CP_WAIT_FLAG 0x0000007f 94 #define CP_SET 0x00700000 95 #define CP_SET_1 0x00000080 96 #define CP_SET_FLAG 0x0000007f 97 #define CP_NEWCTX 0x00600004 98 #define CP_NEXT_TO_SWAP 0x00600005 99 #define CP_SET_CONTEXT_POINTER 0x00600006 100 #define CP_SET_XFER_POINTER 0x00600007 101 #define CP_ENABLE 0x00600009 102 #define CP_END 0x0060000c 103 #define CP_NEXT_TO_CURRENT 0x0060000d 104 #define CP_DISABLE1 0x0090ffff 105 #define CP_DISABLE2 0x0091ffff 106 #define CP_XFER_1 0x008000ff 107 #define CP_XFER_2 0x008800ff 108 #define CP_SEEK_1 0x00c000ff 109 #define CP_SEEK_2 0x00c800ff 110 111 #include "nv50.h" 112 #include "ctx.h" 113 114 #define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf) 115 #define IS_NVAAF(x) ((x) >= 0xaa && (x) <= 0xac) 116 117 #include <subdev/fb.h> 118 119 /* 120 * This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's 121 * the GPU itself that does context-switching, but it needs a special 122 * microcode to do it. And it's the driver's task to supply this microcode, 123 * further known as ctxprog, as well as the initial context values, known 124 * as ctxvals. 125 * 126 * Without ctxprog, you cannot switch contexts. Not even in software, since 127 * the majority of context [xfer strands] isn't accessible directly. You're 128 * stuck with a single channel, and you also suffer all the problems resulting 129 * from missing ctxvals, since you cannot load them. 130 * 131 * Without ctxvals, you're stuck with PGRAPH's default context. It's enough to 132 * run 2d operations, but trying to utilise 3d or CUDA will just lock you up, 133 * since you don't have... some sort of needed setup. 134 * 135 * Nouveau will just disable acceleration if not given ctxprog + ctxvals, since 136 * it's too much hassle to handle no-ctxprog as a special case. 137 */ 138 139 /* 140 * How ctxprogs work. 141 * 142 * The ctxprog is written in its own kind of microcode, with very small and 143 * crappy set of available commands. You upload it to a small [512 insns] 144 * area of memory on PGRAPH, and it'll be run when PFIFO wants PGRAPH to 145 * switch channel. or when the driver explicitely requests it. Stuff visible 146 * to ctxprog consists of: PGRAPH MMIO registers, PGRAPH context strands, 147 * the per-channel context save area in VRAM [known as ctxvals or grctx], 148 * 4 flags registers, a scratch register, two grctx pointers, plus many 149 * random poorly-understood details. 150 * 151 * When ctxprog runs, it's supposed to check what operations are asked of it, 152 * save old context if requested, optionally reset PGRAPH and switch to the 153 * new channel, and load the new context. Context consists of three major 154 * parts: subset of MMIO registers and two "xfer areas". 155 */ 156 157 /* TODO: 158 * - document unimplemented bits compared to nvidia 159 * - NVAx: make a TP subroutine, use it. 160 * - use 0x4008fc instead of 0x1540? 161 */ 162 163 enum cp_label { 164 cp_check_load = 1, 165 cp_setup_auto_load, 166 cp_setup_load, 167 cp_setup_save, 168 cp_swap_state, 169 cp_prepare_exit, 170 cp_exit, 171 }; 172 173 static void nv50_gr_construct_mmio(struct nouveau_grctx *ctx); 174 static void nv50_gr_construct_xfer1(struct nouveau_grctx *ctx); 175 static void nv50_gr_construct_xfer2(struct nouveau_grctx *ctx); 176 177 /* Main function: construct the ctxprog skeleton, call the other functions. */ 178 179 static int 180 nv50_grctx_generate(struct nouveau_grctx *ctx) 181 { 182 cp_set (ctx, STATE, RUNNING); 183 cp_set (ctx, XFER_SWITCH, ENABLE); 184 /* decide whether we're loading/unloading the context */ 185 cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); 186 cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); 187 188 cp_name(ctx, cp_check_load); 189 cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); 190 cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); 191 cp_bra (ctx, ALWAYS, TRUE, cp_prepare_exit); 192 193 /* setup for context load */ 194 cp_name(ctx, cp_setup_auto_load); 195 cp_out (ctx, CP_DISABLE1); 196 cp_out (ctx, CP_DISABLE2); 197 cp_out (ctx, CP_ENABLE); 198 cp_out (ctx, CP_NEXT_TO_SWAP); 199 cp_set (ctx, UNK01, SET); 200 cp_name(ctx, cp_setup_load); 201 cp_out (ctx, CP_NEWCTX); 202 cp_wait(ctx, NEWCTX, BUSY); 203 cp_set (ctx, UNK1D, CLEAR); 204 cp_set (ctx, SWAP_DIRECTION, LOAD); 205 cp_bra (ctx, UNK0B, SET, cp_prepare_exit); 206 cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); 207 208 /* setup for context save */ 209 cp_name(ctx, cp_setup_save); 210 cp_set (ctx, UNK1D, SET); 211 cp_wait(ctx, STATUS, BUSY); 212 cp_wait(ctx, INTR, PENDING); 213 cp_bra (ctx, STATUS, BUSY, cp_setup_save); 214 cp_set (ctx, UNK01, SET); 215 cp_set (ctx, SWAP_DIRECTION, SAVE); 216 217 /* general PGRAPH state */ 218 cp_name(ctx, cp_swap_state); 219 cp_set (ctx, UNK03, SET); 220 cp_pos (ctx, 0x00004/4); 221 cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */ 222 cp_pos (ctx, 0x00100/4); 223 nv50_gr_construct_mmio(ctx); 224 nv50_gr_construct_xfer1(ctx); 225 nv50_gr_construct_xfer2(ctx); 226 227 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); 228 229 cp_set (ctx, UNK20, SET); 230 cp_set (ctx, SWAP_DIRECTION, SAVE); /* no idea why this is needed, but fixes at least one lockup. */ 231 cp_lsr (ctx, ctx->ctxvals_base); 232 cp_out (ctx, CP_SET_XFER_POINTER); 233 cp_lsr (ctx, 4); 234 cp_out (ctx, CP_SEEK_1); 235 cp_out (ctx, CP_XFER_1); 236 cp_wait(ctx, XFER, BUSY); 237 238 /* pre-exit state updates */ 239 cp_name(ctx, cp_prepare_exit); 240 cp_set (ctx, UNK01, CLEAR); 241 cp_set (ctx, UNK03, CLEAR); 242 cp_set (ctx, UNK1D, CLEAR); 243 244 cp_bra (ctx, USER_SAVE, PENDING, cp_exit); 245 cp_out (ctx, CP_NEXT_TO_CURRENT); 246 247 cp_name(ctx, cp_exit); 248 cp_set (ctx, USER_SAVE, NOT_PENDING); 249 cp_set (ctx, USER_LOAD, NOT_PENDING); 250 cp_set (ctx, XFER_SWITCH, DISABLE); 251 cp_set (ctx, STATE, STOPPED); 252 cp_out (ctx, CP_END); 253 ctx->ctxvals_pos += 0x400; /* padding... no idea why you need it */ 254 255 return 0; 256 } 257 258 void 259 nv50_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem) 260 { 261 nv50_grctx_generate(&(struct nouveau_grctx) { 262 .device = device, 263 .mode = NOUVEAU_GRCTX_VALS, 264 .data = mem, 265 }); 266 } 267 268 int 269 nv50_grctx_init(struct nouveau_device *device, u32 *size) 270 { 271 u32 *ctxprog = kmalloc(512 * 4, GFP_KERNEL), i; 272 struct nouveau_grctx ctx = { 273 .device = device, 274 .mode = NOUVEAU_GRCTX_PROG, 275 .data = ctxprog, 276 .ctxprog_max = 512, 277 }; 278 279 if (!ctxprog) 280 return -ENOMEM; 281 nv50_grctx_generate(&ctx); 282 283 nv_wr32(device, 0x400324, 0); 284 for (i = 0; i < ctx.ctxprog_len; i++) 285 nv_wr32(device, 0x400328, ctxprog[i]); 286 *size = ctx.ctxvals_pos * 4; 287 kfree(ctxprog); 288 return 0; 289 } 290 291 /* 292 * Constructs MMIO part of ctxprog and ctxvals. Just a matter of knowing which 293 * registers to save/restore and the default values for them. 294 */ 295 296 static void 297 nv50_gr_construct_mmio_ddata(struct nouveau_grctx *ctx); 298 299 static void 300 nv50_gr_construct_mmio(struct nouveau_grctx *ctx) 301 { 302 struct nouveau_device *device = ctx->device; 303 int i, j; 304 int offset, base; 305 u32 units = nv_rd32 (ctx->device, 0x1540); 306 307 /* 0800: DISPATCH */ 308 cp_ctx(ctx, 0x400808, 7); 309 gr_def(ctx, 0x400814, 0x00000030); 310 cp_ctx(ctx, 0x400834, 0x32); 311 if (device->chipset == 0x50) { 312 gr_def(ctx, 0x400834, 0xff400040); 313 gr_def(ctx, 0x400838, 0xfff00080); 314 gr_def(ctx, 0x40083c, 0xfff70090); 315 gr_def(ctx, 0x400840, 0xffe806a8); 316 } 317 gr_def(ctx, 0x400844, 0x00000002); 318 if (IS_NVA3F(device->chipset)) 319 gr_def(ctx, 0x400894, 0x00001000); 320 gr_def(ctx, 0x4008e8, 0x00000003); 321 gr_def(ctx, 0x4008ec, 0x00001000); 322 if (device->chipset == 0x50) 323 cp_ctx(ctx, 0x400908, 0xb); 324 else if (device->chipset < 0xa0) 325 cp_ctx(ctx, 0x400908, 0xc); 326 else 327 cp_ctx(ctx, 0x400908, 0xe); 328 329 if (device->chipset >= 0xa0) 330 cp_ctx(ctx, 0x400b00, 0x1); 331 if (IS_NVA3F(device->chipset)) { 332 cp_ctx(ctx, 0x400b10, 0x1); 333 gr_def(ctx, 0x400b10, 0x0001629d); 334 cp_ctx(ctx, 0x400b20, 0x1); 335 gr_def(ctx, 0x400b20, 0x0001629d); 336 } 337 338 nv50_gr_construct_mmio_ddata(ctx); 339 340 /* 0C00: VFETCH */ 341 cp_ctx(ctx, 0x400c08, 0x2); 342 gr_def(ctx, 0x400c08, 0x0000fe0c); 343 344 /* 1000 */ 345 if (device->chipset < 0xa0) { 346 cp_ctx(ctx, 0x401008, 0x4); 347 gr_def(ctx, 0x401014, 0x00001000); 348 } else if (!IS_NVA3F(device->chipset)) { 349 cp_ctx(ctx, 0x401008, 0x5); 350 gr_def(ctx, 0x401018, 0x00001000); 351 } else { 352 cp_ctx(ctx, 0x401008, 0x5); 353 gr_def(ctx, 0x401018, 0x00004000); 354 } 355 356 /* 1400 */ 357 cp_ctx(ctx, 0x401400, 0x8); 358 cp_ctx(ctx, 0x401424, 0x3); 359 if (device->chipset == 0x50) 360 gr_def(ctx, 0x40142c, 0x0001fd87); 361 else 362 gr_def(ctx, 0x40142c, 0x00000187); 363 cp_ctx(ctx, 0x401540, 0x5); 364 gr_def(ctx, 0x401550, 0x00001018); 365 366 /* 1800: STREAMOUT */ 367 cp_ctx(ctx, 0x401814, 0x1); 368 gr_def(ctx, 0x401814, 0x000000ff); 369 if (device->chipset == 0x50) { 370 cp_ctx(ctx, 0x40181c, 0xe); 371 gr_def(ctx, 0x401850, 0x00000004); 372 } else if (device->chipset < 0xa0) { 373 cp_ctx(ctx, 0x40181c, 0xf); 374 gr_def(ctx, 0x401854, 0x00000004); 375 } else { 376 cp_ctx(ctx, 0x40181c, 0x13); 377 gr_def(ctx, 0x401864, 0x00000004); 378 } 379 380 /* 1C00 */ 381 cp_ctx(ctx, 0x401c00, 0x1); 382 switch (device->chipset) { 383 case 0x50: 384 gr_def(ctx, 0x401c00, 0x0001005f); 385 break; 386 case 0x84: 387 case 0x86: 388 case 0x94: 389 gr_def(ctx, 0x401c00, 0x044d00df); 390 break; 391 case 0x92: 392 case 0x96: 393 case 0x98: 394 case 0xa0: 395 case 0xaa: 396 case 0xac: 397 gr_def(ctx, 0x401c00, 0x042500df); 398 break; 399 case 0xa3: 400 case 0xa5: 401 case 0xa8: 402 case 0xaf: 403 gr_def(ctx, 0x401c00, 0x142500df); 404 break; 405 } 406 407 /* 2000 */ 408 409 /* 2400 */ 410 cp_ctx(ctx, 0x402400, 0x1); 411 if (device->chipset == 0x50) 412 cp_ctx(ctx, 0x402408, 0x1); 413 else 414 cp_ctx(ctx, 0x402408, 0x2); 415 gr_def(ctx, 0x402408, 0x00000600); 416 417 /* 2800: CSCHED */ 418 cp_ctx(ctx, 0x402800, 0x1); 419 if (device->chipset == 0x50) 420 gr_def(ctx, 0x402800, 0x00000006); 421 422 /* 2C00: ZCULL */ 423 cp_ctx(ctx, 0x402c08, 0x6); 424 if (device->chipset != 0x50) 425 gr_def(ctx, 0x402c14, 0x01000000); 426 gr_def(ctx, 0x402c18, 0x000000ff); 427 if (device->chipset == 0x50) 428 cp_ctx(ctx, 0x402ca0, 0x1); 429 else 430 cp_ctx(ctx, 0x402ca0, 0x2); 431 if (device->chipset < 0xa0) 432 gr_def(ctx, 0x402ca0, 0x00000400); 433 else if (!IS_NVA3F(device->chipset)) 434 gr_def(ctx, 0x402ca0, 0x00000800); 435 else 436 gr_def(ctx, 0x402ca0, 0x00000400); 437 cp_ctx(ctx, 0x402cac, 0x4); 438 439 /* 3000: ENG2D */ 440 cp_ctx(ctx, 0x403004, 0x1); 441 gr_def(ctx, 0x403004, 0x00000001); 442 443 /* 3400 */ 444 if (device->chipset >= 0xa0) { 445 cp_ctx(ctx, 0x403404, 0x1); 446 gr_def(ctx, 0x403404, 0x00000001); 447 } 448 449 /* 5000: CCACHE */ 450 cp_ctx(ctx, 0x405000, 0x1); 451 switch (device->chipset) { 452 case 0x50: 453 gr_def(ctx, 0x405000, 0x00300080); 454 break; 455 case 0x84: 456 case 0xa0: 457 case 0xa3: 458 case 0xa5: 459 case 0xa8: 460 case 0xaa: 461 case 0xac: 462 case 0xaf: 463 gr_def(ctx, 0x405000, 0x000e0080); 464 break; 465 case 0x86: 466 case 0x92: 467 case 0x94: 468 case 0x96: 469 case 0x98: 470 gr_def(ctx, 0x405000, 0x00000080); 471 break; 472 } 473 cp_ctx(ctx, 0x405014, 0x1); 474 gr_def(ctx, 0x405014, 0x00000004); 475 cp_ctx(ctx, 0x40501c, 0x1); 476 cp_ctx(ctx, 0x405024, 0x1); 477 cp_ctx(ctx, 0x40502c, 0x1); 478 479 /* 6000? */ 480 if (device->chipset == 0x50) 481 cp_ctx(ctx, 0x4063e0, 0x1); 482 483 /* 6800: M2MF */ 484 if (device->chipset < 0x90) { 485 cp_ctx(ctx, 0x406814, 0x2b); 486 gr_def(ctx, 0x406818, 0x00000f80); 487 gr_def(ctx, 0x406860, 0x007f0080); 488 gr_def(ctx, 0x40689c, 0x007f0080); 489 } else { 490 cp_ctx(ctx, 0x406814, 0x4); 491 if (device->chipset == 0x98) 492 gr_def(ctx, 0x406818, 0x00000f80); 493 else 494 gr_def(ctx, 0x406818, 0x00001f80); 495 if (IS_NVA3F(device->chipset)) 496 gr_def(ctx, 0x40681c, 0x00000030); 497 cp_ctx(ctx, 0x406830, 0x3); 498 } 499 500 /* 7000: per-ROP group state */ 501 for (i = 0; i < 8; i++) { 502 if (units & (1<<(i+16))) { 503 cp_ctx(ctx, 0x407000 + (i<<8), 3); 504 if (device->chipset == 0x50) 505 gr_def(ctx, 0x407000 + (i<<8), 0x1b74f820); 506 else if (device->chipset != 0xa5) 507 gr_def(ctx, 0x407000 + (i<<8), 0x3b74f821); 508 else 509 gr_def(ctx, 0x407000 + (i<<8), 0x7b74f821); 510 gr_def(ctx, 0x407004 + (i<<8), 0x89058001); 511 512 if (device->chipset == 0x50) { 513 cp_ctx(ctx, 0x407010 + (i<<8), 1); 514 } else if (device->chipset < 0xa0) { 515 cp_ctx(ctx, 0x407010 + (i<<8), 2); 516 gr_def(ctx, 0x407010 + (i<<8), 0x00001000); 517 gr_def(ctx, 0x407014 + (i<<8), 0x0000001f); 518 } else { 519 cp_ctx(ctx, 0x407010 + (i<<8), 3); 520 gr_def(ctx, 0x407010 + (i<<8), 0x00001000); 521 if (device->chipset != 0xa5) 522 gr_def(ctx, 0x407014 + (i<<8), 0x000000ff); 523 else 524 gr_def(ctx, 0x407014 + (i<<8), 0x000001ff); 525 } 526 527 cp_ctx(ctx, 0x407080 + (i<<8), 4); 528 if (device->chipset != 0xa5) 529 gr_def(ctx, 0x407080 + (i<<8), 0x027c10fa); 530 else 531 gr_def(ctx, 0x407080 + (i<<8), 0x827c10fa); 532 if (device->chipset == 0x50) 533 gr_def(ctx, 0x407084 + (i<<8), 0x000000c0); 534 else 535 gr_def(ctx, 0x407084 + (i<<8), 0x400000c0); 536 gr_def(ctx, 0x407088 + (i<<8), 0xb7892080); 537 538 if (device->chipset < 0xa0) 539 cp_ctx(ctx, 0x407094 + (i<<8), 1); 540 else if (!IS_NVA3F(device->chipset)) 541 cp_ctx(ctx, 0x407094 + (i<<8), 3); 542 else { 543 cp_ctx(ctx, 0x407094 + (i<<8), 4); 544 gr_def(ctx, 0x4070a0 + (i<<8), 1); 545 } 546 } 547 } 548 549 cp_ctx(ctx, 0x407c00, 0x3); 550 if (device->chipset < 0x90) 551 gr_def(ctx, 0x407c00, 0x00010040); 552 else if (device->chipset < 0xa0) 553 gr_def(ctx, 0x407c00, 0x00390040); 554 else 555 gr_def(ctx, 0x407c00, 0x003d0040); 556 gr_def(ctx, 0x407c08, 0x00000022); 557 if (device->chipset >= 0xa0) { 558 cp_ctx(ctx, 0x407c10, 0x3); 559 cp_ctx(ctx, 0x407c20, 0x1); 560 cp_ctx(ctx, 0x407c2c, 0x1); 561 } 562 563 if (device->chipset < 0xa0) { 564 cp_ctx(ctx, 0x407d00, 0x9); 565 } else { 566 cp_ctx(ctx, 0x407d00, 0x15); 567 } 568 if (device->chipset == 0x98) 569 gr_def(ctx, 0x407d08, 0x00380040); 570 else { 571 if (device->chipset < 0x90) 572 gr_def(ctx, 0x407d08, 0x00010040); 573 else if (device->chipset < 0xa0) 574 gr_def(ctx, 0x407d08, 0x00390040); 575 else { 576 if (nouveau_fb(device)->ram->type != NV_MEM_TYPE_GDDR5) 577 gr_def(ctx, 0x407d08, 0x003d0040); 578 else 579 gr_def(ctx, 0x407d08, 0x003c0040); 580 } 581 gr_def(ctx, 0x407d0c, 0x00000022); 582 } 583 584 /* 8000+: per-TP state */ 585 for (i = 0; i < 10; i++) { 586 if (units & (1<<i)) { 587 if (device->chipset < 0xa0) 588 base = 0x408000 + (i<<12); 589 else 590 base = 0x408000 + (i<<11); 591 if (device->chipset < 0xa0) 592 offset = base + 0xc00; 593 else 594 offset = base + 0x80; 595 cp_ctx(ctx, offset + 0x00, 1); 596 gr_def(ctx, offset + 0x00, 0x0000ff0a); 597 cp_ctx(ctx, offset + 0x08, 1); 598 599 /* per-MP state */ 600 for (j = 0; j < (device->chipset < 0xa0 ? 2 : 4); j++) { 601 if (!(units & (1 << (j+24)))) continue; 602 if (device->chipset < 0xa0) 603 offset = base + 0x200 + (j<<7); 604 else 605 offset = base + 0x100 + (j<<7); 606 cp_ctx(ctx, offset, 0x20); 607 gr_def(ctx, offset + 0x00, 0x01800000); 608 gr_def(ctx, offset + 0x04, 0x00160000); 609 gr_def(ctx, offset + 0x08, 0x01800000); 610 gr_def(ctx, offset + 0x18, 0x0003ffff); 611 switch (device->chipset) { 612 case 0x50: 613 gr_def(ctx, offset + 0x1c, 0x00080000); 614 break; 615 case 0x84: 616 gr_def(ctx, offset + 0x1c, 0x00880000); 617 break; 618 case 0x86: 619 gr_def(ctx, offset + 0x1c, 0x018c0000); 620 break; 621 case 0x92: 622 case 0x96: 623 case 0x98: 624 gr_def(ctx, offset + 0x1c, 0x118c0000); 625 break; 626 case 0x94: 627 gr_def(ctx, offset + 0x1c, 0x10880000); 628 break; 629 case 0xa0: 630 case 0xa5: 631 gr_def(ctx, offset + 0x1c, 0x310c0000); 632 break; 633 case 0xa3: 634 case 0xa8: 635 case 0xaa: 636 case 0xac: 637 case 0xaf: 638 gr_def(ctx, offset + 0x1c, 0x300c0000); 639 break; 640 } 641 gr_def(ctx, offset + 0x40, 0x00010401); 642 if (device->chipset == 0x50) 643 gr_def(ctx, offset + 0x48, 0x00000040); 644 else 645 gr_def(ctx, offset + 0x48, 0x00000078); 646 gr_def(ctx, offset + 0x50, 0x000000bf); 647 gr_def(ctx, offset + 0x58, 0x00001210); 648 if (device->chipset == 0x50) 649 gr_def(ctx, offset + 0x5c, 0x00000080); 650 else 651 gr_def(ctx, offset + 0x5c, 0x08000080); 652 if (device->chipset >= 0xa0) 653 gr_def(ctx, offset + 0x68, 0x0000003e); 654 } 655 656 if (device->chipset < 0xa0) 657 cp_ctx(ctx, base + 0x300, 0x4); 658 else 659 cp_ctx(ctx, base + 0x300, 0x5); 660 if (device->chipset == 0x50) 661 gr_def(ctx, base + 0x304, 0x00007070); 662 else if (device->chipset < 0xa0) 663 gr_def(ctx, base + 0x304, 0x00027070); 664 else if (!IS_NVA3F(device->chipset)) 665 gr_def(ctx, base + 0x304, 0x01127070); 666 else 667 gr_def(ctx, base + 0x304, 0x05127070); 668 669 if (device->chipset < 0xa0) 670 cp_ctx(ctx, base + 0x318, 1); 671 else 672 cp_ctx(ctx, base + 0x320, 1); 673 if (device->chipset == 0x50) 674 gr_def(ctx, base + 0x318, 0x0003ffff); 675 else if (device->chipset < 0xa0) 676 gr_def(ctx, base + 0x318, 0x03ffffff); 677 else 678 gr_def(ctx, base + 0x320, 0x07ffffff); 679 680 if (device->chipset < 0xa0) 681 cp_ctx(ctx, base + 0x324, 5); 682 else 683 cp_ctx(ctx, base + 0x328, 4); 684 685 if (device->chipset < 0xa0) { 686 cp_ctx(ctx, base + 0x340, 9); 687 offset = base + 0x340; 688 } else if (!IS_NVA3F(device->chipset)) { 689 cp_ctx(ctx, base + 0x33c, 0xb); 690 offset = base + 0x344; 691 } else { 692 cp_ctx(ctx, base + 0x33c, 0xd); 693 offset = base + 0x344; 694 } 695 gr_def(ctx, offset + 0x0, 0x00120407); 696 gr_def(ctx, offset + 0x4, 0x05091507); 697 if (device->chipset == 0x84) 698 gr_def(ctx, offset + 0x8, 0x05100202); 699 else 700 gr_def(ctx, offset + 0x8, 0x05010202); 701 gr_def(ctx, offset + 0xc, 0x00030201); 702 if (device->chipset == 0xa3) 703 cp_ctx(ctx, base + 0x36c, 1); 704 705 cp_ctx(ctx, base + 0x400, 2); 706 gr_def(ctx, base + 0x404, 0x00000040); 707 cp_ctx(ctx, base + 0x40c, 2); 708 gr_def(ctx, base + 0x40c, 0x0d0c0b0a); 709 gr_def(ctx, base + 0x410, 0x00141210); 710 711 if (device->chipset < 0xa0) 712 offset = base + 0x800; 713 else 714 offset = base + 0x500; 715 cp_ctx(ctx, offset, 6); 716 gr_def(ctx, offset + 0x0, 0x000001f0); 717 gr_def(ctx, offset + 0x4, 0x00000001); 718 gr_def(ctx, offset + 0x8, 0x00000003); 719 if (device->chipset == 0x50 || IS_NVAAF(device->chipset)) 720 gr_def(ctx, offset + 0xc, 0x00008000); 721 gr_def(ctx, offset + 0x14, 0x00039e00); 722 cp_ctx(ctx, offset + 0x1c, 2); 723 if (device->chipset == 0x50) 724 gr_def(ctx, offset + 0x1c, 0x00000040); 725 else 726 gr_def(ctx, offset + 0x1c, 0x00000100); 727 gr_def(ctx, offset + 0x20, 0x00003800); 728 729 if (device->chipset >= 0xa0) { 730 cp_ctx(ctx, base + 0x54c, 2); 731 if (!IS_NVA3F(device->chipset)) 732 gr_def(ctx, base + 0x54c, 0x003fe006); 733 else 734 gr_def(ctx, base + 0x54c, 0x003fe007); 735 gr_def(ctx, base + 0x550, 0x003fe000); 736 } 737 738 if (device->chipset < 0xa0) 739 offset = base + 0xa00; 740 else 741 offset = base + 0x680; 742 cp_ctx(ctx, offset, 1); 743 gr_def(ctx, offset, 0x00404040); 744 745 if (device->chipset < 0xa0) 746 offset = base + 0xe00; 747 else 748 offset = base + 0x700; 749 cp_ctx(ctx, offset, 2); 750 if (device->chipset < 0xa0) 751 gr_def(ctx, offset, 0x0077f005); 752 else if (device->chipset == 0xa5) 753 gr_def(ctx, offset, 0x6cf7f007); 754 else if (device->chipset == 0xa8) 755 gr_def(ctx, offset, 0x6cfff007); 756 else if (device->chipset == 0xac) 757 gr_def(ctx, offset, 0x0cfff007); 758 else 759 gr_def(ctx, offset, 0x0cf7f007); 760 if (device->chipset == 0x50) 761 gr_def(ctx, offset + 0x4, 0x00007fff); 762 else if (device->chipset < 0xa0) 763 gr_def(ctx, offset + 0x4, 0x003f7fff); 764 else 765 gr_def(ctx, offset + 0x4, 0x02bf7fff); 766 cp_ctx(ctx, offset + 0x2c, 1); 767 if (device->chipset == 0x50) { 768 cp_ctx(ctx, offset + 0x50, 9); 769 gr_def(ctx, offset + 0x54, 0x000003ff); 770 gr_def(ctx, offset + 0x58, 0x00000003); 771 gr_def(ctx, offset + 0x5c, 0x00000003); 772 gr_def(ctx, offset + 0x60, 0x000001ff); 773 gr_def(ctx, offset + 0x64, 0x0000001f); 774 gr_def(ctx, offset + 0x68, 0x0000000f); 775 gr_def(ctx, offset + 0x6c, 0x0000000f); 776 } else if (device->chipset < 0xa0) { 777 cp_ctx(ctx, offset + 0x50, 1); 778 cp_ctx(ctx, offset + 0x70, 1); 779 } else { 780 cp_ctx(ctx, offset + 0x50, 1); 781 cp_ctx(ctx, offset + 0x60, 5); 782 } 783 } 784 } 785 } 786 787 static void 788 dd_emit(struct nouveau_grctx *ctx, int num, u32 val) { 789 int i; 790 if (val && ctx->mode == NOUVEAU_GRCTX_VALS) 791 for (i = 0; i < num; i++) 792 nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val); 793 ctx->ctxvals_pos += num; 794 } 795 796 static void 797 nv50_gr_construct_mmio_ddata(struct nouveau_grctx *ctx) 798 { 799 struct nouveau_device *device = ctx->device; 800 int base, num; 801 base = ctx->ctxvals_pos; 802 803 /* tesla state */ 804 dd_emit(ctx, 1, 0); /* 00000001 UNK0F90 */ 805 dd_emit(ctx, 1, 0); /* 00000001 UNK135C */ 806 807 /* SRC_TIC state */ 808 dd_emit(ctx, 1, 0); /* 00000007 SRC_TILE_MODE_Z */ 809 dd_emit(ctx, 1, 2); /* 00000007 SRC_TILE_MODE_Y */ 810 dd_emit(ctx, 1, 1); /* 00000001 SRC_LINEAR #1 */ 811 dd_emit(ctx, 1, 0); /* 000000ff SRC_ADDRESS_HIGH */ 812 dd_emit(ctx, 1, 0); /* 00000001 SRC_SRGB */ 813 if (device->chipset >= 0x94) 814 dd_emit(ctx, 1, 0); /* 00000003 eng2d UNK0258 */ 815 dd_emit(ctx, 1, 1); /* 00000fff SRC_DEPTH */ 816 dd_emit(ctx, 1, 0x100); /* 0000ffff SRC_HEIGHT */ 817 818 /* turing state */ 819 dd_emit(ctx, 1, 0); /* 0000000f TEXTURES_LOG2 */ 820 dd_emit(ctx, 1, 0); /* 0000000f SAMPLERS_LOG2 */ 821 dd_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */ 822 dd_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */ 823 dd_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */ 824 dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */ 825 dd_emit(ctx, 1, 1); /* 0000ffff BLOCK_ALLOC_THREADS */ 826 dd_emit(ctx, 1, 1); /* 00000001 LANES32 */ 827 dd_emit(ctx, 1, 0); /* 000000ff UNK370 */ 828 dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_UNK */ 829 dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_COUNT */ 830 dd_emit(ctx, 1, 1); /* 000000ff UNK384 bits 8-15 */ 831 dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ 832 dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ 833 dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */ 834 dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_X */ 835 dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_XMY */ 836 dd_emit(ctx, 1, 0); /* 00000001 BLOCKDIM_XMY_OVERFLOW */ 837 dd_emit(ctx, 1, 1); /* 0003ffff BLOCKDIM_XMYMZ */ 838 dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_Y */ 839 dd_emit(ctx, 1, 1); /* 0000007f BLOCKDIM_Z */ 840 dd_emit(ctx, 1, 4); /* 000000ff CP_REG_ALLOC_TEMP */ 841 dd_emit(ctx, 1, 1); /* 00000001 BLOCKDIM_DIRTY */ 842 if (IS_NVA3F(device->chipset)) 843 dd_emit(ctx, 1, 0); /* 00000003 UNK03E8 */ 844 dd_emit(ctx, 1, 1); /* 0000007f BLOCK_ALLOC_HALFWARPS */ 845 dd_emit(ctx, 1, 1); /* 00000007 LOCAL_WARPS_NO_CLAMP */ 846 dd_emit(ctx, 1, 7); /* 00000007 LOCAL_WARPS_LOG_ALLOC */ 847 dd_emit(ctx, 1, 1); /* 00000007 STACK_WARPS_NO_CLAMP */ 848 dd_emit(ctx, 1, 7); /* 00000007 STACK_WARPS_LOG_ALLOC */ 849 dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_PACKED */ 850 dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_STRIDED */ 851 dd_emit(ctx, 1, 1); /* 000007ff BLOCK_ALLOC_THREADS */ 852 853 /* compat 2d state */ 854 if (device->chipset == 0x50) { 855 dd_emit(ctx, 4, 0); /* 0000ffff clip X, Y, W, H */ 856 857 dd_emit(ctx, 1, 1); /* ffffffff chroma COLOR_FORMAT */ 858 859 dd_emit(ctx, 1, 1); /* ffffffff pattern COLOR_FORMAT */ 860 dd_emit(ctx, 1, 0); /* ffffffff pattern SHAPE */ 861 dd_emit(ctx, 1, 1); /* ffffffff pattern PATTERN_SELECT */ 862 863 dd_emit(ctx, 1, 0xa); /* ffffffff surf2d SRC_FORMAT */ 864 dd_emit(ctx, 1, 0); /* ffffffff surf2d DMA_SRC */ 865 dd_emit(ctx, 1, 0); /* 000000ff surf2d SRC_ADDRESS_HIGH */ 866 dd_emit(ctx, 1, 0); /* ffffffff surf2d SRC_ADDRESS_LOW */ 867 dd_emit(ctx, 1, 0x40); /* 0000ffff surf2d SRC_PITCH */ 868 dd_emit(ctx, 1, 0); /* 0000000f surf2d SRC_TILE_MODE_Z */ 869 dd_emit(ctx, 1, 2); /* 0000000f surf2d SRC_TILE_MODE_Y */ 870 dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_HEIGHT */ 871 dd_emit(ctx, 1, 1); /* 00000001 surf2d SRC_LINEAR */ 872 dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_WIDTH */ 873 874 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_X */ 875 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_Y */ 876 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_X */ 877 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_Y */ 878 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_X */ 879 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_Y */ 880 dd_emit(ctx, 1, 1); /* ffffffff gdirect COLOR_FORMAT */ 881 dd_emit(ctx, 1, 0); /* ffffffff gdirect OPERATION */ 882 dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_X */ 883 dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_Y */ 884 885 dd_emit(ctx, 1, 0); /* 0000ffff blit SRC_Y */ 886 dd_emit(ctx, 1, 0); /* ffffffff blit OPERATION */ 887 888 dd_emit(ctx, 1, 0); /* ffffffff ifc OPERATION */ 889 890 dd_emit(ctx, 1, 0); /* ffffffff iifc INDEX_FORMAT */ 891 dd_emit(ctx, 1, 0); /* ffffffff iifc LUT_OFFSET */ 892 dd_emit(ctx, 1, 4); /* ffffffff iifc COLOR_FORMAT */ 893 dd_emit(ctx, 1, 0); /* ffffffff iifc OPERATION */ 894 } 895 896 /* m2mf state */ 897 dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_COUNT */ 898 dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_LENGTH_IN */ 899 dd_emit(ctx, 2, 0); /* ffffffff m2mf OFFSET_IN, OFFSET_OUT */ 900 dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_OUT */ 901 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_OUT */ 902 dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_OUT_Z */ 903 dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_OUT */ 904 dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_OUT_X, Y */ 905 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_OUT */ 906 dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_IN */ 907 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_IN */ 908 dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_IN_Z */ 909 dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_IN */ 910 dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_IN_X, Y */ 911 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_IN */ 912 913 /* more compat 2d state */ 914 if (device->chipset == 0x50) { 915 dd_emit(ctx, 1, 1); /* ffffffff line COLOR_FORMAT */ 916 dd_emit(ctx, 1, 0); /* ffffffff line OPERATION */ 917 918 dd_emit(ctx, 1, 1); /* ffffffff triangle COLOR_FORMAT */ 919 dd_emit(ctx, 1, 0); /* ffffffff triangle OPERATION */ 920 921 dd_emit(ctx, 1, 0); /* 0000000f sifm TILE_MODE_Z */ 922 dd_emit(ctx, 1, 2); /* 0000000f sifm TILE_MODE_Y */ 923 dd_emit(ctx, 1, 0); /* 000000ff sifm FORMAT_FILTER */ 924 dd_emit(ctx, 1, 1); /* 000000ff sifm FORMAT_ORIGIN */ 925 dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_PITCH */ 926 dd_emit(ctx, 1, 1); /* 00000001 sifm SRC_LINEAR */ 927 dd_emit(ctx, 1, 0); /* 000000ff sifm SRC_OFFSET_HIGH */ 928 dd_emit(ctx, 1, 0); /* ffffffff sifm SRC_OFFSET */ 929 dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_HEIGHT */ 930 dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_WIDTH */ 931 dd_emit(ctx, 1, 3); /* ffffffff sifm COLOR_FORMAT */ 932 dd_emit(ctx, 1, 0); /* ffffffff sifm OPERATION */ 933 934 dd_emit(ctx, 1, 0); /* ffffffff sifc OPERATION */ 935 } 936 937 /* tesla state */ 938 dd_emit(ctx, 1, 0); /* 0000000f GP_TEXTURES_LOG2 */ 939 dd_emit(ctx, 1, 0); /* 0000000f GP_SAMPLERS_LOG2 */ 940 dd_emit(ctx, 1, 0); /* 000000ff */ 941 dd_emit(ctx, 1, 0); /* ffffffff */ 942 dd_emit(ctx, 1, 4); /* 000000ff UNK12B0_0 */ 943 dd_emit(ctx, 1, 0x70); /* 000000ff UNK12B0_1 */ 944 dd_emit(ctx, 1, 0x80); /* 000000ff UNK12B0_3 */ 945 dd_emit(ctx, 1, 0); /* 000000ff UNK12B0_2 */ 946 dd_emit(ctx, 1, 0); /* 0000000f FP_TEXTURES_LOG2 */ 947 dd_emit(ctx, 1, 0); /* 0000000f FP_SAMPLERS_LOG2 */ 948 if (IS_NVA3F(device->chipset)) { 949 dd_emit(ctx, 1, 0); /* ffffffff */ 950 dd_emit(ctx, 1, 0); /* 0000007f MULTISAMPLE_SAMPLES_LOG2 */ 951 } else { 952 dd_emit(ctx, 1, 0); /* 0000000f MULTISAMPLE_SAMPLES_LOG2 */ 953 } 954 dd_emit(ctx, 1, 0xc); /* 000000ff SEMANTIC_COLOR.BFC0_ID */ 955 if (device->chipset != 0x50) 956 dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_COLOR.CLMP_EN */ 957 dd_emit(ctx, 1, 8); /* 000000ff SEMANTIC_COLOR.COLR_NR */ 958 dd_emit(ctx, 1, 0x14); /* 000000ff SEMANTIC_COLOR.FFC0_ID */ 959 if (device->chipset == 0x50) { 960 dd_emit(ctx, 1, 0); /* 000000ff SEMANTIC_LAYER */ 961 dd_emit(ctx, 1, 0); /* 00000001 */ 962 } else { 963 dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_PTSZ.ENABLE */ 964 dd_emit(ctx, 1, 0x29); /* 000000ff SEMANTIC_PTSZ.PTSZ_ID */ 965 dd_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM */ 966 dd_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ 967 dd_emit(ctx, 1, 8); /* 0000000f SMENATIC_CLIP.CLIP_HIGH */ 968 dd_emit(ctx, 1, 4); /* 000000ff SEMANTIC_CLIP.CLIP_LO */ 969 dd_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */ 970 dd_emit(ctx, 1, 0); /* 00000001 UNK1900 */ 971 } 972 dd_emit(ctx, 1, 0); /* 00000007 RT_CONTROL_MAP0 */ 973 dd_emit(ctx, 1, 1); /* 00000007 RT_CONTROL_MAP1 */ 974 dd_emit(ctx, 1, 2); /* 00000007 RT_CONTROL_MAP2 */ 975 dd_emit(ctx, 1, 3); /* 00000007 RT_CONTROL_MAP3 */ 976 dd_emit(ctx, 1, 4); /* 00000007 RT_CONTROL_MAP4 */ 977 dd_emit(ctx, 1, 5); /* 00000007 RT_CONTROL_MAP5 */ 978 dd_emit(ctx, 1, 6); /* 00000007 RT_CONTROL_MAP6 */ 979 dd_emit(ctx, 1, 7); /* 00000007 RT_CONTROL_MAP7 */ 980 dd_emit(ctx, 1, 1); /* 0000000f RT_CONTROL_COUNT */ 981 dd_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_UNK */ 982 dd_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */ 983 dd_emit(ctx, 1, 0xcf); /* 000000ff RT_FORMAT */ 984 dd_emit(ctx, 7, 0); /* 000000ff RT_FORMAT */ 985 if (device->chipset != 0x50) 986 dd_emit(ctx, 3, 0); /* 1, 1, 1 */ 987 else 988 dd_emit(ctx, 2, 0); /* 1, 1 */ 989 dd_emit(ctx, 1, 0); /* ffffffff GP_ENABLE */ 990 dd_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT*/ 991 dd_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ 992 dd_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 993 if (IS_NVA3F(device->chipset)) { 994 dd_emit(ctx, 1, 3); /* 00000003 */ 995 dd_emit(ctx, 1, 0); /* 00000001 UNK1418. Alone. */ 996 } 997 if (device->chipset != 0x50) 998 dd_emit(ctx, 1, 3); /* 00000003 UNK15AC */ 999 dd_emit(ctx, 1, 1); /* ffffffff RASTERIZE_ENABLE */ 1000 dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.EXPORTS_Z */ 1001 if (device->chipset != 0x50) 1002 dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.MULTIPLE_RESULTS */ 1003 dd_emit(ctx, 1, 0x12); /* 000000ff FP_INTERPOLANT_CTRL.COUNT */ 1004 dd_emit(ctx, 1, 0x10); /* 000000ff FP_INTERPOLANT_CTRL.COUNT_NONFLAT */ 1005 dd_emit(ctx, 1, 0xc); /* 000000ff FP_INTERPOLANT_CTRL.OFFSET */ 1006 dd_emit(ctx, 1, 1); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.W */ 1007 dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.X */ 1008 dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Y */ 1009 dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Z */ 1010 dd_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */ 1011 dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */ 1012 dd_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ 1013 if (device->chipset >= 0xa0) 1014 dd_emit(ctx, 1, 0); /* ffffffff */ 1015 dd_emit(ctx, 1, 0); /* 00000001 GP_BUILTIN_RESULT_EN.LAYER_IDX */ 1016 dd_emit(ctx, 1, 0); /* ffffffff STRMOUT_ENABLE */ 1017 dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ 1018 dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ 1019 dd_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE*/ 1020 if (device->chipset != 0x50) 1021 dd_emit(ctx, 8, 0); /* 00000001 */ 1022 if (device->chipset >= 0xa0) { 1023 dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.COMP */ 1024 dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.SIZE */ 1025 dd_emit(ctx, 1, 2); /* 00000007 VTX_ATTR_DEFINE.TYPE */ 1026 dd_emit(ctx, 1, 0); /* 000000ff VTX_ATTR_DEFINE.ATTR */ 1027 } 1028 dd_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1029 dd_emit(ctx, 1, 0x14); /* 0000001f ZETA_FORMAT */ 1030 dd_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 1031 dd_emit(ctx, 1, 0); /* 0000000f VP_TEXTURES_LOG2 */ 1032 dd_emit(ctx, 1, 0); /* 0000000f VP_SAMPLERS_LOG2 */ 1033 if (IS_NVA3F(device->chipset)) 1034 dd_emit(ctx, 1, 0); /* 00000001 */ 1035 dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_BACK */ 1036 if (device->chipset >= 0xa0) 1037 dd_emit(ctx, 1, 0); /* 00000003 VTX_ATTR_DEFINE.SIZE - 1 */ 1038 dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */ 1039 if (device->chipset >= 0xa0) 1040 dd_emit(ctx, 1, 0); /* 00000003 */ 1041 dd_emit(ctx, 1, 0); /* 00000001 CULL_FACE_ENABLE */ 1042 dd_emit(ctx, 1, 1); /* 00000003 CULL_FACE */ 1043 dd_emit(ctx, 1, 0); /* 00000001 FRONT_FACE */ 1044 dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_FRONT */ 1045 dd_emit(ctx, 1, 0x1000); /* 00007fff UNK141C */ 1046 if (device->chipset != 0x50) { 1047 dd_emit(ctx, 1, 0xe00); /* 7fff */ 1048 dd_emit(ctx, 1, 0x1000); /* 7fff */ 1049 dd_emit(ctx, 1, 0x1e00); /* 7fff */ 1050 } 1051 dd_emit(ctx, 1, 0); /* 00000001 BEGIN_END_ACTIVE */ 1052 dd_emit(ctx, 1, 1); /* 00000001 POLYGON_MODE_??? */ 1053 dd_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP / 4 rounded up */ 1054 dd_emit(ctx, 1, 1); /* 000000ff FP_REG_ALLOC_TEMP... without /4? */ 1055 dd_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP / 4 rounded up */ 1056 dd_emit(ctx, 1, 1); /* 00000001 */ 1057 dd_emit(ctx, 1, 0); /* 00000001 */ 1058 dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK0 nonempty */ 1059 dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK1 nonempty */ 1060 dd_emit(ctx, 1, 0x200); /* 0003ffff GP_VERTEX_OUTPUT_COUNT*GP_REG_ALLOC_RESULT */ 1061 if (IS_NVA3F(device->chipset)) 1062 dd_emit(ctx, 1, 0x200); 1063 dd_emit(ctx, 1, 0); /* 00000001 */ 1064 if (device->chipset < 0xa0) { 1065 dd_emit(ctx, 1, 1); /* 00000001 */ 1066 dd_emit(ctx, 1, 0x70); /* 000000ff */ 1067 dd_emit(ctx, 1, 0x80); /* 000000ff */ 1068 dd_emit(ctx, 1, 0); /* 000000ff */ 1069 dd_emit(ctx, 1, 0); /* 00000001 */ 1070 dd_emit(ctx, 1, 1); /* 00000001 */ 1071 dd_emit(ctx, 1, 0x70); /* 000000ff */ 1072 dd_emit(ctx, 1, 0x80); /* 000000ff */ 1073 dd_emit(ctx, 1, 0); /* 000000ff */ 1074 } else { 1075 dd_emit(ctx, 1, 1); /* 00000001 */ 1076 dd_emit(ctx, 1, 0xf0); /* 000000ff */ 1077 dd_emit(ctx, 1, 0xff); /* 000000ff */ 1078 dd_emit(ctx, 1, 0); /* 000000ff */ 1079 dd_emit(ctx, 1, 0); /* 00000001 */ 1080 dd_emit(ctx, 1, 1); /* 00000001 */ 1081 dd_emit(ctx, 1, 0xf0); /* 000000ff */ 1082 dd_emit(ctx, 1, 0xff); /* 000000ff */ 1083 dd_emit(ctx, 1, 0); /* 000000ff */ 1084 dd_emit(ctx, 1, 9); /* 0000003f UNK114C.COMP,SIZE */ 1085 } 1086 1087 /* eng2d state */ 1088 dd_emit(ctx, 1, 0); /* 00000001 eng2d COLOR_KEY_ENABLE */ 1089 dd_emit(ctx, 1, 0); /* 00000007 eng2d COLOR_KEY_FORMAT */ 1090 dd_emit(ctx, 1, 1); /* ffffffff eng2d DST_DEPTH */ 1091 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DST_FORMAT */ 1092 dd_emit(ctx, 1, 0); /* ffffffff eng2d DST_LAYER */ 1093 dd_emit(ctx, 1, 1); /* 00000001 eng2d DST_LINEAR */ 1094 dd_emit(ctx, 1, 0); /* 00000007 eng2d PATTERN_COLOR_FORMAT */ 1095 dd_emit(ctx, 1, 0); /* 00000007 eng2d OPERATION */ 1096 dd_emit(ctx, 1, 0); /* 00000003 eng2d PATTERN_SELECT */ 1097 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SIFC_FORMAT */ 1098 dd_emit(ctx, 1, 0); /* 00000001 eng2d SIFC_BITMAP_ENABLE */ 1099 dd_emit(ctx, 1, 2); /* 00000003 eng2d SIFC_BITMAP_UNK808 */ 1100 dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DU_DX_FRACT */ 1101 dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DU_DX_INT */ 1102 dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DV_DY_FRACT */ 1103 dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DV_DY_INT */ 1104 dd_emit(ctx, 1, 0); /* 00000001 eng2d BLIT_CONTROL_FILTER */ 1105 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DRAW_COLOR_FORMAT */ 1106 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SRC_FORMAT */ 1107 dd_emit(ctx, 1, 1); /* 00000001 eng2d SRC_LINEAR #2 */ 1108 1109 num = ctx->ctxvals_pos - base; 1110 ctx->ctxvals_pos = base; 1111 if (IS_NVA3F(device->chipset)) 1112 cp_ctx(ctx, 0x404800, num); 1113 else 1114 cp_ctx(ctx, 0x405400, num); 1115 } 1116 1117 /* 1118 * xfer areas. These are a pain. 1119 * 1120 * There are 2 xfer areas: the first one is big and contains all sorts of 1121 * stuff, the second is small and contains some per-TP context. 1122 * 1123 * Each area is split into 8 "strands". The areas, when saved to grctx, 1124 * are made of 8-word blocks. Each block contains a single word from 1125 * each strand. The strands are independent of each other, their 1126 * addresses are unrelated to each other, and data in them is closely 1127 * packed together. The strand layout varies a bit between cards: here 1128 * and there, a single word is thrown out in the middle and the whole 1129 * strand is offset by a bit from corresponding one on another chipset. 1130 * For this reason, addresses of stuff in strands are almost useless. 1131 * Knowing sequence of stuff and size of gaps between them is much more 1132 * useful, and that's how we build the strands in our generator. 1133 * 1134 * NVA0 takes this mess to a whole new level by cutting the old strands 1135 * into a few dozen pieces [known as genes], rearranging them randomly, 1136 * and putting them back together to make new strands. Hopefully these 1137 * genes correspond more or less directly to the same PGRAPH subunits 1138 * as in 400040 register. 1139 * 1140 * The most common value in default context is 0, and when the genes 1141 * are separated by 0's, gene bounduaries are quite speculative... 1142 * some of them can be clearly deduced, others can be guessed, and yet 1143 * others won't be resolved without figuring out the real meaning of 1144 * given ctxval. For the same reason, ending point of each strand 1145 * is unknown. Except for strand 0, which is the longest strand and 1146 * its end corresponds to end of the whole xfer. 1147 * 1148 * An unsolved mystery is the seek instruction: it takes an argument 1149 * in bits 8-18, and that argument is clearly the place in strands to 1150 * seek to... but the offsets don't seem to correspond to offsets as 1151 * seen in grctx. Perhaps there's another, real, not randomly-changing 1152 * addressing in strands, and the xfer insn just happens to skip over 1153 * the unused bits? NV10-NV30 PIPE comes to mind... 1154 * 1155 * As far as I know, there's no way to access the xfer areas directly 1156 * without the help of ctxprog. 1157 */ 1158 1159 static void 1160 xf_emit(struct nouveau_grctx *ctx, int num, u32 val) { 1161 int i; 1162 if (val && ctx->mode == NOUVEAU_GRCTX_VALS) 1163 for (i = 0; i < num; i++) 1164 nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val); 1165 ctx->ctxvals_pos += num << 3; 1166 } 1167 1168 /* Gene declarations... */ 1169 1170 static void nv50_gr_construct_gene_dispatch(struct nouveau_grctx *ctx); 1171 static void nv50_gr_construct_gene_m2mf(struct nouveau_grctx *ctx); 1172 static void nv50_gr_construct_gene_ccache(struct nouveau_grctx *ctx); 1173 static void nv50_gr_construct_gene_unk10xx(struct nouveau_grctx *ctx); 1174 static void nv50_gr_construct_gene_unk14xx(struct nouveau_grctx *ctx); 1175 static void nv50_gr_construct_gene_zcull(struct nouveau_grctx *ctx); 1176 static void nv50_gr_construct_gene_clipid(struct nouveau_grctx *ctx); 1177 static void nv50_gr_construct_gene_unk24xx(struct nouveau_grctx *ctx); 1178 static void nv50_gr_construct_gene_vfetch(struct nouveau_grctx *ctx); 1179 static void nv50_gr_construct_gene_eng2d(struct nouveau_grctx *ctx); 1180 static void nv50_gr_construct_gene_csched(struct nouveau_grctx *ctx); 1181 static void nv50_gr_construct_gene_unk1cxx(struct nouveau_grctx *ctx); 1182 static void nv50_gr_construct_gene_strmout(struct nouveau_grctx *ctx); 1183 static void nv50_gr_construct_gene_unk34xx(struct nouveau_grctx *ctx); 1184 static void nv50_gr_construct_gene_ropm1(struct nouveau_grctx *ctx); 1185 static void nv50_gr_construct_gene_ropm2(struct nouveau_grctx *ctx); 1186 static void nv50_gr_construct_gene_ropc(struct nouveau_grctx *ctx); 1187 static void nv50_gr_construct_xfer_tp(struct nouveau_grctx *ctx); 1188 1189 static void 1190 nv50_gr_construct_xfer1(struct nouveau_grctx *ctx) 1191 { 1192 struct nouveau_device *device = ctx->device; 1193 int i; 1194 int offset; 1195 int size = 0; 1196 u32 units = nv_rd32 (ctx->device, 0x1540); 1197 1198 offset = (ctx->ctxvals_pos+0x3f)&~0x3f; 1199 ctx->ctxvals_base = offset; 1200 1201 if (device->chipset < 0xa0) { 1202 /* Strand 0 */ 1203 ctx->ctxvals_pos = offset; 1204 nv50_gr_construct_gene_dispatch(ctx); 1205 nv50_gr_construct_gene_m2mf(ctx); 1206 nv50_gr_construct_gene_unk24xx(ctx); 1207 nv50_gr_construct_gene_clipid(ctx); 1208 nv50_gr_construct_gene_zcull(ctx); 1209 if ((ctx->ctxvals_pos-offset)/8 > size) 1210 size = (ctx->ctxvals_pos-offset)/8; 1211 1212 /* Strand 1 */ 1213 ctx->ctxvals_pos = offset + 0x1; 1214 nv50_gr_construct_gene_vfetch(ctx); 1215 nv50_gr_construct_gene_eng2d(ctx); 1216 nv50_gr_construct_gene_csched(ctx); 1217 nv50_gr_construct_gene_ropm1(ctx); 1218 nv50_gr_construct_gene_ropm2(ctx); 1219 if ((ctx->ctxvals_pos-offset)/8 > size) 1220 size = (ctx->ctxvals_pos-offset)/8; 1221 1222 /* Strand 2 */ 1223 ctx->ctxvals_pos = offset + 0x2; 1224 nv50_gr_construct_gene_ccache(ctx); 1225 nv50_gr_construct_gene_unk1cxx(ctx); 1226 nv50_gr_construct_gene_strmout(ctx); 1227 nv50_gr_construct_gene_unk14xx(ctx); 1228 nv50_gr_construct_gene_unk10xx(ctx); 1229 nv50_gr_construct_gene_unk34xx(ctx); 1230 if ((ctx->ctxvals_pos-offset)/8 > size) 1231 size = (ctx->ctxvals_pos-offset)/8; 1232 1233 /* Strand 3: per-ROP group state */ 1234 ctx->ctxvals_pos = offset + 3; 1235 for (i = 0; i < 6; i++) 1236 if (units & (1 << (i + 16))) 1237 nv50_gr_construct_gene_ropc(ctx); 1238 if ((ctx->ctxvals_pos-offset)/8 > size) 1239 size = (ctx->ctxvals_pos-offset)/8; 1240 1241 /* Strands 4-7: per-TP state */ 1242 for (i = 0; i < 4; i++) { 1243 ctx->ctxvals_pos = offset + 4 + i; 1244 if (units & (1 << (2 * i))) 1245 nv50_gr_construct_xfer_tp(ctx); 1246 if (units & (1 << (2 * i + 1))) 1247 nv50_gr_construct_xfer_tp(ctx); 1248 if ((ctx->ctxvals_pos-offset)/8 > size) 1249 size = (ctx->ctxvals_pos-offset)/8; 1250 } 1251 } else { 1252 /* Strand 0 */ 1253 ctx->ctxvals_pos = offset; 1254 nv50_gr_construct_gene_dispatch(ctx); 1255 nv50_gr_construct_gene_m2mf(ctx); 1256 nv50_gr_construct_gene_unk34xx(ctx); 1257 nv50_gr_construct_gene_csched(ctx); 1258 nv50_gr_construct_gene_unk1cxx(ctx); 1259 nv50_gr_construct_gene_strmout(ctx); 1260 if ((ctx->ctxvals_pos-offset)/8 > size) 1261 size = (ctx->ctxvals_pos-offset)/8; 1262 1263 /* Strand 1 */ 1264 ctx->ctxvals_pos = offset + 1; 1265 nv50_gr_construct_gene_unk10xx(ctx); 1266 if ((ctx->ctxvals_pos-offset)/8 > size) 1267 size = (ctx->ctxvals_pos-offset)/8; 1268 1269 /* Strand 2 */ 1270 ctx->ctxvals_pos = offset + 2; 1271 if (device->chipset == 0xa0) 1272 nv50_gr_construct_gene_unk14xx(ctx); 1273 nv50_gr_construct_gene_unk24xx(ctx); 1274 if ((ctx->ctxvals_pos-offset)/8 > size) 1275 size = (ctx->ctxvals_pos-offset)/8; 1276 1277 /* Strand 3 */ 1278 ctx->ctxvals_pos = offset + 3; 1279 nv50_gr_construct_gene_vfetch(ctx); 1280 if ((ctx->ctxvals_pos-offset)/8 > size) 1281 size = (ctx->ctxvals_pos-offset)/8; 1282 1283 /* Strand 4 */ 1284 ctx->ctxvals_pos = offset + 4; 1285 nv50_gr_construct_gene_ccache(ctx); 1286 if ((ctx->ctxvals_pos-offset)/8 > size) 1287 size = (ctx->ctxvals_pos-offset)/8; 1288 1289 /* Strand 5 */ 1290 ctx->ctxvals_pos = offset + 5; 1291 nv50_gr_construct_gene_ropm2(ctx); 1292 nv50_gr_construct_gene_ropm1(ctx); 1293 /* per-ROP context */ 1294 for (i = 0; i < 8; i++) 1295 if (units & (1<<(i+16))) 1296 nv50_gr_construct_gene_ropc(ctx); 1297 if ((ctx->ctxvals_pos-offset)/8 > size) 1298 size = (ctx->ctxvals_pos-offset)/8; 1299 1300 /* Strand 6 */ 1301 ctx->ctxvals_pos = offset + 6; 1302 nv50_gr_construct_gene_zcull(ctx); 1303 nv50_gr_construct_gene_clipid(ctx); 1304 nv50_gr_construct_gene_eng2d(ctx); 1305 if (units & (1 << 0)) 1306 nv50_gr_construct_xfer_tp(ctx); 1307 if (units & (1 << 1)) 1308 nv50_gr_construct_xfer_tp(ctx); 1309 if (units & (1 << 2)) 1310 nv50_gr_construct_xfer_tp(ctx); 1311 if (units & (1 << 3)) 1312 nv50_gr_construct_xfer_tp(ctx); 1313 if ((ctx->ctxvals_pos-offset)/8 > size) 1314 size = (ctx->ctxvals_pos-offset)/8; 1315 1316 /* Strand 7 */ 1317 ctx->ctxvals_pos = offset + 7; 1318 if (device->chipset == 0xa0) { 1319 if (units & (1 << 4)) 1320 nv50_gr_construct_xfer_tp(ctx); 1321 if (units & (1 << 5)) 1322 nv50_gr_construct_xfer_tp(ctx); 1323 if (units & (1 << 6)) 1324 nv50_gr_construct_xfer_tp(ctx); 1325 if (units & (1 << 7)) 1326 nv50_gr_construct_xfer_tp(ctx); 1327 if (units & (1 << 8)) 1328 nv50_gr_construct_xfer_tp(ctx); 1329 if (units & (1 << 9)) 1330 nv50_gr_construct_xfer_tp(ctx); 1331 } else { 1332 nv50_gr_construct_gene_unk14xx(ctx); 1333 } 1334 if ((ctx->ctxvals_pos-offset)/8 > size) 1335 size = (ctx->ctxvals_pos-offset)/8; 1336 } 1337 1338 ctx->ctxvals_pos = offset + size * 8; 1339 ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f; 1340 cp_lsr (ctx, offset); 1341 cp_out (ctx, CP_SET_XFER_POINTER); 1342 cp_lsr (ctx, size); 1343 cp_out (ctx, CP_SEEK_1); 1344 cp_out (ctx, CP_XFER_1); 1345 cp_wait(ctx, XFER, BUSY); 1346 } 1347 1348 /* 1349 * non-trivial demagiced parts of ctx init go here 1350 */ 1351 1352 static void 1353 nv50_gr_construct_gene_dispatch(struct nouveau_grctx *ctx) 1354 { 1355 /* start of strand 0 */ 1356 struct nouveau_device *device = ctx->device; 1357 /* SEEK */ 1358 if (device->chipset == 0x50) 1359 xf_emit(ctx, 5, 0); 1360 else if (!IS_NVA3F(device->chipset)) 1361 xf_emit(ctx, 6, 0); 1362 else 1363 xf_emit(ctx, 4, 0); 1364 /* SEEK */ 1365 /* the PGRAPH's internal FIFO */ 1366 if (device->chipset == 0x50) 1367 xf_emit(ctx, 8*3, 0); 1368 else 1369 xf_emit(ctx, 0x100*3, 0); 1370 /* and another bonus slot?!? */ 1371 xf_emit(ctx, 3, 0); 1372 /* and YET ANOTHER bonus slot? */ 1373 if (IS_NVA3F(device->chipset)) 1374 xf_emit(ctx, 3, 0); 1375 /* SEEK */ 1376 /* CTX_SWITCH: caches of gr objects bound to subchannels. 8 values, last used index */ 1377 xf_emit(ctx, 9, 0); 1378 /* SEEK */ 1379 xf_emit(ctx, 9, 0); 1380 /* SEEK */ 1381 xf_emit(ctx, 9, 0); 1382 /* SEEK */ 1383 xf_emit(ctx, 9, 0); 1384 /* SEEK */ 1385 if (device->chipset < 0x90) 1386 xf_emit(ctx, 4, 0); 1387 /* SEEK */ 1388 xf_emit(ctx, 2, 0); 1389 /* SEEK */ 1390 xf_emit(ctx, 6*2, 0); 1391 xf_emit(ctx, 2, 0); 1392 /* SEEK */ 1393 xf_emit(ctx, 2, 0); 1394 /* SEEK */ 1395 xf_emit(ctx, 6*2, 0); 1396 xf_emit(ctx, 2, 0); 1397 /* SEEK */ 1398 if (device->chipset == 0x50) 1399 xf_emit(ctx, 0x1c, 0); 1400 else if (device->chipset < 0xa0) 1401 xf_emit(ctx, 0x1e, 0); 1402 else 1403 xf_emit(ctx, 0x22, 0); 1404 /* SEEK */ 1405 xf_emit(ctx, 0x15, 0); 1406 } 1407 1408 static void 1409 nv50_gr_construct_gene_m2mf(struct nouveau_grctx *ctx) 1410 { 1411 /* Strand 0, right after dispatch */ 1412 struct nouveau_device *device = ctx->device; 1413 int smallm2mf = 0; 1414 if (device->chipset < 0x92 || device->chipset == 0x98) 1415 smallm2mf = 1; 1416 /* SEEK */ 1417 xf_emit (ctx, 1, 0); /* DMA_NOTIFY instance >> 4 */ 1418 xf_emit (ctx, 1, 0); /* DMA_BUFFER_IN instance >> 4 */ 1419 xf_emit (ctx, 1, 0); /* DMA_BUFFER_OUT instance >> 4 */ 1420 xf_emit (ctx, 1, 0); /* OFFSET_IN */ 1421 xf_emit (ctx, 1, 0); /* OFFSET_OUT */ 1422 xf_emit (ctx, 1, 0); /* PITCH_IN */ 1423 xf_emit (ctx, 1, 0); /* PITCH_OUT */ 1424 xf_emit (ctx, 1, 0); /* LINE_LENGTH */ 1425 xf_emit (ctx, 1, 0); /* LINE_COUNT */ 1426 xf_emit (ctx, 1, 0x21); /* FORMAT: bits 0-4 INPUT_INC, bits 5-9 OUTPUT_INC */ 1427 xf_emit (ctx, 1, 1); /* LINEAR_IN */ 1428 xf_emit (ctx, 1, 0x2); /* TILING_MODE_IN: bits 0-2 y tiling, bits 3-5 z tiling */ 1429 xf_emit (ctx, 1, 0x100); /* TILING_PITCH_IN */ 1430 xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_IN */ 1431 xf_emit (ctx, 1, 1); /* TILING_DEPTH_IN */ 1432 xf_emit (ctx, 1, 0); /* TILING_POSITION_IN_Z */ 1433 xf_emit (ctx, 1, 0); /* TILING_POSITION_IN */ 1434 xf_emit (ctx, 1, 1); /* LINEAR_OUT */ 1435 xf_emit (ctx, 1, 0x2); /* TILING_MODE_OUT: bits 0-2 y tiling, bits 3-5 z tiling */ 1436 xf_emit (ctx, 1, 0x100); /* TILING_PITCH_OUT */ 1437 xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_OUT */ 1438 xf_emit (ctx, 1, 1); /* TILING_DEPTH_OUT */ 1439 xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT_Z */ 1440 xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT */ 1441 xf_emit (ctx, 1, 0); /* OFFSET_IN_HIGH */ 1442 xf_emit (ctx, 1, 0); /* OFFSET_OUT_HIGH */ 1443 /* SEEK */ 1444 if (smallm2mf) 1445 xf_emit(ctx, 0x40, 0); /* 20 * ffffffff, 3ffff */ 1446 else 1447 xf_emit(ctx, 0x100, 0); /* 80 * ffffffff, 3ffff */ 1448 xf_emit(ctx, 4, 0); /* 1f/7f, 0, 1f/7f, 0 [1f for smallm2mf, 7f otherwise] */ 1449 /* SEEK */ 1450 if (smallm2mf) 1451 xf_emit(ctx, 0x400, 0); /* ffffffff */ 1452 else 1453 xf_emit(ctx, 0x800, 0); /* ffffffff */ 1454 xf_emit(ctx, 4, 0); /* ff/1ff, 0, 0, 0 [ff for smallm2mf, 1ff otherwise] */ 1455 /* SEEK */ 1456 xf_emit(ctx, 0x40, 0); /* 20 * bits ffffffff, 3ffff */ 1457 xf_emit(ctx, 0x6, 0); /* 1f, 0, 1f, 0, 1f, 0 */ 1458 } 1459 1460 static void 1461 nv50_gr_construct_gene_ccache(struct nouveau_grctx *ctx) 1462 { 1463 struct nouveau_device *device = ctx->device; 1464 xf_emit(ctx, 2, 0); /* RO */ 1465 xf_emit(ctx, 0x800, 0); /* ffffffff */ 1466 switch (device->chipset) { 1467 case 0x50: 1468 case 0x92: 1469 case 0xa0: 1470 xf_emit(ctx, 0x2b, 0); 1471 break; 1472 case 0x84: 1473 xf_emit(ctx, 0x29, 0); 1474 break; 1475 case 0x94: 1476 case 0x96: 1477 case 0xa3: 1478 xf_emit(ctx, 0x27, 0); 1479 break; 1480 case 0x86: 1481 case 0x98: 1482 case 0xa5: 1483 case 0xa8: 1484 case 0xaa: 1485 case 0xac: 1486 case 0xaf: 1487 xf_emit(ctx, 0x25, 0); 1488 break; 1489 } 1490 /* CB bindings, 0x80 of them. first word is address >> 8, second is 1491 * size >> 4 | valid << 24 */ 1492 xf_emit(ctx, 0x100, 0); /* ffffffff CB_DEF */ 1493 xf_emit(ctx, 1, 0); /* 0000007f CB_ADDR_BUFFER */ 1494 xf_emit(ctx, 1, 0); /* 0 */ 1495 xf_emit(ctx, 0x30, 0); /* ff SET_PROGRAM_CB */ 1496 xf_emit(ctx, 1, 0); /* 3f last SET_PROGRAM_CB */ 1497 xf_emit(ctx, 4, 0); /* RO */ 1498 xf_emit(ctx, 0x100, 0); /* ffffffff */ 1499 xf_emit(ctx, 8, 0); /* 1f, 0, 0, ... */ 1500 xf_emit(ctx, 8, 0); /* ffffffff */ 1501 xf_emit(ctx, 4, 0); /* ffffffff */ 1502 xf_emit(ctx, 1, 0); /* 3 */ 1503 xf_emit(ctx, 1, 0); /* ffffffff */ 1504 xf_emit(ctx, 1, 0); /* 0000ffff DMA_CODE_CB */ 1505 xf_emit(ctx, 1, 0); /* 0000ffff DMA_TIC */ 1506 xf_emit(ctx, 1, 0); /* 0000ffff DMA_TSC */ 1507 xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */ 1508 xf_emit(ctx, 1, 0); /* 000000ff TIC_ADDRESS_HIGH */ 1509 xf_emit(ctx, 1, 0); /* ffffffff TIC_ADDRESS_LOW */ 1510 xf_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ 1511 xf_emit(ctx, 1, 0); /* 000000ff TSC_ADDRESS_HIGH */ 1512 xf_emit(ctx, 1, 0); /* ffffffff TSC_ADDRESS_LOW */ 1513 xf_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ 1514 xf_emit(ctx, 1, 0); /* 000000ff VP_ADDRESS_HIGH */ 1515 xf_emit(ctx, 1, 0); /* ffffffff VP_ADDRESS_LOW */ 1516 xf_emit(ctx, 1, 0); /* 00ffffff VP_START_ID */ 1517 xf_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */ 1518 xf_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */ 1519 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1520 xf_emit(ctx, 1, 0); /* 000000ff GP_ADDRESS_HIGH */ 1521 xf_emit(ctx, 1, 0); /* ffffffff GP_ADDRESS_LOW */ 1522 xf_emit(ctx, 1, 0); /* 00ffffff GP_START_ID */ 1523 xf_emit(ctx, 1, 0); /* 000000ff FP_ADDRESS_HIGH */ 1524 xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */ 1525 xf_emit(ctx, 1, 0); /* 00ffffff FP_START_ID */ 1526 } 1527 1528 static void 1529 nv50_gr_construct_gene_unk10xx(struct nouveau_grctx *ctx) 1530 { 1531 struct nouveau_device *device = ctx->device; 1532 int i; 1533 /* end of area 2 on pre-NVA0, area 1 on NVAx */ 1534 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1535 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1536 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1537 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ 1538 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ 1539 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1540 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ 1541 if (device->chipset == 0x50) 1542 xf_emit(ctx, 1, 0x3ff); 1543 else 1544 xf_emit(ctx, 1, 0x7ff); /* 000007ff */ 1545 xf_emit(ctx, 1, 0); /* 111/113 */ 1546 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1547 for (i = 0; i < 8; i++) { 1548 switch (device->chipset) { 1549 case 0x50: 1550 case 0x86: 1551 case 0x98: 1552 case 0xaa: 1553 case 0xac: 1554 xf_emit(ctx, 0xa0, 0); /* ffffffff */ 1555 break; 1556 case 0x84: 1557 case 0x92: 1558 case 0x94: 1559 case 0x96: 1560 xf_emit(ctx, 0x120, 0); 1561 break; 1562 case 0xa5: 1563 case 0xa8: 1564 xf_emit(ctx, 0x100, 0); /* ffffffff */ 1565 break; 1566 case 0xa0: 1567 case 0xa3: 1568 case 0xaf: 1569 xf_emit(ctx, 0x400, 0); /* ffffffff */ 1570 break; 1571 } 1572 xf_emit(ctx, 4, 0); /* 3f, 0, 0, 0 */ 1573 xf_emit(ctx, 4, 0); /* ffffffff */ 1574 } 1575 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1576 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1577 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1578 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ 1579 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_TEMP */ 1580 xf_emit(ctx, 1, 1); /* 00000001 RASTERIZE_ENABLE */ 1581 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1582 xf_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */ 1583 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 1584 xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ 1585 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1586 } 1587 1588 static void 1589 nv50_gr_construct_gene_unk34xx(struct nouveau_grctx *ctx) 1590 { 1591 struct nouveau_device *device = ctx->device; 1592 /* end of area 2 on pre-NVA0, area 1 on NVAx */ 1593 xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */ 1594 xf_emit(ctx, 1, 0); /* 00000003 VIEWPORT_CLIP_MODE */ 1595 xf_emit(ctx, 0x10, 0x04000000); /* 07ffffff VIEWPORT_CLIP_HORIZ*8, VIEWPORT_CLIP_VERT*8 */ 1596 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */ 1597 xf_emit(ctx, 0x20, 0); /* ffffffff POLYGON_STIPPLE */ 1598 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ 1599 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 1600 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */ 1601 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */ 1602 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 1603 xf_emit(ctx, 1, 0); /* 00000007 */ 1604 xf_emit(ctx, 1, 0x1fe21); /* 0001ffff tesla UNK0FAC */ 1605 if (device->chipset >= 0xa0) 1606 xf_emit(ctx, 1, 0x0fac6881); 1607 if (IS_NVA3F(device->chipset)) { 1608 xf_emit(ctx, 1, 1); 1609 xf_emit(ctx, 3, 0); 1610 } 1611 } 1612 1613 static void 1614 nv50_gr_construct_gene_unk14xx(struct nouveau_grctx *ctx) 1615 { 1616 struct nouveau_device *device = ctx->device; 1617 /* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */ 1618 if (device->chipset != 0x50) { 1619 xf_emit(ctx, 5, 0); /* ffffffff */ 1620 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1621 xf_emit(ctx, 1, 0); /* 00000001 */ 1622 xf_emit(ctx, 1, 0); /* 000003ff */ 1623 xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */ 1624 xf_emit(ctx, 1, 0); /* 00000001 */ 1625 xf_emit(ctx, 2, 4); /* 7f, ff */ 1626 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1627 } 1628 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1629 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1630 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1631 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1632 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ 1633 xf_emit(ctx, 1, 0); /* 000000ff VP_CLIP_DISTANCE_ENABLE */ 1634 if (device->chipset != 0x50) 1635 xf_emit(ctx, 1, 0); /* 3ff */ 1636 xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1940 */ 1637 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */ 1638 xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */ 1639 xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ 1640 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 1641 if (device->chipset != 0x50) 1642 xf_emit(ctx, 1, 0x7f); /* 000000ff tesla UNK0FFC */ 1643 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1644 xf_emit(ctx, 1, 1); /* 00000001 SHADE_MODEL */ 1645 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1646 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1647 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1648 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1649 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1650 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1651 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ 1652 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */ 1653 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0F8C */ 1654 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1655 xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ 1656 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1657 xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */ 1658 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1659 xf_emit(ctx, 1, 0); /* 0000000f */ 1660 if (device->chipset == 0x50) 1661 xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */ 1662 else 1663 xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */ 1664 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1665 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ 1666 xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_SCALE: X0, Y0, Z0, X1, Y1, ... */ 1667 xf_emit(ctx, 3, 0); /* f, 0, 0 */ 1668 xf_emit(ctx, 3, 0); /* ffffffff last VIEWPORT_SCALE? */ 1669 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1670 xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ 1671 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1672 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ 1673 xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ 1674 xf_emit(ctx, 1, 0); /* 00000001 */ 1675 xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_TRANSLATE */ 1676 xf_emit(ctx, 3, 0); /* f, 0, 0 */ 1677 xf_emit(ctx, 3, 0); /* ffffffff */ 1678 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1679 xf_emit(ctx, 2, 0x88); /* 000001ff tesla UNK19D8 */ 1680 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ 1681 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1682 xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ 1683 xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ 1684 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ 1685 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 1686 xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ 1687 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 1688 xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ 1689 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1690 xf_emit(ctx, 1, 0); /* 0000000f */ 1691 xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */ 1692 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 1693 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ 1694 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 1695 if (IS_NVA3F(device->chipset)) 1696 xf_emit(ctx, 1, 0); /* 00000001 */ 1697 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 1698 xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ 1699 if (device->chipset != 0x50) { 1700 xf_emit(ctx, 1, 0); /* ffffffff */ 1701 xf_emit(ctx, 1, 0); /* 00000001 */ 1702 xf_emit(ctx, 1, 0); /* 000003ff */ 1703 } 1704 xf_emit(ctx, 0x20, 0); /* 10xbits ffffffff, 3fffff. SCISSOR_* */ 1705 xf_emit(ctx, 1, 0); /* f */ 1706 xf_emit(ctx, 1, 0); /* 0? */ 1707 xf_emit(ctx, 1, 0); /* ffffffff */ 1708 xf_emit(ctx, 1, 0); /* 003fffff */ 1709 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1710 xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */ 1711 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 1712 xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ 1713 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1714 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1715 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1716 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1717 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 1718 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ 1719 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 1720 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ 1721 xf_emit(ctx, 1, 0); /* 0000000f */ 1722 } 1723 1724 static void 1725 nv50_gr_construct_gene_zcull(struct nouveau_grctx *ctx) 1726 { 1727 struct nouveau_device *device = ctx->device; 1728 /* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */ 1729 /* SEEK */ 1730 xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */ 1731 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ 1732 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 1733 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 1734 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ 1735 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ 1736 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ 1737 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ 1738 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ 1739 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ 1740 xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */ 1741 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 1742 xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */ 1743 xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ 1744 xf_emit(ctx, 1, 0); /* 00000001 */ 1745 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ 1746 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 1747 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 1748 xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ 1749 xf_emit(ctx, 1, 0); /* 0000ffff */ 1750 xf_emit(ctx, 1, 0); /* 00000001 UNK0FB0 */ 1751 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */ 1752 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 1753 xf_emit(ctx, 1, 0); /* ffffffff */ 1754 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 1755 xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */ 1756 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ 1757 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ 1758 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ 1759 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 1760 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ 1761 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 1762 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 1763 xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ 1764 xf_emit(ctx, 1, 0); /* 00000007 */ 1765 if (device->chipset != 0x50) 1766 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1108 */ 1767 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 1768 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 1769 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 1770 xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */ 1771 /* SEEK */ 1772 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ 1773 xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ 1774 xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ 1775 xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ 1776 xf_emit(ctx, 1, 0x10); /* 7f/ff/3ff VIEW_VOLUME_CLIP_CTRL */ 1777 xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */ 1778 xf_emit(ctx, 1, 3); /* 00000003 FP_CTRL_UNK196C */ 1779 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1968 */ 1780 if (device->chipset != 0x50) 1781 xf_emit(ctx, 1, 0); /* 0fffffff tesla UNK1104 */ 1782 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK151C */ 1783 } 1784 1785 static void 1786 nv50_gr_construct_gene_clipid(struct nouveau_grctx *ctx) 1787 { 1788 /* middle of strand 0 on pre-NVA0 [after 24xx], middle of area 6 on NVAx */ 1789 /* SEEK */ 1790 xf_emit(ctx, 1, 0); /* 00000007 UNK0FB4 */ 1791 /* SEEK */ 1792 xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_HORIZ */ 1793 xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_VERT */ 1794 xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ 1795 xf_emit(ctx, 2, 0x04000000); /* 07ffffff UNK1508 */ 1796 xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */ 1797 xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_WIDTH */ 1798 xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ID */ 1799 xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ADDRESS_HIGH */ 1800 xf_emit(ctx, 1, 0); /* ffffffff CLIPID_ADDRESS_LOW */ 1801 xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_HEIGHT */ 1802 xf_emit(ctx, 1, 0); /* 0000ffff DMA_CLIPID */ 1803 } 1804 1805 static void 1806 nv50_gr_construct_gene_unk24xx(struct nouveau_grctx *ctx) 1807 { 1808 struct nouveau_device *device = ctx->device; 1809 int i; 1810 /* middle of strand 0 on pre-NVA0 [after m2mf], end of strand 2 on NVAx */ 1811 /* SEEK */ 1812 xf_emit(ctx, 0x33, 0); 1813 /* SEEK */ 1814 xf_emit(ctx, 2, 0); 1815 /* SEEK */ 1816 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1817 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1818 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1819 /* SEEK */ 1820 if (IS_NVA3F(device->chipset)) { 1821 xf_emit(ctx, 4, 0); /* RO */ 1822 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ 1823 xf_emit(ctx, 1, 0); /* 1ff */ 1824 xf_emit(ctx, 8, 0); /* 0? */ 1825 xf_emit(ctx, 9, 0); /* ffffffff, 7ff */ 1826 1827 xf_emit(ctx, 4, 0); /* RO */ 1828 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ 1829 xf_emit(ctx, 1, 0); /* 1ff */ 1830 xf_emit(ctx, 8, 0); /* 0? */ 1831 xf_emit(ctx, 9, 0); /* ffffffff, 7ff */ 1832 } else { 1833 xf_emit(ctx, 0xc, 0); /* RO */ 1834 /* SEEK */ 1835 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ 1836 xf_emit(ctx, 1, 0); /* 1ff */ 1837 xf_emit(ctx, 8, 0); /* 0? */ 1838 1839 /* SEEK */ 1840 xf_emit(ctx, 0xc, 0); /* RO */ 1841 /* SEEK */ 1842 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ 1843 xf_emit(ctx, 1, 0); /* 1ff */ 1844 xf_emit(ctx, 8, 0); /* 0? */ 1845 } 1846 /* SEEK */ 1847 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1848 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1849 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1850 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1851 if (device->chipset != 0x50) 1852 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ 1853 /* SEEK */ 1854 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1855 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1856 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ 1857 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1858 xf_emit(ctx, 1, 1); /* 00000001 */ 1859 /* SEEK */ 1860 if (device->chipset >= 0xa0) 1861 xf_emit(ctx, 2, 4); /* 000000ff */ 1862 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1863 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ 1864 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ 1865 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1866 xf_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM_ID */ 1867 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1868 xf_emit(ctx, 1, 0); /* 0000000f */ 1869 xf_emit(ctx, 1, 1); /* 00000001 */ 1870 for (i = 0; i < 10; i++) { 1871 /* SEEK */ 1872 xf_emit(ctx, 0x40, 0); /* ffffffff */ 1873 xf_emit(ctx, 0x10, 0); /* 3, 0, 0.... */ 1874 xf_emit(ctx, 0x10, 0); /* ffffffff */ 1875 } 1876 /* SEEK */ 1877 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_CTRL */ 1878 xf_emit(ctx, 1, 1); /* 00000001 */ 1879 xf_emit(ctx, 1, 0); /* ffffffff */ 1880 xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */ 1881 xf_emit(ctx, 0x10, 0); /* 00ffffff POINT_COORD_REPLACE_MAP */ 1882 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 1883 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1884 if (device->chipset != 0x50) 1885 xf_emit(ctx, 1, 0); /* 000003ff */ 1886 } 1887 1888 static void 1889 nv50_gr_construct_gene_vfetch(struct nouveau_grctx *ctx) 1890 { 1891 struct nouveau_device *device = ctx->device; 1892 int acnt = 0x10, rep, i; 1893 /* beginning of strand 1 on pre-NVA0, strand 3 on NVAx */ 1894 if (IS_NVA3F(device->chipset)) 1895 acnt = 0x20; 1896 /* SEEK */ 1897 if (device->chipset >= 0xa0) { 1898 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK13A4 */ 1899 xf_emit(ctx, 1, 1); /* 00000fff tesla UNK1318 */ 1900 } 1901 xf_emit(ctx, 1, 0); /* ffffffff VERTEX_BUFFER_FIRST */ 1902 xf_emit(ctx, 1, 0); /* 00000001 PRIMITIVE_RESTART_ENABLE */ 1903 xf_emit(ctx, 1, 0); /* 00000001 UNK0DE8 */ 1904 xf_emit(ctx, 1, 0); /* ffffffff PRIMITIVE_RESTART_INDEX */ 1905 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ 1906 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ 1907 xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATR_MASK_UNK0DD0 */ 1908 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ 1909 xf_emit(ctx, 1, 0x20); /* 0000ffff tesla UNK129C */ 1910 xf_emit(ctx, 1, 0); /* 000000ff turing UNK370??? */ 1911 xf_emit(ctx, 1, 0); /* 0000ffff turing USER_PARAM_COUNT */ 1912 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1913 /* SEEK */ 1914 if (IS_NVA3F(device->chipset)) 1915 xf_emit(ctx, 0xb, 0); /* RO */ 1916 else if (device->chipset >= 0xa0) 1917 xf_emit(ctx, 0x9, 0); /* RO */ 1918 else 1919 xf_emit(ctx, 0x8, 0); /* RO */ 1920 /* SEEK */ 1921 xf_emit(ctx, 1, 0); /* 00000001 EDGE_FLAG */ 1922 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ 1923 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1924 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 1925 /* SEEK */ 1926 xf_emit(ctx, 0xc, 0); /* RO */ 1927 /* SEEK */ 1928 xf_emit(ctx, 1, 0); /* 7f/ff */ 1929 xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ 1930 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ 1931 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ 1932 xf_emit(ctx, 1, 4); /* 000001ff UNK1A28 */ 1933 xf_emit(ctx, 1, 8); /* 000001ff UNK0DF0 */ 1934 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1935 if (device->chipset == 0x50) 1936 xf_emit(ctx, 1, 0x3ff); /* 3ff tesla UNK0D68 */ 1937 else 1938 xf_emit(ctx, 1, 0x7ff); /* 7ff tesla UNK0D68 */ 1939 if (device->chipset == 0xa8) 1940 xf_emit(ctx, 1, 0x1e00); /* 7fff */ 1941 /* SEEK */ 1942 xf_emit(ctx, 0xc, 0); /* RO or close */ 1943 /* SEEK */ 1944 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ 1945 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ 1946 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ 1947 if (device->chipset > 0x50 && device->chipset < 0xa0) 1948 xf_emit(ctx, 2, 0); /* ffffffff */ 1949 else 1950 xf_emit(ctx, 1, 0); /* ffffffff */ 1951 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0FD8 */ 1952 /* SEEK */ 1953 if (IS_NVA3F(device->chipset)) { 1954 xf_emit(ctx, 0x10, 0); /* 0? */ 1955 xf_emit(ctx, 2, 0); /* weird... */ 1956 xf_emit(ctx, 2, 0); /* RO */ 1957 } else { 1958 xf_emit(ctx, 8, 0); /* 0? */ 1959 xf_emit(ctx, 1, 0); /* weird... */ 1960 xf_emit(ctx, 2, 0); /* RO */ 1961 } 1962 /* SEEK */ 1963 xf_emit(ctx, 1, 0); /* ffffffff VB_ELEMENT_BASE */ 1964 xf_emit(ctx, 1, 0); /* ffffffff UNK1438 */ 1965 xf_emit(ctx, acnt, 0); /* 1 tesla UNK1000 */ 1966 if (device->chipset >= 0xa0) 1967 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1118? */ 1968 /* SEEK */ 1969 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */ 1970 xf_emit(ctx, 1, 0); /* f/1f */ 1971 /* SEEK */ 1972 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */ 1973 xf_emit(ctx, 1, 0); /* f/1f */ 1974 /* SEEK */ 1975 xf_emit(ctx, acnt, 0); /* RO */ 1976 xf_emit(ctx, 2, 0); /* RO */ 1977 /* SEEK */ 1978 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK111C? */ 1979 xf_emit(ctx, 1, 0); /* RO */ 1980 /* SEEK */ 1981 xf_emit(ctx, 1, 0); /* 000000ff UNK15F4_ADDRESS_HIGH */ 1982 xf_emit(ctx, 1, 0); /* ffffffff UNK15F4_ADDRESS_LOW */ 1983 xf_emit(ctx, 1, 0); /* 000000ff UNK0F84_ADDRESS_HIGH */ 1984 xf_emit(ctx, 1, 0); /* ffffffff UNK0F84_ADDRESS_LOW */ 1985 /* SEEK */ 1986 xf_emit(ctx, acnt, 0); /* 00003fff VERTEX_ARRAY_ATTRIB_OFFSET */ 1987 xf_emit(ctx, 3, 0); /* f/1f */ 1988 /* SEEK */ 1989 xf_emit(ctx, acnt, 0); /* 00000fff VERTEX_ARRAY_STRIDE */ 1990 xf_emit(ctx, 3, 0); /* f/1f */ 1991 /* SEEK */ 1992 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_LOW */ 1993 xf_emit(ctx, 3, 0); /* f/1f */ 1994 /* SEEK */ 1995 xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_ARRAY_HIGH */ 1996 xf_emit(ctx, 3, 0); /* f/1f */ 1997 /* SEEK */ 1998 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_LIMIT_LOW */ 1999 xf_emit(ctx, 3, 0); /* f/1f */ 2000 /* SEEK */ 2001 xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_LIMIT_HIGH */ 2002 xf_emit(ctx, 3, 0); /* f/1f */ 2003 /* SEEK */ 2004 if (IS_NVA3F(device->chipset)) { 2005 xf_emit(ctx, acnt, 0); /* f */ 2006 xf_emit(ctx, 3, 0); /* f/1f */ 2007 } 2008 /* SEEK */ 2009 if (IS_NVA3F(device->chipset)) 2010 xf_emit(ctx, 2, 0); /* RO */ 2011 else 2012 xf_emit(ctx, 5, 0); /* RO */ 2013 /* SEEK */ 2014 xf_emit(ctx, 1, 0); /* ffff DMA_VTXBUF */ 2015 /* SEEK */ 2016 if (device->chipset < 0xa0) { 2017 xf_emit(ctx, 0x41, 0); /* RO */ 2018 /* SEEK */ 2019 xf_emit(ctx, 0x11, 0); /* RO */ 2020 } else if (!IS_NVA3F(device->chipset)) 2021 xf_emit(ctx, 0x50, 0); /* RO */ 2022 else 2023 xf_emit(ctx, 0x58, 0); /* RO */ 2024 /* SEEK */ 2025 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ 2026 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ 2027 xf_emit(ctx, 1, 1); /* 1 UNK0DEC */ 2028 /* SEEK */ 2029 xf_emit(ctx, acnt*4, 0); /* ffffffff VTX_ATTR */ 2030 xf_emit(ctx, 4, 0); /* f/1f, 0, 0, 0 */ 2031 /* SEEK */ 2032 if (IS_NVA3F(device->chipset)) 2033 xf_emit(ctx, 0x1d, 0); /* RO */ 2034 else 2035 xf_emit(ctx, 0x16, 0); /* RO */ 2036 /* SEEK */ 2037 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ 2038 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ 2039 /* SEEK */ 2040 if (device->chipset < 0xa0) 2041 xf_emit(ctx, 8, 0); /* RO */ 2042 else if (IS_NVA3F(device->chipset)) 2043 xf_emit(ctx, 0xc, 0); /* RO */ 2044 else 2045 xf_emit(ctx, 7, 0); /* RO */ 2046 /* SEEK */ 2047 xf_emit(ctx, 0xa, 0); /* RO */ 2048 if (device->chipset == 0xa0) 2049 rep = 0xc; 2050 else 2051 rep = 4; 2052 for (i = 0; i < rep; i++) { 2053 /* SEEK */ 2054 if (IS_NVA3F(device->chipset)) 2055 xf_emit(ctx, 0x20, 0); /* ffffffff */ 2056 xf_emit(ctx, 0x200, 0); /* ffffffff */ 2057 xf_emit(ctx, 4, 0); /* 7f/ff, 0, 0, 0 */ 2058 xf_emit(ctx, 4, 0); /* ffffffff */ 2059 } 2060 /* SEEK */ 2061 xf_emit(ctx, 1, 0); /* 113/111 */ 2062 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ 2063 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ 2064 xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATTR_MASK_UNK0DD0 */ 2065 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ 2066 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2067 /* SEEK */ 2068 if (IS_NVA3F(device->chipset)) 2069 xf_emit(ctx, 7, 0); /* weird... */ 2070 else 2071 xf_emit(ctx, 5, 0); /* weird... */ 2072 } 2073 2074 static void 2075 nv50_gr_construct_gene_eng2d(struct nouveau_grctx *ctx) 2076 { 2077 struct nouveau_device *device = ctx->device; 2078 /* middle of strand 1 on pre-NVA0 [after vfetch], middle of strand 6 on NVAx */ 2079 /* SEEK */ 2080 xf_emit(ctx, 2, 0); /* 0001ffff CLIP_X, CLIP_Y */ 2081 xf_emit(ctx, 2, 0); /* 0000ffff CLIP_W, CLIP_H */ 2082 xf_emit(ctx, 1, 0); /* 00000001 CLIP_ENABLE */ 2083 if (device->chipset < 0xa0) { 2084 /* this is useless on everything but the original NV50, 2085 * guess they forgot to nuke it. Or just didn't bother. */ 2086 xf_emit(ctx, 2, 0); /* 0000ffff IFC_CLIP_X, Y */ 2087 xf_emit(ctx, 2, 1); /* 0000ffff IFC_CLIP_W, H */ 2088 xf_emit(ctx, 1, 0); /* 00000001 IFC_CLIP_ENABLE */ 2089 } 2090 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2091 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */ 2092 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */ 2093 xf_emit(ctx, 1, 0x11); /* 3f[NV50]/7f[NV84+] DST_FORMAT */ 2094 xf_emit(ctx, 1, 0); /* 0001ffff DRAW_POINT_X */ 2095 xf_emit(ctx, 1, 8); /* 0000000f DRAW_UNK58C */ 2096 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_X_FRACT */ 2097 xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_X_INT */ 2098 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_Y_FRACT */ 2099 xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_Y_INT */ 2100 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DX_DU_FRACT */ 2101 xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DX_DU_INT */ 2102 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DY_DV_FRACT */ 2103 xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DY_DV_INT */ 2104 xf_emit(ctx, 1, 1); /* 0000ffff SIFC_WIDTH */ 2105 xf_emit(ctx, 1, 1); /* 0000ffff SIFC_HEIGHT */ 2106 xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */ 2107 xf_emit(ctx, 1, 2); /* 00000003 SIFC_BITMAP_UNK808 */ 2108 xf_emit(ctx, 1, 0); /* 00000003 SIFC_BITMAP_LINE_PACK_MODE */ 2109 xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_LSB_FIRST */ 2110 xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_ENABLE */ 2111 xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_X */ 2112 xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_Y */ 2113 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */ 2114 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */ 2115 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */ 2116 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */ 2117 xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_W */ 2118 xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_H */ 2119 xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_X_FRACT */ 2120 xf_emit(ctx, 1, 0); /* 0001ffff BLIT_SRC_X_INT */ 2121 xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_Y_FRACT */ 2122 xf_emit(ctx, 1, 0); /* 00000001 UNK888 */ 2123 xf_emit(ctx, 1, 4); /* 0000003f UNK884 */ 2124 xf_emit(ctx, 1, 0); /* 00000007 UNK880 */ 2125 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK0FB8 */ 2126 xf_emit(ctx, 1, 0x15); /* 000000ff tesla UNK128C */ 2127 xf_emit(ctx, 2, 0); /* 00000007, ffff0ff3 */ 2128 xf_emit(ctx, 1, 0); /* 00000001 UNK260 */ 2129 xf_emit(ctx, 1, 0x4444480); /* 1fffffff UNK870 */ 2130 /* SEEK */ 2131 xf_emit(ctx, 0x10, 0); 2132 /* SEEK */ 2133 xf_emit(ctx, 0x27, 0); 2134 } 2135 2136 static void 2137 nv50_gr_construct_gene_csched(struct nouveau_grctx *ctx) 2138 { 2139 struct nouveau_device *device = ctx->device; 2140 /* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */ 2141 /* SEEK */ 2142 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY... what is it doing here??? */ 2143 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ 2144 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 2145 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 2146 xf_emit(ctx, 1, 0); /* 000003ff */ 2147 /* SEEK */ 2148 xf_emit(ctx, 1, 0); /* ffffffff turing UNK364 */ 2149 xf_emit(ctx, 1, 0); /* 0000000f turing UNK36C */ 2150 xf_emit(ctx, 1, 0); /* 0000ffff USER_PARAM_COUNT */ 2151 xf_emit(ctx, 1, 0x100); /* 00ffffff turing UNK384 */ 2152 xf_emit(ctx, 1, 0); /* 0000000f turing UNK2A0 */ 2153 xf_emit(ctx, 1, 0); /* 0000ffff GRIDID */ 2154 xf_emit(ctx, 1, 0x10001); /* ffffffff GRIDDIM_XY */ 2155 xf_emit(ctx, 1, 0); /* ffffffff */ 2156 xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */ 2157 xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */ 2158 xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */ 2159 xf_emit(ctx, 1, 1); /* 00000001 LANES32 */ 2160 xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ 2161 xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ 2162 /* SEEK */ 2163 xf_emit(ctx, 0x40, 0); /* ffffffff USER_PARAM */ 2164 switch (device->chipset) { 2165 case 0x50: 2166 case 0x92: 2167 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2168 xf_emit(ctx, 0x80, 0); /* fff */ 2169 xf_emit(ctx, 2, 0); /* ff, fff */ 2170 xf_emit(ctx, 0x10*2, 0); /* ffffffff, 1f */ 2171 break; 2172 case 0x84: 2173 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2174 xf_emit(ctx, 0x60, 0); /* fff */ 2175 xf_emit(ctx, 2, 0); /* ff, fff */ 2176 xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */ 2177 break; 2178 case 0x94: 2179 case 0x96: 2180 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2181 xf_emit(ctx, 0x40, 0); /* fff */ 2182 xf_emit(ctx, 2, 0); /* ff, fff */ 2183 xf_emit(ctx, 8*2, 0); /* ffffffff, 1f */ 2184 break; 2185 case 0x86: 2186 case 0x98: 2187 xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */ 2188 xf_emit(ctx, 0x10, 0); /* fff */ 2189 xf_emit(ctx, 2, 0); /* ff, fff */ 2190 xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */ 2191 break; 2192 case 0xa0: 2193 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2194 xf_emit(ctx, 0xf0, 0); /* fff */ 2195 xf_emit(ctx, 2, 0); /* ff, fff */ 2196 xf_emit(ctx, 0x1e*2, 0); /* ffffffff, 1f */ 2197 break; 2198 case 0xa3: 2199 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2200 xf_emit(ctx, 0x60, 0); /* fff */ 2201 xf_emit(ctx, 2, 0); /* ff, fff */ 2202 xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */ 2203 break; 2204 case 0xa5: 2205 case 0xaf: 2206 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2207 xf_emit(ctx, 0x30, 0); /* fff */ 2208 xf_emit(ctx, 2, 0); /* ff, fff */ 2209 xf_emit(ctx, 6*2, 0); /* ffffffff, 1f */ 2210 break; 2211 case 0xaa: 2212 xf_emit(ctx, 0x12, 0); 2213 break; 2214 case 0xa8: 2215 case 0xac: 2216 xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */ 2217 xf_emit(ctx, 0x10, 0); /* fff */ 2218 xf_emit(ctx, 2, 0); /* ff, fff */ 2219 xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */ 2220 break; 2221 } 2222 xf_emit(ctx, 1, 0); /* 0000000f */ 2223 xf_emit(ctx, 1, 0); /* 00000000 */ 2224 xf_emit(ctx, 1, 0); /* ffffffff */ 2225 xf_emit(ctx, 1, 0); /* 0000001f */ 2226 xf_emit(ctx, 4, 0); /* ffffffff */ 2227 xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */ 2228 xf_emit(ctx, 1, 0); /* ffffffff */ 2229 xf_emit(ctx, 4, 0); /* ffffffff */ 2230 xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */ 2231 xf_emit(ctx, 1, 0); /* ffffffff */ 2232 xf_emit(ctx, 1, 0); /* 000000ff */ 2233 } 2234 2235 static void 2236 nv50_gr_construct_gene_unk1cxx(struct nouveau_grctx *ctx) 2237 { 2238 struct nouveau_device *device = ctx->device; 2239 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ 2240 xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */ 2241 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ 2242 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */ 2243 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */ 2244 xf_emit(ctx, 3, 0); /* 00000001 POLYGON_OFFSET_*_ENABLE */ 2245 xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ 2246 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 2247 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2248 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ 2249 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */ 2250 xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ 2251 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2252 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 2253 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ 2254 xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_UNITS */ 2255 xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_FACTOR */ 2256 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */ 2257 xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ 2258 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 2259 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2260 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2261 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2262 xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */ 2263 xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */ 2264 xf_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_LINEAR */ 2265 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 2266 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ 2267 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ 2268 if (IS_NVA3F(device->chipset)) 2269 xf_emit(ctx, 1, 3); /* 00000003 UNK16B4 */ 2270 else if (device->chipset >= 0xa0) 2271 xf_emit(ctx, 1, 1); /* 00000001 UNK16B4 */ 2272 xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ 2273 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */ 2274 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ 2275 xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */ 2276 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 2277 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2278 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 2279 xf_emit(ctx, 1, 5); /* 0000000f UNK1408 */ 2280 xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */ 2281 xf_emit(ctx, 1, 0); /* ffffffff POINT_SIZE */ 2282 xf_emit(ctx, 1, 0); /* 00000001 */ 2283 xf_emit(ctx, 1, 0); /* 00000007 tesla UNK0FB4 */ 2284 if (device->chipset != 0x50) { 2285 xf_emit(ctx, 1, 0); /* 3ff */ 2286 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK1110 */ 2287 } 2288 if (IS_NVA3F(device->chipset)) 2289 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */ 2290 xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ 2291 xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ 2292 xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ 2293 xf_emit(ctx, 0x20, 0); /* 07ffffff VIEWPORT_HORIZ, then VIEWPORT_VERT. (W&0x3fff)<<13 | (X&0x1fff). */ 2294 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK187C */ 2295 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 2296 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2297 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2298 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2299 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ 2300 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 2301 xf_emit(ctx, 1, 5); /* 0000000f tesla UNK1220 */ 2302 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2303 xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1A20 */ 2304 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2305 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ 2306 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ 2307 if (device->chipset != 0x50) 2308 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ 2309 if (device->chipset < 0xa0) 2310 xf_emit(ctx, 0x1c, 0); /* RO */ 2311 else if (IS_NVA3F(device->chipset)) 2312 xf_emit(ctx, 0x9, 0); 2313 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ 2314 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ 2315 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 2316 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ 2317 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 2318 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 2319 if (device->chipset != 0x50) { 2320 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ 2321 xf_emit(ctx, 1, 0); /* 3ff */ 2322 } 2323 /* XXX: the following block could belong either to unk1cxx, or 2324 * to STRMOUT. Rather hard to tell. */ 2325 if (device->chipset < 0xa0) 2326 xf_emit(ctx, 0x25, 0); 2327 else 2328 xf_emit(ctx, 0x3b, 0); 2329 } 2330 2331 static void 2332 nv50_gr_construct_gene_strmout(struct nouveau_grctx *ctx) 2333 { 2334 struct nouveau_device *device = ctx->device; 2335 xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */ 2336 xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */ 2337 xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */ 2338 if (device->chipset >= 0xa0) { 2339 xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */ 2340 xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */ 2341 } 2342 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 2343 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 2344 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2345 if (device->chipset == 0x50) 2346 xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */ 2347 else 2348 xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */ 2349 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2350 /* SEEK */ 2351 xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */ 2352 xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */ 2353 xf_emit(ctx, 4, 0); /* 000000ff STRMOUT_ADDRESS_HIGH */ 2354 xf_emit(ctx, 4, 0); /* ffffffff STRMOUT_ADDRESS_LOW */ 2355 xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */ 2356 if (device->chipset >= 0xa0) { 2357 xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */ 2358 xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */ 2359 } 2360 xf_emit(ctx, 1, 0); /* 0000ffff DMA_STRMOUT */ 2361 xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ 2362 xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ 2363 xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW QUERY_COUNTER */ 2364 xf_emit(ctx, 2, 0); /* ffffffff */ 2365 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2366 /* SEEK */ 2367 xf_emit(ctx, 0x20, 0); /* ffffffff STRMOUT_MAP */ 2368 xf_emit(ctx, 1, 0); /* 0000000f */ 2369 xf_emit(ctx, 1, 0); /* 00000000? */ 2370 xf_emit(ctx, 2, 0); /* ffffffff */ 2371 } 2372 2373 static void 2374 nv50_gr_construct_gene_ropm1(struct nouveau_grctx *ctx) 2375 { 2376 struct nouveau_device *device = ctx->device; 2377 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */ 2378 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */ 2379 xf_emit(ctx, 1, 0); /* 00000007 */ 2380 xf_emit(ctx, 1, 0); /* 000003ff */ 2381 if (IS_NVA3F(device->chipset)) 2382 xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */ 2383 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2384 } 2385 2386 static void 2387 nv50_gr_construct_gene_ropm2(struct nouveau_grctx *ctx) 2388 { 2389 struct nouveau_device *device = ctx->device; 2390 /* SEEK */ 2391 xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ 2392 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2393 xf_emit(ctx, 2, 0); /* ffffffff */ 2394 xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ 2395 xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */ 2396 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 2397 xf_emit(ctx, 1, 0); /* 7 */ 2398 /* SEEK */ 2399 xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ 2400 xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ 2401 xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */ 2402 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */ 2403 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */ 2404 xf_emit(ctx, 1, 0); /* 00000001 eng2d UNK260 */ 2405 xf_emit(ctx, 1, 0); /* ff/3ff */ 2406 xf_emit(ctx, 1, 0); /* 00000007 */ 2407 if (IS_NVA3F(device->chipset)) 2408 xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */ 2409 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2410 } 2411 2412 static void 2413 nv50_gr_construct_gene_ropc(struct nouveau_grctx *ctx) 2414 { 2415 struct nouveau_device *device = ctx->device; 2416 int magic2; 2417 if (device->chipset == 0x50) { 2418 magic2 = 0x00003e60; 2419 } else if (!IS_NVA3F(device->chipset)) { 2420 magic2 = 0x001ffe67; 2421 } else { 2422 magic2 = 0x00087e67; 2423 } 2424 xf_emit(ctx, 1, 0); /* f/7 MUTISAMPLE_SAMPLES_LOG2 */ 2425 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2426 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ 2427 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ 2428 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ 2429 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ 2430 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ 2431 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2432 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ 2433 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2434 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ 2435 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2436 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2437 if (IS_NVA3F(device->chipset)) 2438 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2439 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ 2440 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ 2441 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 2442 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ 2443 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2444 if (device->chipset >= 0xa0 && !IS_NVAAF(device->chipset)) 2445 xf_emit(ctx, 1, 0x15); /* 000000ff */ 2446 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2447 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2448 xf_emit(ctx, 1, 0x10); /* 3ff/ff VIEW_VOLUME_CLIP_CTRL */ 2449 xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ 2450 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2451 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2452 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2453 if (device->chipset == 0x86 || device->chipset == 0x92 || device->chipset == 0x98 || device->chipset >= 0xa0) { 2454 xf_emit(ctx, 3, 0); /* ff, ffffffff, ffffffff */ 2455 xf_emit(ctx, 1, 4); /* 7 */ 2456 xf_emit(ctx, 1, 0x400); /* fffffff */ 2457 xf_emit(ctx, 1, 0x300); /* ffff */ 2458 xf_emit(ctx, 1, 0x1001); /* 1fff */ 2459 if (device->chipset != 0xa0) { 2460 if (IS_NVA3F(device->chipset)) 2461 xf_emit(ctx, 1, 0); /* 0000000f UNK15C8 */ 2462 else 2463 xf_emit(ctx, 1, 0x15); /* ff */ 2464 } 2465 } 2466 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2467 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2468 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ 2469 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ 2470 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2471 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ 2472 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2473 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ 2474 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2475 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2476 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ 2477 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ 2478 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2479 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2480 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2481 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ 2482 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2483 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2484 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2485 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2486 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 2487 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ 2488 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ 2489 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ 2490 xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ 2491 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2492 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ 2493 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2494 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2495 xf_emit(ctx, 1, 0); /* 0000000f */ 2496 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ 2497 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ 2498 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ 2499 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ 2500 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2501 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2502 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ 2503 xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ 2504 xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ 2505 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2506 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2507 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ 2508 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ 2509 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ 2510 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ 2511 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ 2512 xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ 2513 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2514 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ 2515 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2516 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2517 xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */ 2518 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ 2519 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ 2520 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ 2521 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 2522 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ 2523 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2524 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2525 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ 2526 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2527 xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */ 2528 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2529 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2530 xf_emit(ctx, 2, 0); /* ffff0ff3, ffff */ 2531 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ 2532 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 2533 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2534 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2535 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2536 xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ 2537 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ 2538 if (device->chipset >= 0xa0) { 2539 xf_emit(ctx, 2, 0); 2540 xf_emit(ctx, 1, 0x1001); 2541 xf_emit(ctx, 0xb, 0); 2542 } else { 2543 xf_emit(ctx, 1, 0); /* 00000007 */ 2544 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2545 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2546 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 2547 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2548 } 2549 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2550 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2551 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2552 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2553 xf_emit(ctx, 1, 0x11); /* 3f/7f */ 2554 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 2555 if (device->chipset != 0x50) { 2556 xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */ 2557 xf_emit(ctx, 1, 0); /* 000000ff */ 2558 } 2559 xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ 2560 xf_emit(ctx, 1, 0); /* ff/3ff */ 2561 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ 2562 xf_emit(ctx, 2, 1); /* 00000007 BLEND_EQUATION_RGB, ALPHA */ 2563 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ 2564 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ 2565 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ 2566 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ 2567 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ 2568 xf_emit(ctx, 1, 0); /* 00000001 */ 2569 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ 2570 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2571 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2572 if (IS_NVA3F(device->chipset)) { 2573 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK12E4 */ 2574 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ 2575 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ 2576 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ 2577 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ 2578 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ 2579 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ 2580 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ 2581 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */ 2582 xf_emit(ctx, 2, 0); /* 00000001 */ 2583 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2584 xf_emit(ctx, 1, 0); /* 0000000f */ 2585 xf_emit(ctx, 1, 0); /* 00000003 */ 2586 xf_emit(ctx, 1, 0); /* ffffffff */ 2587 xf_emit(ctx, 2, 0); /* 00000001 */ 2588 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2589 xf_emit(ctx, 1, 0); /* 00000001 */ 2590 xf_emit(ctx, 1, 0); /* 000003ff */ 2591 } else if (device->chipset >= 0xa0) { 2592 xf_emit(ctx, 2, 0); /* 00000001 */ 2593 xf_emit(ctx, 1, 0); /* 00000007 */ 2594 xf_emit(ctx, 1, 0); /* 00000003 */ 2595 xf_emit(ctx, 1, 0); /* ffffffff */ 2596 xf_emit(ctx, 2, 0); /* 00000001 */ 2597 } else { 2598 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2599 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1430 */ 2600 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2601 } 2602 xf_emit(ctx, 4, 0); /* ffffffff CLEAR_COLOR */ 2603 xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR A R G B */ 2604 xf_emit(ctx, 1, 0); /* 00000fff eng2d UNK2B0 */ 2605 if (device->chipset >= 0xa0) 2606 xf_emit(ctx, 2, 0); /* 00000001 */ 2607 xf_emit(ctx, 1, 0); /* 000003ff */ 2608 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 2609 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ 2610 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ 2611 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ 2612 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ 2613 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ 2614 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ 2615 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ 2616 xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */ 2617 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 2618 xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */ 2619 if (device->chipset >= 0xa0) 2620 xf_emit(ctx, 1, 0); /* 00000001 UNK12E4? NVA3+ only? */ 2621 if (IS_NVA3F(device->chipset)) { 2622 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ 2623 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ 2624 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ 2625 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ 2626 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ 2627 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ 2628 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ 2629 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK15C4 */ 2630 xf_emit(ctx, 1, 0); /* 00000001 */ 2631 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */ 2632 } 2633 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2634 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2635 xf_emit(ctx, 1, 0); /* 00000007 PATTERN_COLOR_FORMAT */ 2636 xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_COLOR */ 2637 xf_emit(ctx, 1, 0); /* 00000001 PATTERN_MONO_FORMAT */ 2638 xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_BITMAP */ 2639 xf_emit(ctx, 1, 0); /* 00000003 PATTERN_SELECT */ 2640 xf_emit(ctx, 1, 0); /* 000000ff ROP */ 2641 xf_emit(ctx, 1, 0); /* ffffffff BETA1 */ 2642 xf_emit(ctx, 1, 0); /* ffffffff BETA4 */ 2643 xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ 2644 xf_emit(ctx, 0x50, 0); /* 10x ffffff, ffffff, ffffff, ffffff, 3 PATTERN */ 2645 } 2646 2647 static void 2648 nv50_gr_construct_xfer_unk84xx(struct nouveau_grctx *ctx) 2649 { 2650 struct nouveau_device *device = ctx->device; 2651 int magic3; 2652 switch (device->chipset) { 2653 case 0x50: 2654 magic3 = 0x1000; 2655 break; 2656 case 0x86: 2657 case 0x98: 2658 case 0xa8: 2659 case 0xaa: 2660 case 0xac: 2661 case 0xaf: 2662 magic3 = 0x1e00; 2663 break; 2664 default: 2665 magic3 = 0; 2666 } 2667 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2668 xf_emit(ctx, 1, 4); /* 7f/ff[NVA0+] VP_REG_ALLOC_RESULT */ 2669 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2670 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2671 xf_emit(ctx, 1, 0); /* 111/113[NVA0+] */ 2672 if (IS_NVA3F(device->chipset)) 2673 xf_emit(ctx, 0x1f, 0); /* ffffffff */ 2674 else if (device->chipset >= 0xa0) 2675 xf_emit(ctx, 0x0f, 0); /* ffffffff */ 2676 else 2677 xf_emit(ctx, 0x10, 0); /* fffffff VP_RESULT_MAP_1 up */ 2678 xf_emit(ctx, 2, 0); /* f/1f[NVA3], fffffff/ffffffff[NVA0+] */ 2679 xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ 2680 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ 2681 if (device->chipset >= 0xa0) 2682 xf_emit(ctx, 1, 0x03020100); /* ffffffff */ 2683 else 2684 xf_emit(ctx, 1, 0x00608080); /* fffffff VP_RESULT_MAP_0 */ 2685 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2686 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2687 xf_emit(ctx, 2, 0); /* 111/113, 7f/ff */ 2688 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ 2689 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2690 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2691 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ 2692 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 2693 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ 2694 if (magic3) 2695 xf_emit(ctx, 1, magic3); /* 00007fff tesla UNK141C */ 2696 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ 2697 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2698 xf_emit(ctx, 1, 0); /* 111/113 */ 2699 xf_emit(ctx, 0x1f, 0); /* ffffffff GP_RESULT_MAP_1 up */ 2700 xf_emit(ctx, 1, 0); /* 0000001f */ 2701 xf_emit(ctx, 1, 0); /* ffffffff */ 2702 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2703 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ 2704 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ 2705 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 2706 xf_emit(ctx, 1, 0x03020100); /* ffffffff GP_RESULT_MAP_0 */ 2707 xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ 2708 if (magic3) 2709 xf_emit(ctx, 1, magic3); /* 7fff tesla UNK141C */ 2710 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ 2711 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ 2712 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2713 xf_emit(ctx, 1, 0); /* 111/113 */ 2714 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2715 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 2716 xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ 2717 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ 2718 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2719 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK13A0 */ 2720 xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ 2721 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2722 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2723 xf_emit(ctx, 1, 0); /* 111/113 */ 2724 if (device->chipset == 0x94 || device->chipset == 0x96) 2725 xf_emit(ctx, 0x1020, 0); /* 4 x (0x400 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */ 2726 else if (device->chipset < 0xa0) 2727 xf_emit(ctx, 0xa20, 0); /* 4 x (0x280 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */ 2728 else if (!IS_NVA3F(device->chipset)) 2729 xf_emit(ctx, 0x210, 0); /* ffffffff */ 2730 else 2731 xf_emit(ctx, 0x410, 0); /* ffffffff */ 2732 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2733 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 2734 xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ 2735 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ 2736 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2737 } 2738 2739 static void 2740 nv50_gr_construct_xfer_tprop(struct nouveau_grctx *ctx) 2741 { 2742 struct nouveau_device *device = ctx->device; 2743 int magic1, magic2; 2744 if (device->chipset == 0x50) { 2745 magic1 = 0x3ff; 2746 magic2 = 0x00003e60; 2747 } else if (!IS_NVA3F(device->chipset)) { 2748 magic1 = 0x7ff; 2749 magic2 = 0x001ffe67; 2750 } else { 2751 magic1 = 0x7ff; 2752 magic2 = 0x00087e67; 2753 } 2754 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ 2755 xf_emit(ctx, 1, 0); /* ffffffff ALPHA_TEST_REF */ 2756 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ 2757 if (IS_NVA3F(device->chipset)) 2758 xf_emit(ctx, 1, 1); /* 0000000f UNK16A0 */ 2759 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2760 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2761 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ 2762 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ 2763 xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR */ 2764 xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */ 2765 xf_emit(ctx, 1, 0); /* 00000001 UNK0FDC */ 2766 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2767 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2768 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2769 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2770 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 2771 xf_emit(ctx, 1, 0); /* ff[NV50]/3ff[NV84+] */ 2772 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 2773 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ 2774 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 2775 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ 2776 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2777 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2778 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ 2779 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ 2780 xf_emit(ctx, 1, 0); /* 7 */ 2781 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 2782 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2783 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2784 xf_emit(ctx, 1, 0); /* ffffffff COLOR_KEY */ 2785 xf_emit(ctx, 1, 0); /* 00000001 COLOR_KEY_ENABLE */ 2786 xf_emit(ctx, 1, 0); /* 00000007 COLOR_KEY_FORMAT */ 2787 xf_emit(ctx, 2, 0); /* ffffffff SIFC_BITMAP_COLOR */ 2788 xf_emit(ctx, 1, 1); /* 00000001 SIFC_BITMAP_WRITE_BIT0_ENABLE */ 2789 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ 2790 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ 2791 if (IS_NVA3F(device->chipset)) { 2792 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */ 2793 xf_emit(ctx, 1, 0); /* 00000003 */ 2794 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1298 */ 2795 } else if (device->chipset >= 0xa0) { 2796 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK16B4 */ 2797 xf_emit(ctx, 1, 0); /* 00000003 */ 2798 } else { 2799 xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ 2800 } 2801 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2802 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 2803 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ 2804 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ 2805 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ 2806 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ 2807 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ 2808 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ 2809 if (IS_NVA3F(device->chipset)) { 2810 xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */ 2811 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ 2812 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ 2813 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ 2814 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_RGB */ 2815 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_RGB */ 2816 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_ALPHA */ 2817 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_ALPHA */ 2818 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ 2819 } 2820 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ 2821 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2822 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2823 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2824 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2825 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 2826 xf_emit(ctx, 1, 0); /* ff/3ff */ 2827 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 2828 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ 2829 xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ 2830 xf_emit(ctx, 1, 0); /* 7 */ 2831 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2832 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2833 xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ 2834 xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */ 2835 xf_emit(ctx, 1, 0xcf); /* 000000ff DRAW_COLOR_FORMAT */ 2836 xf_emit(ctx, 1, 0xcf); /* 000000ff SRC_FORMAT */ 2837 if (IS_NVA3F(device->chipset)) 2838 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2839 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2840 xf_emit(ctx, 1, 0); /* 7/f[NVA3] MULTISAMPLE_SAMPLES_LOG2 */ 2841 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 2842 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ 2843 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ 2844 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ 2845 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ 2846 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ 2847 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ 2848 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ 2849 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2850 xf_emit(ctx, 8, 1); /* 00000001 UNK19E0 */ 2851 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2852 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2853 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2854 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2855 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2856 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ 2857 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2858 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2859 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2860 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2861 if (IS_NVA3F(device->chipset)) 2862 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2863 if (device->chipset == 0x50) 2864 xf_emit(ctx, 1, 0); /* ff */ 2865 else 2866 xf_emit(ctx, 3, 0); /* 1, 7, 3ff */ 2867 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 2868 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ 2869 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2870 xf_emit(ctx, 1, 0); /* 00000007 */ 2871 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 2872 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2873 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2874 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2875 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2876 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2877 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2878 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2879 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2880 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2881 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2882 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2883 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2884 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2885 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2886 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */ 2887 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */ 2888 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */ 2889 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */ 2890 xf_emit(ctx, 1, 0); /* ff/3ff */ 2891 xf_emit(ctx, 1, magic1); /* 3ff/7ff tesla UNK0D68 */ 2892 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2893 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2894 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2895 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2896 xf_emit(ctx, 1, 0); /* 00000007 */ 2897 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2898 if (IS_NVA3F(device->chipset)) 2899 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2900 xf_emit(ctx, 8, 0); /* 0000ffff DMA_COLOR */ 2901 xf_emit(ctx, 1, 0); /* 0000ffff DMA_GLOBAL */ 2902 xf_emit(ctx, 1, 0); /* 0000ffff DMA_LOCAL */ 2903 xf_emit(ctx, 1, 0); /* 0000ffff DMA_STACK */ 2904 xf_emit(ctx, 1, 0); /* ff/3ff */ 2905 xf_emit(ctx, 1, 0); /* 0000ffff DMA_DST */ 2906 xf_emit(ctx, 1, 0); /* 7 */ 2907 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2908 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2909 xf_emit(ctx, 8, 0); /* 000000ff RT_ADDRESS_HIGH */ 2910 xf_emit(ctx, 8, 0); /* ffffffff RT_LAYER_STRIDE */ 2911 xf_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */ 2912 xf_emit(ctx, 8, 8); /* 0000007f RT_TILE_MODE */ 2913 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2914 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2915 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2916 xf_emit(ctx, 8, 0x400); /* 0fffffff RT_HORIZ */ 2917 xf_emit(ctx, 8, 0x300); /* 0000ffff RT_VERT */ 2918 xf_emit(ctx, 1, 1); /* 00001fff RT_ARRAY_MODE */ 2919 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2920 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2921 xf_emit(ctx, 1, 0x20); /* 00000fff DST_TILE_MODE */ 2922 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2923 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */ 2924 xf_emit(ctx, 1, 0); /* 000007ff DST_LAYER */ 2925 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2926 xf_emit(ctx, 1, 0); /* ffffffff DST_ADDRESS_LOW */ 2927 xf_emit(ctx, 1, 0); /* 000000ff DST_ADDRESS_HIGH */ 2928 xf_emit(ctx, 1, 0x40); /* 0007ffff DST_PITCH */ 2929 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */ 2930 xf_emit(ctx, 1, 0); /* 0000ffff */ 2931 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK15AC */ 2932 xf_emit(ctx, 1, 0); /* ff/3ff */ 2933 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 2934 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ 2935 xf_emit(ctx, 1, 0); /* 00000007 */ 2936 if (IS_NVA3F(device->chipset)) 2937 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2938 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ 2939 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2940 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2941 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2942 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ 2943 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2944 xf_emit(ctx, 1, 0); /* 0000ffff DMA_ZETA */ 2945 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2946 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2947 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2948 xf_emit(ctx, 2, 0); /* ffff, ff/3ff */ 2949 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 2950 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2951 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 2952 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2953 xf_emit(ctx, 1, 0); /* 00000007 */ 2954 xf_emit(ctx, 1, 0); /* ffffffff ZETA_LAYER_STRIDE */ 2955 xf_emit(ctx, 1, 0); /* 000000ff ZETA_ADDRESS_HIGH */ 2956 xf_emit(ctx, 1, 0); /* ffffffff ZETA_ADDRESS_LOW */ 2957 xf_emit(ctx, 1, 4); /* 00000007 ZETA_TILE_MODE */ 2958 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2959 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2960 xf_emit(ctx, 1, 0x400); /* 0fffffff ZETA_HORIZ */ 2961 xf_emit(ctx, 1, 0x300); /* 0000ffff ZETA_VERT */ 2962 xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */ 2963 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2964 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2965 if (IS_NVA3F(device->chipset)) 2966 xf_emit(ctx, 1, 0); /* 00000001 */ 2967 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2968 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2969 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2970 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2971 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2972 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2973 xf_emit(ctx, 1, 0); /* ff/3ff */ 2974 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 2975 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ 2976 xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ 2977 xf_emit(ctx, 1, 0); /* 7 */ 2978 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 2979 if (IS_NVA3F(device->chipset)) { 2980 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ 2981 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2982 } 2983 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2984 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ 2985 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2986 if (device->chipset >= 0xa0) 2987 xf_emit(ctx, 1, 0x0fac6881); /* fffffff */ 2988 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ 2989 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2990 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2991 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2992 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2993 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ 2994 xf_emit(ctx, 1, 0); /* ff/3ff */ 2995 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 2996 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2997 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2998 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ 2999 xf_emit(ctx, 1, 0); /* 00000007 */ 3000 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 3001 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 3002 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 3003 if (IS_NVA3F(device->chipset)) { 3004 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 3005 xf_emit(ctx, 1, 0); /* 0000000f tesla UNK15C8 */ 3006 } 3007 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 3008 if (device->chipset >= 0xa0) { 3009 xf_emit(ctx, 3, 0); /* 7/f, 1, ffff0ff3 */ 3010 xf_emit(ctx, 1, 0xfac6881); /* fffffff */ 3011 xf_emit(ctx, 4, 0); /* 1, 1, 1, 3ff */ 3012 xf_emit(ctx, 1, 4); /* 7 */ 3013 xf_emit(ctx, 1, 0); /* 1 */ 3014 xf_emit(ctx, 2, 1); /* 1 */ 3015 xf_emit(ctx, 2, 0); /* 7, f */ 3016 xf_emit(ctx, 1, 1); /* 1 */ 3017 xf_emit(ctx, 1, 0); /* 7/f */ 3018 if (IS_NVA3F(device->chipset)) 3019 xf_emit(ctx, 0x9, 0); /* 1 */ 3020 else 3021 xf_emit(ctx, 0x8, 0); /* 1 */ 3022 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 3023 xf_emit(ctx, 8, 1); /* 1 */ 3024 xf_emit(ctx, 1, 0x11); /* 7f */ 3025 xf_emit(ctx, 7, 0); /* 7f */ 3026 xf_emit(ctx, 1, 0xfac6881); /* fffffff */ 3027 xf_emit(ctx, 1, 0xf); /* f */ 3028 xf_emit(ctx, 7, 0); /* f */ 3029 xf_emit(ctx, 1, 0x11); /* 7f */ 3030 xf_emit(ctx, 1, 1); /* 1 */ 3031 xf_emit(ctx, 5, 0); /* 1, 7, 3ff, 3, 7 */ 3032 if (IS_NVA3F(device->chipset)) { 3033 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ 3034 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 3035 } 3036 } 3037 } 3038 3039 static void 3040 nv50_gr_construct_xfer_tex(struct nouveau_grctx *ctx) 3041 { 3042 struct nouveau_device *device = ctx->device; 3043 xf_emit(ctx, 2, 0); /* 1 LINKED_TSC. yes, 2. */ 3044 if (device->chipset != 0x50) 3045 xf_emit(ctx, 1, 0); /* 3 */ 3046 xf_emit(ctx, 1, 1); /* 1ffff BLIT_DU_DX_INT */ 3047 xf_emit(ctx, 1, 0); /* fffff BLIT_DU_DX_FRACT */ 3048 xf_emit(ctx, 1, 1); /* 1ffff BLIT_DV_DY_INT */ 3049 xf_emit(ctx, 1, 0); /* fffff BLIT_DV_DY_FRACT */ 3050 if (device->chipset == 0x50) 3051 xf_emit(ctx, 1, 0); /* 3 BLIT_CONTROL */ 3052 else 3053 xf_emit(ctx, 2, 0); /* 3ff, 1 */ 3054 xf_emit(ctx, 1, 0x2a712488); /* ffffffff SRC_TIC_0 */ 3055 xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_1 */ 3056 xf_emit(ctx, 1, 0x4085c000); /* ffffffff SRC_TIC_2 */ 3057 xf_emit(ctx, 1, 0x40); /* ffffffff SRC_TIC_3 */ 3058 xf_emit(ctx, 1, 0x100); /* ffffffff SRC_TIC_4 */ 3059 xf_emit(ctx, 1, 0x10100); /* ffffffff SRC_TIC_5 */ 3060 xf_emit(ctx, 1, 0x02800000); /* ffffffff SRC_TIC_6 */ 3061 xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_7 */ 3062 if (device->chipset == 0x50) { 3063 xf_emit(ctx, 1, 0); /* 00000001 turing UNK358 */ 3064 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */ 3065 xf_emit(ctx, 1, 0); /* 00000003 turing UNK37C tesla UNK1690 */ 3066 xf_emit(ctx, 1, 0); /* 00000003 BLIT_CONTROL */ 3067 xf_emit(ctx, 1, 0); /* 00000001 turing UNK32C tesla UNK0F94 */ 3068 } else if (!IS_NVAAF(device->chipset)) { 3069 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */ 3070 xf_emit(ctx, 1, 0); /* 00000003 */ 3071 xf_emit(ctx, 1, 0); /* 000003ff */ 3072 xf_emit(ctx, 1, 0); /* 00000003 */ 3073 xf_emit(ctx, 1, 0); /* 000003ff */ 3074 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1664 / turing UNK03E8 */ 3075 xf_emit(ctx, 1, 0); /* 00000003 */ 3076 xf_emit(ctx, 1, 0); /* 000003ff */ 3077 } else { 3078 xf_emit(ctx, 0x6, 0); 3079 } 3080 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */ 3081 xf_emit(ctx, 1, 0); /* 0000ffff DMA_TEXTURE */ 3082 xf_emit(ctx, 1, 0); /* 0000ffff DMA_SRC */ 3083 } 3084 3085 static void 3086 nv50_gr_construct_xfer_unk8cxx(struct nouveau_grctx *ctx) 3087 { 3088 struct nouveau_device *device = ctx->device; 3089 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ 3090 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 3091 xf_emit(ctx, 2, 0); /* 7, ffff0ff3 */ 3092 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 3093 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */ 3094 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */ 3095 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */ 3096 xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */ 3097 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 3098 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ 3099 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK0F98 */ 3100 if (IS_NVA3F(device->chipset)) 3101 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 3102 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */ 3103 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 3104 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ 3105 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */ 3106 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ 3107 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 3108 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */ 3109 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ 3110 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 3111 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 3112 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */ 3113 xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */ 3114 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ 3115 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */ 3116 xf_emit(ctx, 1, 0x30201000); /* ffffffff tesla UNK1670 */ 3117 xf_emit(ctx, 1, 0x70605040); /* ffffffff tesla UNK1670 */ 3118 xf_emit(ctx, 1, 0xb8a89888); /* ffffffff tesla UNK1670 */ 3119 xf_emit(ctx, 1, 0xf8e8d8c8); /* ffffffff tesla UNK1670 */ 3120 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ 3121 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 3122 } 3123 3124 static void 3125 nv50_gr_construct_xfer_tp(struct nouveau_grctx *ctx) 3126 { 3127 struct nouveau_device *device = ctx->device; 3128 if (device->chipset < 0xa0) { 3129 nv50_gr_construct_xfer_unk84xx(ctx); 3130 nv50_gr_construct_xfer_tprop(ctx); 3131 nv50_gr_construct_xfer_tex(ctx); 3132 nv50_gr_construct_xfer_unk8cxx(ctx); 3133 } else { 3134 nv50_gr_construct_xfer_tex(ctx); 3135 nv50_gr_construct_xfer_tprop(ctx); 3136 nv50_gr_construct_xfer_unk8cxx(ctx); 3137 nv50_gr_construct_xfer_unk84xx(ctx); 3138 } 3139 } 3140 3141 static void 3142 nv50_gr_construct_xfer_mpc(struct nouveau_grctx *ctx) 3143 { 3144 struct nouveau_device *device = ctx->device; 3145 int i, mpcnt = 2; 3146 switch (device->chipset) { 3147 case 0x98: 3148 case 0xaa: 3149 mpcnt = 1; 3150 break; 3151 case 0x50: 3152 case 0x84: 3153 case 0x86: 3154 case 0x92: 3155 case 0x94: 3156 case 0x96: 3157 case 0xa8: 3158 case 0xac: 3159 mpcnt = 2; 3160 break; 3161 case 0xa0: 3162 case 0xa3: 3163 case 0xa5: 3164 case 0xaf: 3165 mpcnt = 3; 3166 break; 3167 } 3168 for (i = 0; i < mpcnt; i++) { 3169 xf_emit(ctx, 1, 0); /* ff */ 3170 xf_emit(ctx, 1, 0x80); /* ffffffff tesla UNK1404 */ 3171 xf_emit(ctx, 1, 0x80007004); /* ffffffff tesla UNK12B0 */ 3172 xf_emit(ctx, 1, 0x04000400); /* ffffffff */ 3173 if (device->chipset >= 0xa0) 3174 xf_emit(ctx, 1, 0xc0); /* 00007fff tesla UNK152C */ 3175 xf_emit(ctx, 1, 0x1000); /* 0000ffff tesla UNK0D60 */ 3176 xf_emit(ctx, 1, 0); /* ff/3ff */ 3177 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 3178 if (device->chipset == 0x86 || device->chipset == 0x98 || device->chipset == 0xa8 || IS_NVAAF(device->chipset)) { 3179 xf_emit(ctx, 1, 0xe00); /* 7fff */ 3180 xf_emit(ctx, 1, 0x1e00); /* 7fff */ 3181 } 3182 xf_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP */ 3183 xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */ 3184 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 3185 if (device->chipset == 0x50) 3186 xf_emit(ctx, 2, 0x1000); /* 7fff tesla UNK141C */ 3187 xf_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP */ 3188 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 3189 xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ 3190 xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ 3191 if (IS_NVAAF(device->chipset)) 3192 xf_emit(ctx, 0xb, 0); /* RO */ 3193 else if (device->chipset >= 0xa0) 3194 xf_emit(ctx, 0xc, 0); /* RO */ 3195 else 3196 xf_emit(ctx, 0xa, 0); /* RO */ 3197 } 3198 xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 3199 xf_emit(ctx, 1, 0); /* ff/3ff */ 3200 if (device->chipset >= 0xa0) { 3201 xf_emit(ctx, 1, 0x1fe21); /* 0003ffff tesla UNK0FAC */ 3202 } 3203 xf_emit(ctx, 3, 0); /* 7fff, 0, 0 */ 3204 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 3205 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 3206 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ 3207 xf_emit(ctx, 1, 1); /* 00000001 LANES32 */ 3208 xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */ 3209 xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */ 3210 xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */ 3211 xf_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */ 3212 xf_emit(ctx, 1, 0x1fe21); /* 1ffff/3ffff[NVA0+] tesla UNk0FAC */ 3213 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */ 3214 if (IS_NVA3F(device->chipset)) 3215 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 3216 xf_emit(ctx, 1, 0); /* ff/3ff */ 3217 xf_emit(ctx, 1, 0); /* 1 LINKED_TSC */ 3218 xf_emit(ctx, 1, 0); /* ff FP_ADDRESS_HIGH */ 3219 xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */ 3220 xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 3221 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 3222 xf_emit(ctx, 1, 0); /* 000000ff FRAG_COLOR_CLAMP_EN */ 3223 xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ 3224 xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */ 3225 xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */ 3226 xf_emit(ctx, 1, 0); /* 00000007 */ 3227 xf_emit(ctx, 1, 0xfac6881); /* 0fffffff RT_CONTROL */ 3228 xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ 3229 if (IS_NVA3F(device->chipset)) 3230 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */ 3231 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ 3232 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ 3233 xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ 3234 xf_emit(ctx, 1, 4); /* ffffffff tesla UNK1400 */ 3235 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 3236 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 3237 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ 3238 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ 3239 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ 3240 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ 3241 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ 3242 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ 3243 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ 3244 if (IS_NVA3F(device->chipset)) { 3245 xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */ 3246 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ 3247 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ 3248 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ 3249 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ 3250 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ 3251 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ 3252 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ 3253 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */ 3254 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ 3255 } 3256 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */ 3257 xf_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */ 3258 /* XXX: demagic this part some day */ 3259 if (device->chipset == 0x50) 3260 xf_emit(ctx, 0x3a0, 0); 3261 else if (device->chipset < 0x94) 3262 xf_emit(ctx, 0x3a2, 0); 3263 else if (device->chipset == 0x98 || device->chipset == 0xaa) 3264 xf_emit(ctx, 0x39f, 0); 3265 else 3266 xf_emit(ctx, 0x3a3, 0); 3267 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 3268 xf_emit(ctx, 1, 0); /* 7 OPERATION */ 3269 xf_emit(ctx, 1, 1); /* 1 DST_LINEAR */ 3270 xf_emit(ctx, 0x2d, 0); 3271 } 3272 3273 static void 3274 nv50_gr_construct_xfer2(struct nouveau_grctx *ctx) 3275 { 3276 struct nouveau_device *device = ctx->device; 3277 int i; 3278 u32 offset; 3279 u32 units = nv_rd32 (ctx->device, 0x1540); 3280 int size = 0; 3281 3282 offset = (ctx->ctxvals_pos+0x3f)&~0x3f; 3283 3284 if (device->chipset < 0xa0) { 3285 for (i = 0; i < 8; i++) { 3286 ctx->ctxvals_pos = offset + i; 3287 /* that little bugger belongs to csched. No idea 3288 * what it's doing here. */ 3289 if (i == 0) 3290 xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */ 3291 if (units & (1 << i)) 3292 nv50_gr_construct_xfer_mpc(ctx); 3293 if ((ctx->ctxvals_pos-offset)/8 > size) 3294 size = (ctx->ctxvals_pos-offset)/8; 3295 } 3296 } else { 3297 /* Strand 0: TPs 0, 1 */ 3298 ctx->ctxvals_pos = offset; 3299 /* that little bugger belongs to csched. No idea 3300 * what it's doing here. */ 3301 xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */ 3302 if (units & (1 << 0)) 3303 nv50_gr_construct_xfer_mpc(ctx); 3304 if (units & (1 << 1)) 3305 nv50_gr_construct_xfer_mpc(ctx); 3306 if ((ctx->ctxvals_pos-offset)/8 > size) 3307 size = (ctx->ctxvals_pos-offset)/8; 3308 3309 /* Strand 1: TPs 2, 3 */ 3310 ctx->ctxvals_pos = offset + 1; 3311 if (units & (1 << 2)) 3312 nv50_gr_construct_xfer_mpc(ctx); 3313 if (units & (1 << 3)) 3314 nv50_gr_construct_xfer_mpc(ctx); 3315 if ((ctx->ctxvals_pos-offset)/8 > size) 3316 size = (ctx->ctxvals_pos-offset)/8; 3317 3318 /* Strand 2: TPs 4, 5, 6 */ 3319 ctx->ctxvals_pos = offset + 2; 3320 if (units & (1 << 4)) 3321 nv50_gr_construct_xfer_mpc(ctx); 3322 if (units & (1 << 5)) 3323 nv50_gr_construct_xfer_mpc(ctx); 3324 if (units & (1 << 6)) 3325 nv50_gr_construct_xfer_mpc(ctx); 3326 if ((ctx->ctxvals_pos-offset)/8 > size) 3327 size = (ctx->ctxvals_pos-offset)/8; 3328 3329 /* Strand 3: TPs 7, 8, 9 */ 3330 ctx->ctxvals_pos = offset + 3; 3331 if (units & (1 << 7)) 3332 nv50_gr_construct_xfer_mpc(ctx); 3333 if (units & (1 << 8)) 3334 nv50_gr_construct_xfer_mpc(ctx); 3335 if (units & (1 << 9)) 3336 nv50_gr_construct_xfer_mpc(ctx); 3337 if ((ctx->ctxvals_pos-offset)/8 > size) 3338 size = (ctx->ctxvals_pos-offset)/8; 3339 } 3340 ctx->ctxvals_pos = offset + size * 8; 3341 ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f; 3342 cp_lsr (ctx, offset); 3343 cp_out (ctx, CP_SET_XFER_POINTER); 3344 cp_lsr (ctx, size); 3345 cp_out (ctx, CP_SEEK_2); 3346 cp_out (ctx, CP_XFER_2); 3347 cp_wait(ctx, XFER, BUSY); 3348 } 3349