1 /* 2 * Copyright 2009 Marcin Kościelnicki 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define CP_FLAG_CLEAR 0 24 #define CP_FLAG_SET 1 25 #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) 26 #define CP_FLAG_SWAP_DIRECTION_LOAD 0 27 #define CP_FLAG_SWAP_DIRECTION_SAVE 1 28 #define CP_FLAG_UNK01 ((0 * 32) + 1) 29 #define CP_FLAG_UNK01_CLEAR 0 30 #define CP_FLAG_UNK01_SET 1 31 #define CP_FLAG_UNK03 ((0 * 32) + 3) 32 #define CP_FLAG_UNK03_CLEAR 0 33 #define CP_FLAG_UNK03_SET 1 34 #define CP_FLAG_USER_SAVE ((0 * 32) + 5) 35 #define CP_FLAG_USER_SAVE_NOT_PENDING 0 36 #define CP_FLAG_USER_SAVE_PENDING 1 37 #define CP_FLAG_USER_LOAD ((0 * 32) + 6) 38 #define CP_FLAG_USER_LOAD_NOT_PENDING 0 39 #define CP_FLAG_USER_LOAD_PENDING 1 40 #define CP_FLAG_UNK0B ((0 * 32) + 0xb) 41 #define CP_FLAG_UNK0B_CLEAR 0 42 #define CP_FLAG_UNK0B_SET 1 43 #define CP_FLAG_XFER_SWITCH ((0 * 32) + 0xe) 44 #define CP_FLAG_XFER_SWITCH_DISABLE 0 45 #define CP_FLAG_XFER_SWITCH_ENABLE 1 46 #define CP_FLAG_STATE ((0 * 32) + 0x1c) 47 #define CP_FLAG_STATE_STOPPED 0 48 #define CP_FLAG_STATE_RUNNING 1 49 #define CP_FLAG_UNK1D ((0 * 32) + 0x1d) 50 #define CP_FLAG_UNK1D_CLEAR 0 51 #define CP_FLAG_UNK1D_SET 1 52 #define CP_FLAG_UNK20 ((1 * 32) + 0) 53 #define CP_FLAG_UNK20_CLEAR 0 54 #define CP_FLAG_UNK20_SET 1 55 #define CP_FLAG_STATUS ((2 * 32) + 0) 56 #define CP_FLAG_STATUS_BUSY 0 57 #define CP_FLAG_STATUS_IDLE 1 58 #define CP_FLAG_AUTO_SAVE ((2 * 32) + 4) 59 #define CP_FLAG_AUTO_SAVE_NOT_PENDING 0 60 #define CP_FLAG_AUTO_SAVE_PENDING 1 61 #define CP_FLAG_AUTO_LOAD ((2 * 32) + 5) 62 #define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 63 #define CP_FLAG_AUTO_LOAD_PENDING 1 64 #define CP_FLAG_NEWCTX ((2 * 32) + 10) 65 #define CP_FLAG_NEWCTX_BUSY 0 66 #define CP_FLAG_NEWCTX_DONE 1 67 #define CP_FLAG_XFER ((2 * 32) + 11) 68 #define CP_FLAG_XFER_IDLE 0 69 #define CP_FLAG_XFER_BUSY 1 70 #define CP_FLAG_ALWAYS ((2 * 32) + 13) 71 #define CP_FLAG_ALWAYS_FALSE 0 72 #define CP_FLAG_ALWAYS_TRUE 1 73 #define CP_FLAG_INTR ((2 * 32) + 15) 74 #define CP_FLAG_INTR_NOT_PENDING 0 75 #define CP_FLAG_INTR_PENDING 1 76 77 #define CP_CTX 0x00100000 78 #define CP_CTX_COUNT 0x000f0000 79 #define CP_CTX_COUNT_SHIFT 16 80 #define CP_CTX_REG 0x00003fff 81 #define CP_LOAD_SR 0x00200000 82 #define CP_LOAD_SR_VALUE 0x000fffff 83 #define CP_BRA 0x00400000 84 #define CP_BRA_IP 0x0001ff00 85 #define CP_BRA_IP_SHIFT 8 86 #define CP_BRA_IF_CLEAR 0x00000080 87 #define CP_BRA_FLAG 0x0000007f 88 #define CP_WAIT 0x00500000 89 #define CP_WAIT_SET 0x00000080 90 #define CP_WAIT_FLAG 0x0000007f 91 #define CP_SET 0x00700000 92 #define CP_SET_1 0x00000080 93 #define CP_SET_FLAG 0x0000007f 94 #define CP_NEWCTX 0x00600004 95 #define CP_NEXT_TO_SWAP 0x00600005 96 #define CP_SET_CONTEXT_POINTER 0x00600006 97 #define CP_SET_XFER_POINTER 0x00600007 98 #define CP_ENABLE 0x00600009 99 #define CP_END 0x0060000c 100 #define CP_NEXT_TO_CURRENT 0x0060000d 101 #define CP_DISABLE1 0x0090ffff 102 #define CP_DISABLE2 0x0091ffff 103 #define CP_XFER_1 0x008000ff 104 #define CP_XFER_2 0x008800ff 105 #define CP_SEEK_1 0x00c000ff 106 #define CP_SEEK_2 0x00c800ff 107 108 #include "ctxnv40.h" 109 110 #include <subdev/fb.h> 111 112 #define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf) 113 #define IS_NVAAF(x) ((x) >= 0xaa && (x) <= 0xac) 114 115 /* 116 * This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's 117 * the GPU itself that does context-switching, but it needs a special 118 * microcode to do it. And it's the driver's task to supply this microcode, 119 * further known as ctxprog, as well as the initial context values, known 120 * as ctxvals. 121 * 122 * Without ctxprog, you cannot switch contexts. Not even in software, since 123 * the majority of context [xfer strands] isn't accessible directly. You're 124 * stuck with a single channel, and you also suffer all the problems resulting 125 * from missing ctxvals, since you cannot load them. 126 * 127 * Without ctxvals, you're stuck with PGRAPH's default context. It's enough to 128 * run 2d operations, but trying to utilise 3d or CUDA will just lock you up, 129 * since you don't have... some sort of needed setup. 130 * 131 * Nouveau will just disable acceleration if not given ctxprog + ctxvals, since 132 * it's too much hassle to handle no-ctxprog as a special case. 133 */ 134 135 /* 136 * How ctxprogs work. 137 * 138 * The ctxprog is written in its own kind of microcode, with very small and 139 * crappy set of available commands. You upload it to a small [512 insns] 140 * area of memory on PGRAPH, and it'll be run when PFIFO wants PGRAPH to 141 * switch channel. or when the driver explicitely requests it. Stuff visible 142 * to ctxprog consists of: PGRAPH MMIO registers, PGRAPH context strands, 143 * the per-channel context save area in VRAM [known as ctxvals or grctx], 144 * 4 flags registers, a scratch register, two grctx pointers, plus many 145 * random poorly-understood details. 146 * 147 * When ctxprog runs, it's supposed to check what operations are asked of it, 148 * save old context if requested, optionally reset PGRAPH and switch to the 149 * new channel, and load the new context. Context consists of three major 150 * parts: subset of MMIO registers and two "xfer areas". 151 */ 152 153 /* TODO: 154 * - document unimplemented bits compared to nvidia 155 * - NVAx: make a TP subroutine, use it. 156 * - use 0x4008fc instead of 0x1540? 157 */ 158 159 enum cp_label { 160 cp_check_load = 1, 161 cp_setup_auto_load, 162 cp_setup_load, 163 cp_setup_save, 164 cp_swap_state, 165 cp_prepare_exit, 166 cp_exit, 167 }; 168 169 static void nv50_gr_construct_mmio(struct nvkm_grctx *ctx); 170 static void nv50_gr_construct_xfer1(struct nvkm_grctx *ctx); 171 static void nv50_gr_construct_xfer2(struct nvkm_grctx *ctx); 172 173 /* Main function: construct the ctxprog skeleton, call the other functions. */ 174 175 static int 176 nv50_grctx_generate(struct nvkm_grctx *ctx) 177 { 178 cp_set (ctx, STATE, RUNNING); 179 cp_set (ctx, XFER_SWITCH, ENABLE); 180 /* decide whether we're loading/unloading the context */ 181 cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); 182 cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); 183 184 cp_name(ctx, cp_check_load); 185 cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); 186 cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); 187 cp_bra (ctx, ALWAYS, TRUE, cp_prepare_exit); 188 189 /* setup for context load */ 190 cp_name(ctx, cp_setup_auto_load); 191 cp_out (ctx, CP_DISABLE1); 192 cp_out (ctx, CP_DISABLE2); 193 cp_out (ctx, CP_ENABLE); 194 cp_out (ctx, CP_NEXT_TO_SWAP); 195 cp_set (ctx, UNK01, SET); 196 cp_name(ctx, cp_setup_load); 197 cp_out (ctx, CP_NEWCTX); 198 cp_wait(ctx, NEWCTX, BUSY); 199 cp_set (ctx, UNK1D, CLEAR); 200 cp_set (ctx, SWAP_DIRECTION, LOAD); 201 cp_bra (ctx, UNK0B, SET, cp_prepare_exit); 202 cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); 203 204 /* setup for context save */ 205 cp_name(ctx, cp_setup_save); 206 cp_set (ctx, UNK1D, SET); 207 cp_wait(ctx, STATUS, BUSY); 208 cp_wait(ctx, INTR, PENDING); 209 cp_bra (ctx, STATUS, BUSY, cp_setup_save); 210 cp_set (ctx, UNK01, SET); 211 cp_set (ctx, SWAP_DIRECTION, SAVE); 212 213 /* general PGRAPH state */ 214 cp_name(ctx, cp_swap_state); 215 cp_set (ctx, UNK03, SET); 216 cp_pos (ctx, 0x00004/4); 217 cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */ 218 cp_pos (ctx, 0x00100/4); 219 nv50_gr_construct_mmio(ctx); 220 nv50_gr_construct_xfer1(ctx); 221 nv50_gr_construct_xfer2(ctx); 222 223 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); 224 225 cp_set (ctx, UNK20, SET); 226 cp_set (ctx, SWAP_DIRECTION, SAVE); /* no idea why this is needed, but fixes at least one lockup. */ 227 cp_lsr (ctx, ctx->ctxvals_base); 228 cp_out (ctx, CP_SET_XFER_POINTER); 229 cp_lsr (ctx, 4); 230 cp_out (ctx, CP_SEEK_1); 231 cp_out (ctx, CP_XFER_1); 232 cp_wait(ctx, XFER, BUSY); 233 234 /* pre-exit state updates */ 235 cp_name(ctx, cp_prepare_exit); 236 cp_set (ctx, UNK01, CLEAR); 237 cp_set (ctx, UNK03, CLEAR); 238 cp_set (ctx, UNK1D, CLEAR); 239 240 cp_bra (ctx, USER_SAVE, PENDING, cp_exit); 241 cp_out (ctx, CP_NEXT_TO_CURRENT); 242 243 cp_name(ctx, cp_exit); 244 cp_set (ctx, USER_SAVE, NOT_PENDING); 245 cp_set (ctx, USER_LOAD, NOT_PENDING); 246 cp_set (ctx, XFER_SWITCH, DISABLE); 247 cp_set (ctx, STATE, STOPPED); 248 cp_out (ctx, CP_END); 249 ctx->ctxvals_pos += 0x400; /* padding... no idea why you need it */ 250 251 return 0; 252 } 253 254 void 255 nv50_grctx_fill(struct nvkm_device *device, struct nvkm_gpuobj *mem) 256 { 257 nv50_grctx_generate(&(struct nvkm_grctx) { 258 .device = device, 259 .mode = NVKM_GRCTX_VALS, 260 .data = mem, 261 }); 262 } 263 264 int 265 nv50_grctx_init(struct nvkm_device *device, u32 *size) 266 { 267 u32 *ctxprog = kmalloc(512 * 4, GFP_KERNEL), i; 268 struct nvkm_grctx ctx = { 269 .device = device, 270 .mode = NVKM_GRCTX_PROG, 271 .ucode = ctxprog, 272 .ctxprog_max = 512, 273 }; 274 275 if (!ctxprog) 276 return -ENOMEM; 277 nv50_grctx_generate(&ctx); 278 279 nvkm_wr32(device, 0x400324, 0); 280 for (i = 0; i < ctx.ctxprog_len; i++) 281 nvkm_wr32(device, 0x400328, ctxprog[i]); 282 *size = ctx.ctxvals_pos * 4; 283 kfree(ctxprog); 284 return 0; 285 } 286 287 /* 288 * Constructs MMIO part of ctxprog and ctxvals. Just a matter of knowing which 289 * registers to save/restore and the default values for them. 290 */ 291 292 static void 293 nv50_gr_construct_mmio_ddata(struct nvkm_grctx *ctx); 294 295 static void 296 nv50_gr_construct_mmio(struct nvkm_grctx *ctx) 297 { 298 struct nvkm_device *device = ctx->device; 299 int i, j; 300 int offset, base; 301 u32 units = nvkm_rd32(device, 0x1540); 302 303 /* 0800: DISPATCH */ 304 cp_ctx(ctx, 0x400808, 7); 305 gr_def(ctx, 0x400814, 0x00000030); 306 cp_ctx(ctx, 0x400834, 0x32); 307 if (device->chipset == 0x50) { 308 gr_def(ctx, 0x400834, 0xff400040); 309 gr_def(ctx, 0x400838, 0xfff00080); 310 gr_def(ctx, 0x40083c, 0xfff70090); 311 gr_def(ctx, 0x400840, 0xffe806a8); 312 } 313 gr_def(ctx, 0x400844, 0x00000002); 314 if (IS_NVA3F(device->chipset)) 315 gr_def(ctx, 0x400894, 0x00001000); 316 gr_def(ctx, 0x4008e8, 0x00000003); 317 gr_def(ctx, 0x4008ec, 0x00001000); 318 if (device->chipset == 0x50) 319 cp_ctx(ctx, 0x400908, 0xb); 320 else if (device->chipset < 0xa0) 321 cp_ctx(ctx, 0x400908, 0xc); 322 else 323 cp_ctx(ctx, 0x400908, 0xe); 324 325 if (device->chipset >= 0xa0) 326 cp_ctx(ctx, 0x400b00, 0x1); 327 if (IS_NVA3F(device->chipset)) { 328 cp_ctx(ctx, 0x400b10, 0x1); 329 gr_def(ctx, 0x400b10, 0x0001629d); 330 cp_ctx(ctx, 0x400b20, 0x1); 331 gr_def(ctx, 0x400b20, 0x0001629d); 332 } 333 334 nv50_gr_construct_mmio_ddata(ctx); 335 336 /* 0C00: VFETCH */ 337 cp_ctx(ctx, 0x400c08, 0x2); 338 gr_def(ctx, 0x400c08, 0x0000fe0c); 339 340 /* 1000 */ 341 if (device->chipset < 0xa0) { 342 cp_ctx(ctx, 0x401008, 0x4); 343 gr_def(ctx, 0x401014, 0x00001000); 344 } else if (!IS_NVA3F(device->chipset)) { 345 cp_ctx(ctx, 0x401008, 0x5); 346 gr_def(ctx, 0x401018, 0x00001000); 347 } else { 348 cp_ctx(ctx, 0x401008, 0x5); 349 gr_def(ctx, 0x401018, 0x00004000); 350 } 351 352 /* 1400 */ 353 cp_ctx(ctx, 0x401400, 0x8); 354 cp_ctx(ctx, 0x401424, 0x3); 355 if (device->chipset == 0x50) 356 gr_def(ctx, 0x40142c, 0x0001fd87); 357 else 358 gr_def(ctx, 0x40142c, 0x00000187); 359 cp_ctx(ctx, 0x401540, 0x5); 360 gr_def(ctx, 0x401550, 0x00001018); 361 362 /* 1800: STREAMOUT */ 363 cp_ctx(ctx, 0x401814, 0x1); 364 gr_def(ctx, 0x401814, 0x000000ff); 365 if (device->chipset == 0x50) { 366 cp_ctx(ctx, 0x40181c, 0xe); 367 gr_def(ctx, 0x401850, 0x00000004); 368 } else if (device->chipset < 0xa0) { 369 cp_ctx(ctx, 0x40181c, 0xf); 370 gr_def(ctx, 0x401854, 0x00000004); 371 } else { 372 cp_ctx(ctx, 0x40181c, 0x13); 373 gr_def(ctx, 0x401864, 0x00000004); 374 } 375 376 /* 1C00 */ 377 cp_ctx(ctx, 0x401c00, 0x1); 378 switch (device->chipset) { 379 case 0x50: 380 gr_def(ctx, 0x401c00, 0x0001005f); 381 break; 382 case 0x84: 383 case 0x86: 384 case 0x94: 385 gr_def(ctx, 0x401c00, 0x044d00df); 386 break; 387 case 0x92: 388 case 0x96: 389 case 0x98: 390 case 0xa0: 391 case 0xaa: 392 case 0xac: 393 gr_def(ctx, 0x401c00, 0x042500df); 394 break; 395 case 0xa3: 396 case 0xa5: 397 case 0xa8: 398 case 0xaf: 399 gr_def(ctx, 0x401c00, 0x142500df); 400 break; 401 } 402 403 /* 2000 */ 404 405 /* 2400 */ 406 cp_ctx(ctx, 0x402400, 0x1); 407 if (device->chipset == 0x50) 408 cp_ctx(ctx, 0x402408, 0x1); 409 else 410 cp_ctx(ctx, 0x402408, 0x2); 411 gr_def(ctx, 0x402408, 0x00000600); 412 413 /* 2800: CSCHED */ 414 cp_ctx(ctx, 0x402800, 0x1); 415 if (device->chipset == 0x50) 416 gr_def(ctx, 0x402800, 0x00000006); 417 418 /* 2C00: ZCULL */ 419 cp_ctx(ctx, 0x402c08, 0x6); 420 if (device->chipset != 0x50) 421 gr_def(ctx, 0x402c14, 0x01000000); 422 gr_def(ctx, 0x402c18, 0x000000ff); 423 if (device->chipset == 0x50) 424 cp_ctx(ctx, 0x402ca0, 0x1); 425 else 426 cp_ctx(ctx, 0x402ca0, 0x2); 427 if (device->chipset < 0xa0) 428 gr_def(ctx, 0x402ca0, 0x00000400); 429 else if (!IS_NVA3F(device->chipset)) 430 gr_def(ctx, 0x402ca0, 0x00000800); 431 else 432 gr_def(ctx, 0x402ca0, 0x00000400); 433 cp_ctx(ctx, 0x402cac, 0x4); 434 435 /* 3000: ENG2D */ 436 cp_ctx(ctx, 0x403004, 0x1); 437 gr_def(ctx, 0x403004, 0x00000001); 438 439 /* 3400 */ 440 if (device->chipset >= 0xa0) { 441 cp_ctx(ctx, 0x403404, 0x1); 442 gr_def(ctx, 0x403404, 0x00000001); 443 } 444 445 /* 5000: CCACHE */ 446 cp_ctx(ctx, 0x405000, 0x1); 447 switch (device->chipset) { 448 case 0x50: 449 gr_def(ctx, 0x405000, 0x00300080); 450 break; 451 case 0x84: 452 case 0xa0: 453 case 0xa3: 454 case 0xa5: 455 case 0xa8: 456 case 0xaa: 457 case 0xac: 458 case 0xaf: 459 gr_def(ctx, 0x405000, 0x000e0080); 460 break; 461 case 0x86: 462 case 0x92: 463 case 0x94: 464 case 0x96: 465 case 0x98: 466 gr_def(ctx, 0x405000, 0x00000080); 467 break; 468 } 469 cp_ctx(ctx, 0x405014, 0x1); 470 gr_def(ctx, 0x405014, 0x00000004); 471 cp_ctx(ctx, 0x40501c, 0x1); 472 cp_ctx(ctx, 0x405024, 0x1); 473 cp_ctx(ctx, 0x40502c, 0x1); 474 475 /* 6000? */ 476 if (device->chipset == 0x50) 477 cp_ctx(ctx, 0x4063e0, 0x1); 478 479 /* 6800: M2MF */ 480 if (device->chipset < 0x90) { 481 cp_ctx(ctx, 0x406814, 0x2b); 482 gr_def(ctx, 0x406818, 0x00000f80); 483 gr_def(ctx, 0x406860, 0x007f0080); 484 gr_def(ctx, 0x40689c, 0x007f0080); 485 } else { 486 cp_ctx(ctx, 0x406814, 0x4); 487 if (device->chipset == 0x98) 488 gr_def(ctx, 0x406818, 0x00000f80); 489 else 490 gr_def(ctx, 0x406818, 0x00001f80); 491 if (IS_NVA3F(device->chipset)) 492 gr_def(ctx, 0x40681c, 0x00000030); 493 cp_ctx(ctx, 0x406830, 0x3); 494 } 495 496 /* 7000: per-ROP group state */ 497 for (i = 0; i < 8; i++) { 498 if (units & (1<<(i+16))) { 499 cp_ctx(ctx, 0x407000 + (i<<8), 3); 500 if (device->chipset == 0x50) 501 gr_def(ctx, 0x407000 + (i<<8), 0x1b74f820); 502 else if (device->chipset != 0xa5) 503 gr_def(ctx, 0x407000 + (i<<8), 0x3b74f821); 504 else 505 gr_def(ctx, 0x407000 + (i<<8), 0x7b74f821); 506 gr_def(ctx, 0x407004 + (i<<8), 0x89058001); 507 508 if (device->chipset == 0x50) { 509 cp_ctx(ctx, 0x407010 + (i<<8), 1); 510 } else if (device->chipset < 0xa0) { 511 cp_ctx(ctx, 0x407010 + (i<<8), 2); 512 gr_def(ctx, 0x407010 + (i<<8), 0x00001000); 513 gr_def(ctx, 0x407014 + (i<<8), 0x0000001f); 514 } else { 515 cp_ctx(ctx, 0x407010 + (i<<8), 3); 516 gr_def(ctx, 0x407010 + (i<<8), 0x00001000); 517 if (device->chipset != 0xa5) 518 gr_def(ctx, 0x407014 + (i<<8), 0x000000ff); 519 else 520 gr_def(ctx, 0x407014 + (i<<8), 0x000001ff); 521 } 522 523 cp_ctx(ctx, 0x407080 + (i<<8), 4); 524 if (device->chipset != 0xa5) 525 gr_def(ctx, 0x407080 + (i<<8), 0x027c10fa); 526 else 527 gr_def(ctx, 0x407080 + (i<<8), 0x827c10fa); 528 if (device->chipset == 0x50) 529 gr_def(ctx, 0x407084 + (i<<8), 0x000000c0); 530 else 531 gr_def(ctx, 0x407084 + (i<<8), 0x400000c0); 532 gr_def(ctx, 0x407088 + (i<<8), 0xb7892080); 533 534 if (device->chipset < 0xa0) 535 cp_ctx(ctx, 0x407094 + (i<<8), 1); 536 else if (!IS_NVA3F(device->chipset)) 537 cp_ctx(ctx, 0x407094 + (i<<8), 3); 538 else { 539 cp_ctx(ctx, 0x407094 + (i<<8), 4); 540 gr_def(ctx, 0x4070a0 + (i<<8), 1); 541 } 542 } 543 } 544 545 cp_ctx(ctx, 0x407c00, 0x3); 546 if (device->chipset < 0x90) 547 gr_def(ctx, 0x407c00, 0x00010040); 548 else if (device->chipset < 0xa0) 549 gr_def(ctx, 0x407c00, 0x00390040); 550 else 551 gr_def(ctx, 0x407c00, 0x003d0040); 552 gr_def(ctx, 0x407c08, 0x00000022); 553 if (device->chipset >= 0xa0) { 554 cp_ctx(ctx, 0x407c10, 0x3); 555 cp_ctx(ctx, 0x407c20, 0x1); 556 cp_ctx(ctx, 0x407c2c, 0x1); 557 } 558 559 if (device->chipset < 0xa0) { 560 cp_ctx(ctx, 0x407d00, 0x9); 561 } else { 562 cp_ctx(ctx, 0x407d00, 0x15); 563 } 564 if (device->chipset == 0x98) 565 gr_def(ctx, 0x407d08, 0x00380040); 566 else { 567 if (device->chipset < 0x90) 568 gr_def(ctx, 0x407d08, 0x00010040); 569 else if (device->chipset < 0xa0) 570 gr_def(ctx, 0x407d08, 0x00390040); 571 else { 572 if (device->fb->ram->type != NVKM_RAM_TYPE_GDDR5) 573 gr_def(ctx, 0x407d08, 0x003d0040); 574 else 575 gr_def(ctx, 0x407d08, 0x003c0040); 576 } 577 gr_def(ctx, 0x407d0c, 0x00000022); 578 } 579 580 /* 8000+: per-TP state */ 581 for (i = 0; i < 10; i++) { 582 if (units & (1<<i)) { 583 if (device->chipset < 0xa0) 584 base = 0x408000 + (i<<12); 585 else 586 base = 0x408000 + (i<<11); 587 if (device->chipset < 0xa0) 588 offset = base + 0xc00; 589 else 590 offset = base + 0x80; 591 cp_ctx(ctx, offset + 0x00, 1); 592 gr_def(ctx, offset + 0x00, 0x0000ff0a); 593 cp_ctx(ctx, offset + 0x08, 1); 594 595 /* per-MP state */ 596 for (j = 0; j < (device->chipset < 0xa0 ? 2 : 4); j++) { 597 if (!(units & (1 << (j+24)))) continue; 598 if (device->chipset < 0xa0) 599 offset = base + 0x200 + (j<<7); 600 else 601 offset = base + 0x100 + (j<<7); 602 cp_ctx(ctx, offset, 0x20); 603 gr_def(ctx, offset + 0x00, 0x01800000); 604 gr_def(ctx, offset + 0x04, 0x00160000); 605 gr_def(ctx, offset + 0x08, 0x01800000); 606 gr_def(ctx, offset + 0x18, 0x0003ffff); 607 switch (device->chipset) { 608 case 0x50: 609 gr_def(ctx, offset + 0x1c, 0x00080000); 610 break; 611 case 0x84: 612 gr_def(ctx, offset + 0x1c, 0x00880000); 613 break; 614 case 0x86: 615 gr_def(ctx, offset + 0x1c, 0x018c0000); 616 break; 617 case 0x92: 618 case 0x96: 619 case 0x98: 620 gr_def(ctx, offset + 0x1c, 0x118c0000); 621 break; 622 case 0x94: 623 gr_def(ctx, offset + 0x1c, 0x10880000); 624 break; 625 case 0xa0: 626 case 0xa5: 627 gr_def(ctx, offset + 0x1c, 0x310c0000); 628 break; 629 case 0xa3: 630 case 0xa8: 631 case 0xaa: 632 case 0xac: 633 case 0xaf: 634 gr_def(ctx, offset + 0x1c, 0x300c0000); 635 break; 636 } 637 gr_def(ctx, offset + 0x40, 0x00010401); 638 if (device->chipset == 0x50) 639 gr_def(ctx, offset + 0x48, 0x00000040); 640 else 641 gr_def(ctx, offset + 0x48, 0x00000078); 642 gr_def(ctx, offset + 0x50, 0x000000bf); 643 gr_def(ctx, offset + 0x58, 0x00001210); 644 if (device->chipset == 0x50) 645 gr_def(ctx, offset + 0x5c, 0x00000080); 646 else 647 gr_def(ctx, offset + 0x5c, 0x08000080); 648 if (device->chipset >= 0xa0) 649 gr_def(ctx, offset + 0x68, 0x0000003e); 650 } 651 652 if (device->chipset < 0xa0) 653 cp_ctx(ctx, base + 0x300, 0x4); 654 else 655 cp_ctx(ctx, base + 0x300, 0x5); 656 if (device->chipset == 0x50) 657 gr_def(ctx, base + 0x304, 0x00007070); 658 else if (device->chipset < 0xa0) 659 gr_def(ctx, base + 0x304, 0x00027070); 660 else if (!IS_NVA3F(device->chipset)) 661 gr_def(ctx, base + 0x304, 0x01127070); 662 else 663 gr_def(ctx, base + 0x304, 0x05127070); 664 665 if (device->chipset < 0xa0) 666 cp_ctx(ctx, base + 0x318, 1); 667 else 668 cp_ctx(ctx, base + 0x320, 1); 669 if (device->chipset == 0x50) 670 gr_def(ctx, base + 0x318, 0x0003ffff); 671 else if (device->chipset < 0xa0) 672 gr_def(ctx, base + 0x318, 0x03ffffff); 673 else 674 gr_def(ctx, base + 0x320, 0x07ffffff); 675 676 if (device->chipset < 0xa0) 677 cp_ctx(ctx, base + 0x324, 5); 678 else 679 cp_ctx(ctx, base + 0x328, 4); 680 681 if (device->chipset < 0xa0) { 682 cp_ctx(ctx, base + 0x340, 9); 683 offset = base + 0x340; 684 } else if (!IS_NVA3F(device->chipset)) { 685 cp_ctx(ctx, base + 0x33c, 0xb); 686 offset = base + 0x344; 687 } else { 688 cp_ctx(ctx, base + 0x33c, 0xd); 689 offset = base + 0x344; 690 } 691 gr_def(ctx, offset + 0x0, 0x00120407); 692 gr_def(ctx, offset + 0x4, 0x05091507); 693 if (device->chipset == 0x84) 694 gr_def(ctx, offset + 0x8, 0x05100202); 695 else 696 gr_def(ctx, offset + 0x8, 0x05010202); 697 gr_def(ctx, offset + 0xc, 0x00030201); 698 if (device->chipset == 0xa3) 699 cp_ctx(ctx, base + 0x36c, 1); 700 701 cp_ctx(ctx, base + 0x400, 2); 702 gr_def(ctx, base + 0x404, 0x00000040); 703 cp_ctx(ctx, base + 0x40c, 2); 704 gr_def(ctx, base + 0x40c, 0x0d0c0b0a); 705 gr_def(ctx, base + 0x410, 0x00141210); 706 707 if (device->chipset < 0xa0) 708 offset = base + 0x800; 709 else 710 offset = base + 0x500; 711 cp_ctx(ctx, offset, 6); 712 gr_def(ctx, offset + 0x0, 0x000001f0); 713 gr_def(ctx, offset + 0x4, 0x00000001); 714 gr_def(ctx, offset + 0x8, 0x00000003); 715 if (device->chipset == 0x50 || IS_NVAAF(device->chipset)) 716 gr_def(ctx, offset + 0xc, 0x00008000); 717 gr_def(ctx, offset + 0x14, 0x00039e00); 718 cp_ctx(ctx, offset + 0x1c, 2); 719 if (device->chipset == 0x50) 720 gr_def(ctx, offset + 0x1c, 0x00000040); 721 else 722 gr_def(ctx, offset + 0x1c, 0x00000100); 723 gr_def(ctx, offset + 0x20, 0x00003800); 724 725 if (device->chipset >= 0xa0) { 726 cp_ctx(ctx, base + 0x54c, 2); 727 if (!IS_NVA3F(device->chipset)) 728 gr_def(ctx, base + 0x54c, 0x003fe006); 729 else 730 gr_def(ctx, base + 0x54c, 0x003fe007); 731 gr_def(ctx, base + 0x550, 0x003fe000); 732 } 733 734 if (device->chipset < 0xa0) 735 offset = base + 0xa00; 736 else 737 offset = base + 0x680; 738 cp_ctx(ctx, offset, 1); 739 gr_def(ctx, offset, 0x00404040); 740 741 if (device->chipset < 0xa0) 742 offset = base + 0xe00; 743 else 744 offset = base + 0x700; 745 cp_ctx(ctx, offset, 2); 746 if (device->chipset < 0xa0) 747 gr_def(ctx, offset, 0x0077f005); 748 else if (device->chipset == 0xa5) 749 gr_def(ctx, offset, 0x6cf7f007); 750 else if (device->chipset == 0xa8) 751 gr_def(ctx, offset, 0x6cfff007); 752 else if (device->chipset == 0xac) 753 gr_def(ctx, offset, 0x0cfff007); 754 else 755 gr_def(ctx, offset, 0x0cf7f007); 756 if (device->chipset == 0x50) 757 gr_def(ctx, offset + 0x4, 0x00007fff); 758 else if (device->chipset < 0xa0) 759 gr_def(ctx, offset + 0x4, 0x003f7fff); 760 else 761 gr_def(ctx, offset + 0x4, 0x02bf7fff); 762 cp_ctx(ctx, offset + 0x2c, 1); 763 if (device->chipset == 0x50) { 764 cp_ctx(ctx, offset + 0x50, 9); 765 gr_def(ctx, offset + 0x54, 0x000003ff); 766 gr_def(ctx, offset + 0x58, 0x00000003); 767 gr_def(ctx, offset + 0x5c, 0x00000003); 768 gr_def(ctx, offset + 0x60, 0x000001ff); 769 gr_def(ctx, offset + 0x64, 0x0000001f); 770 gr_def(ctx, offset + 0x68, 0x0000000f); 771 gr_def(ctx, offset + 0x6c, 0x0000000f); 772 } else if (device->chipset < 0xa0) { 773 cp_ctx(ctx, offset + 0x50, 1); 774 cp_ctx(ctx, offset + 0x70, 1); 775 } else { 776 cp_ctx(ctx, offset + 0x50, 1); 777 cp_ctx(ctx, offset + 0x60, 5); 778 } 779 } 780 } 781 } 782 783 static void 784 dd_emit(struct nvkm_grctx *ctx, int num, u32 val) { 785 int i; 786 if (val && ctx->mode == NVKM_GRCTX_VALS) { 787 for (i = 0; i < num; i++) 788 nvkm_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val); 789 } 790 ctx->ctxvals_pos += num; 791 } 792 793 static void 794 nv50_gr_construct_mmio_ddata(struct nvkm_grctx *ctx) 795 { 796 struct nvkm_device *device = ctx->device; 797 int base, num; 798 base = ctx->ctxvals_pos; 799 800 /* tesla state */ 801 dd_emit(ctx, 1, 0); /* 00000001 UNK0F90 */ 802 dd_emit(ctx, 1, 0); /* 00000001 UNK135C */ 803 804 /* SRC_TIC state */ 805 dd_emit(ctx, 1, 0); /* 00000007 SRC_TILE_MODE_Z */ 806 dd_emit(ctx, 1, 2); /* 00000007 SRC_TILE_MODE_Y */ 807 dd_emit(ctx, 1, 1); /* 00000001 SRC_LINEAR #1 */ 808 dd_emit(ctx, 1, 0); /* 000000ff SRC_ADDRESS_HIGH */ 809 dd_emit(ctx, 1, 0); /* 00000001 SRC_SRGB */ 810 if (device->chipset >= 0x94) 811 dd_emit(ctx, 1, 0); /* 00000003 eng2d UNK0258 */ 812 dd_emit(ctx, 1, 1); /* 00000fff SRC_DEPTH */ 813 dd_emit(ctx, 1, 0x100); /* 0000ffff SRC_HEIGHT */ 814 815 /* turing state */ 816 dd_emit(ctx, 1, 0); /* 0000000f TEXTURES_LOG2 */ 817 dd_emit(ctx, 1, 0); /* 0000000f SAMPLERS_LOG2 */ 818 dd_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */ 819 dd_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */ 820 dd_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */ 821 dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */ 822 dd_emit(ctx, 1, 1); /* 0000ffff BLOCK_ALLOC_THREADS */ 823 dd_emit(ctx, 1, 1); /* 00000001 LANES32 */ 824 dd_emit(ctx, 1, 0); /* 000000ff UNK370 */ 825 dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_UNK */ 826 dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_COUNT */ 827 dd_emit(ctx, 1, 1); /* 000000ff UNK384 bits 8-15 */ 828 dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ 829 dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ 830 dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */ 831 dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_X */ 832 dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_XMY */ 833 dd_emit(ctx, 1, 0); /* 00000001 BLOCKDIM_XMY_OVERFLOW */ 834 dd_emit(ctx, 1, 1); /* 0003ffff BLOCKDIM_XMYMZ */ 835 dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_Y */ 836 dd_emit(ctx, 1, 1); /* 0000007f BLOCKDIM_Z */ 837 dd_emit(ctx, 1, 4); /* 000000ff CP_REG_ALLOC_TEMP */ 838 dd_emit(ctx, 1, 1); /* 00000001 BLOCKDIM_DIRTY */ 839 if (IS_NVA3F(device->chipset)) 840 dd_emit(ctx, 1, 0); /* 00000003 UNK03E8 */ 841 dd_emit(ctx, 1, 1); /* 0000007f BLOCK_ALLOC_HALFWARPS */ 842 dd_emit(ctx, 1, 1); /* 00000007 LOCAL_WARPS_NO_CLAMP */ 843 dd_emit(ctx, 1, 7); /* 00000007 LOCAL_WARPS_LOG_ALLOC */ 844 dd_emit(ctx, 1, 1); /* 00000007 STACK_WARPS_NO_CLAMP */ 845 dd_emit(ctx, 1, 7); /* 00000007 STACK_WARPS_LOG_ALLOC */ 846 dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_PACKED */ 847 dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_STRIDED */ 848 dd_emit(ctx, 1, 1); /* 000007ff BLOCK_ALLOC_THREADS */ 849 850 /* compat 2d state */ 851 if (device->chipset == 0x50) { 852 dd_emit(ctx, 4, 0); /* 0000ffff clip X, Y, W, H */ 853 854 dd_emit(ctx, 1, 1); /* ffffffff chroma COLOR_FORMAT */ 855 856 dd_emit(ctx, 1, 1); /* ffffffff pattern COLOR_FORMAT */ 857 dd_emit(ctx, 1, 0); /* ffffffff pattern SHAPE */ 858 dd_emit(ctx, 1, 1); /* ffffffff pattern PATTERN_SELECT */ 859 860 dd_emit(ctx, 1, 0xa); /* ffffffff surf2d SRC_FORMAT */ 861 dd_emit(ctx, 1, 0); /* ffffffff surf2d DMA_SRC */ 862 dd_emit(ctx, 1, 0); /* 000000ff surf2d SRC_ADDRESS_HIGH */ 863 dd_emit(ctx, 1, 0); /* ffffffff surf2d SRC_ADDRESS_LOW */ 864 dd_emit(ctx, 1, 0x40); /* 0000ffff surf2d SRC_PITCH */ 865 dd_emit(ctx, 1, 0); /* 0000000f surf2d SRC_TILE_MODE_Z */ 866 dd_emit(ctx, 1, 2); /* 0000000f surf2d SRC_TILE_MODE_Y */ 867 dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_HEIGHT */ 868 dd_emit(ctx, 1, 1); /* 00000001 surf2d SRC_LINEAR */ 869 dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_WIDTH */ 870 871 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_X */ 872 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_Y */ 873 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_X */ 874 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_Y */ 875 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_X */ 876 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_Y */ 877 dd_emit(ctx, 1, 1); /* ffffffff gdirect COLOR_FORMAT */ 878 dd_emit(ctx, 1, 0); /* ffffffff gdirect OPERATION */ 879 dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_X */ 880 dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_Y */ 881 882 dd_emit(ctx, 1, 0); /* 0000ffff blit SRC_Y */ 883 dd_emit(ctx, 1, 0); /* ffffffff blit OPERATION */ 884 885 dd_emit(ctx, 1, 0); /* ffffffff ifc OPERATION */ 886 887 dd_emit(ctx, 1, 0); /* ffffffff iifc INDEX_FORMAT */ 888 dd_emit(ctx, 1, 0); /* ffffffff iifc LUT_OFFSET */ 889 dd_emit(ctx, 1, 4); /* ffffffff iifc COLOR_FORMAT */ 890 dd_emit(ctx, 1, 0); /* ffffffff iifc OPERATION */ 891 } 892 893 /* m2mf state */ 894 dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_COUNT */ 895 dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_LENGTH_IN */ 896 dd_emit(ctx, 2, 0); /* ffffffff m2mf OFFSET_IN, OFFSET_OUT */ 897 dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_OUT */ 898 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_OUT */ 899 dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_OUT_Z */ 900 dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_OUT */ 901 dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_OUT_X, Y */ 902 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_OUT */ 903 dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_IN */ 904 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_IN */ 905 dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_IN_Z */ 906 dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_IN */ 907 dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_IN_X, Y */ 908 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_IN */ 909 910 /* more compat 2d state */ 911 if (device->chipset == 0x50) { 912 dd_emit(ctx, 1, 1); /* ffffffff line COLOR_FORMAT */ 913 dd_emit(ctx, 1, 0); /* ffffffff line OPERATION */ 914 915 dd_emit(ctx, 1, 1); /* ffffffff triangle COLOR_FORMAT */ 916 dd_emit(ctx, 1, 0); /* ffffffff triangle OPERATION */ 917 918 dd_emit(ctx, 1, 0); /* 0000000f sifm TILE_MODE_Z */ 919 dd_emit(ctx, 1, 2); /* 0000000f sifm TILE_MODE_Y */ 920 dd_emit(ctx, 1, 0); /* 000000ff sifm FORMAT_FILTER */ 921 dd_emit(ctx, 1, 1); /* 000000ff sifm FORMAT_ORIGIN */ 922 dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_PITCH */ 923 dd_emit(ctx, 1, 1); /* 00000001 sifm SRC_LINEAR */ 924 dd_emit(ctx, 1, 0); /* 000000ff sifm SRC_OFFSET_HIGH */ 925 dd_emit(ctx, 1, 0); /* ffffffff sifm SRC_OFFSET */ 926 dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_HEIGHT */ 927 dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_WIDTH */ 928 dd_emit(ctx, 1, 3); /* ffffffff sifm COLOR_FORMAT */ 929 dd_emit(ctx, 1, 0); /* ffffffff sifm OPERATION */ 930 931 dd_emit(ctx, 1, 0); /* ffffffff sifc OPERATION */ 932 } 933 934 /* tesla state */ 935 dd_emit(ctx, 1, 0); /* 0000000f GP_TEXTURES_LOG2 */ 936 dd_emit(ctx, 1, 0); /* 0000000f GP_SAMPLERS_LOG2 */ 937 dd_emit(ctx, 1, 0); /* 000000ff */ 938 dd_emit(ctx, 1, 0); /* ffffffff */ 939 dd_emit(ctx, 1, 4); /* 000000ff UNK12B0_0 */ 940 dd_emit(ctx, 1, 0x70); /* 000000ff UNK12B0_1 */ 941 dd_emit(ctx, 1, 0x80); /* 000000ff UNK12B0_3 */ 942 dd_emit(ctx, 1, 0); /* 000000ff UNK12B0_2 */ 943 dd_emit(ctx, 1, 0); /* 0000000f FP_TEXTURES_LOG2 */ 944 dd_emit(ctx, 1, 0); /* 0000000f FP_SAMPLERS_LOG2 */ 945 if (IS_NVA3F(device->chipset)) { 946 dd_emit(ctx, 1, 0); /* ffffffff */ 947 dd_emit(ctx, 1, 0); /* 0000007f MULTISAMPLE_SAMPLES_LOG2 */ 948 } else { 949 dd_emit(ctx, 1, 0); /* 0000000f MULTISAMPLE_SAMPLES_LOG2 */ 950 } 951 dd_emit(ctx, 1, 0xc); /* 000000ff SEMANTIC_COLOR.BFC0_ID */ 952 if (device->chipset != 0x50) 953 dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_COLOR.CLMP_EN */ 954 dd_emit(ctx, 1, 8); /* 000000ff SEMANTIC_COLOR.COLR_NR */ 955 dd_emit(ctx, 1, 0x14); /* 000000ff SEMANTIC_COLOR.FFC0_ID */ 956 if (device->chipset == 0x50) { 957 dd_emit(ctx, 1, 0); /* 000000ff SEMANTIC_LAYER */ 958 dd_emit(ctx, 1, 0); /* 00000001 */ 959 } else { 960 dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_PTSZ.ENABLE */ 961 dd_emit(ctx, 1, 0x29); /* 000000ff SEMANTIC_PTSZ.PTSZ_ID */ 962 dd_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM */ 963 dd_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ 964 dd_emit(ctx, 1, 8); /* 0000000f SMENATIC_CLIP.CLIP_HIGH */ 965 dd_emit(ctx, 1, 4); /* 000000ff SEMANTIC_CLIP.CLIP_LO */ 966 dd_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */ 967 dd_emit(ctx, 1, 0); /* 00000001 UNK1900 */ 968 } 969 dd_emit(ctx, 1, 0); /* 00000007 RT_CONTROL_MAP0 */ 970 dd_emit(ctx, 1, 1); /* 00000007 RT_CONTROL_MAP1 */ 971 dd_emit(ctx, 1, 2); /* 00000007 RT_CONTROL_MAP2 */ 972 dd_emit(ctx, 1, 3); /* 00000007 RT_CONTROL_MAP3 */ 973 dd_emit(ctx, 1, 4); /* 00000007 RT_CONTROL_MAP4 */ 974 dd_emit(ctx, 1, 5); /* 00000007 RT_CONTROL_MAP5 */ 975 dd_emit(ctx, 1, 6); /* 00000007 RT_CONTROL_MAP6 */ 976 dd_emit(ctx, 1, 7); /* 00000007 RT_CONTROL_MAP7 */ 977 dd_emit(ctx, 1, 1); /* 0000000f RT_CONTROL_COUNT */ 978 dd_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_UNK */ 979 dd_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */ 980 dd_emit(ctx, 1, 0xcf); /* 000000ff RT_FORMAT */ 981 dd_emit(ctx, 7, 0); /* 000000ff RT_FORMAT */ 982 if (device->chipset != 0x50) 983 dd_emit(ctx, 3, 0); /* 1, 1, 1 */ 984 else 985 dd_emit(ctx, 2, 0); /* 1, 1 */ 986 dd_emit(ctx, 1, 0); /* ffffffff GP_ENABLE */ 987 dd_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT*/ 988 dd_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ 989 dd_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 990 if (IS_NVA3F(device->chipset)) { 991 dd_emit(ctx, 1, 3); /* 00000003 */ 992 dd_emit(ctx, 1, 0); /* 00000001 UNK1418. Alone. */ 993 } 994 if (device->chipset != 0x50) 995 dd_emit(ctx, 1, 3); /* 00000003 UNK15AC */ 996 dd_emit(ctx, 1, 1); /* ffffffff RASTERIZE_ENABLE */ 997 dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.EXPORTS_Z */ 998 if (device->chipset != 0x50) 999 dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.MULTIPLE_RESULTS */ 1000 dd_emit(ctx, 1, 0x12); /* 000000ff FP_INTERPOLANT_CTRL.COUNT */ 1001 dd_emit(ctx, 1, 0x10); /* 000000ff FP_INTERPOLANT_CTRL.COUNT_NONFLAT */ 1002 dd_emit(ctx, 1, 0xc); /* 000000ff FP_INTERPOLANT_CTRL.OFFSET */ 1003 dd_emit(ctx, 1, 1); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.W */ 1004 dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.X */ 1005 dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Y */ 1006 dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Z */ 1007 dd_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */ 1008 dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */ 1009 dd_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ 1010 if (device->chipset >= 0xa0) 1011 dd_emit(ctx, 1, 0); /* ffffffff */ 1012 dd_emit(ctx, 1, 0); /* 00000001 GP_BUILTIN_RESULT_EN.LAYER_IDX */ 1013 dd_emit(ctx, 1, 0); /* ffffffff STRMOUT_ENABLE */ 1014 dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ 1015 dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ 1016 dd_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE*/ 1017 if (device->chipset != 0x50) 1018 dd_emit(ctx, 8, 0); /* 00000001 */ 1019 if (device->chipset >= 0xa0) { 1020 dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.COMP */ 1021 dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.SIZE */ 1022 dd_emit(ctx, 1, 2); /* 00000007 VTX_ATTR_DEFINE.TYPE */ 1023 dd_emit(ctx, 1, 0); /* 000000ff VTX_ATTR_DEFINE.ATTR */ 1024 } 1025 dd_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1026 dd_emit(ctx, 1, 0x14); /* 0000001f ZETA_FORMAT */ 1027 dd_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 1028 dd_emit(ctx, 1, 0); /* 0000000f VP_TEXTURES_LOG2 */ 1029 dd_emit(ctx, 1, 0); /* 0000000f VP_SAMPLERS_LOG2 */ 1030 if (IS_NVA3F(device->chipset)) 1031 dd_emit(ctx, 1, 0); /* 00000001 */ 1032 dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_BACK */ 1033 if (device->chipset >= 0xa0) 1034 dd_emit(ctx, 1, 0); /* 00000003 VTX_ATTR_DEFINE.SIZE - 1 */ 1035 dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */ 1036 if (device->chipset >= 0xa0) 1037 dd_emit(ctx, 1, 0); /* 00000003 */ 1038 dd_emit(ctx, 1, 0); /* 00000001 CULL_FACE_ENABLE */ 1039 dd_emit(ctx, 1, 1); /* 00000003 CULL_FACE */ 1040 dd_emit(ctx, 1, 0); /* 00000001 FRONT_FACE */ 1041 dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_FRONT */ 1042 dd_emit(ctx, 1, 0x1000); /* 00007fff UNK141C */ 1043 if (device->chipset != 0x50) { 1044 dd_emit(ctx, 1, 0xe00); /* 7fff */ 1045 dd_emit(ctx, 1, 0x1000); /* 7fff */ 1046 dd_emit(ctx, 1, 0x1e00); /* 7fff */ 1047 } 1048 dd_emit(ctx, 1, 0); /* 00000001 BEGIN_END_ACTIVE */ 1049 dd_emit(ctx, 1, 1); /* 00000001 POLYGON_MODE_??? */ 1050 dd_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP / 4 rounded up */ 1051 dd_emit(ctx, 1, 1); /* 000000ff FP_REG_ALLOC_TEMP... without /4? */ 1052 dd_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP / 4 rounded up */ 1053 dd_emit(ctx, 1, 1); /* 00000001 */ 1054 dd_emit(ctx, 1, 0); /* 00000001 */ 1055 dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK0 nonempty */ 1056 dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK1 nonempty */ 1057 dd_emit(ctx, 1, 0x200); /* 0003ffff GP_VERTEX_OUTPUT_COUNT*GP_REG_ALLOC_RESULT */ 1058 if (IS_NVA3F(device->chipset)) 1059 dd_emit(ctx, 1, 0x200); 1060 dd_emit(ctx, 1, 0); /* 00000001 */ 1061 if (device->chipset < 0xa0) { 1062 dd_emit(ctx, 1, 1); /* 00000001 */ 1063 dd_emit(ctx, 1, 0x70); /* 000000ff */ 1064 dd_emit(ctx, 1, 0x80); /* 000000ff */ 1065 dd_emit(ctx, 1, 0); /* 000000ff */ 1066 dd_emit(ctx, 1, 0); /* 00000001 */ 1067 dd_emit(ctx, 1, 1); /* 00000001 */ 1068 dd_emit(ctx, 1, 0x70); /* 000000ff */ 1069 dd_emit(ctx, 1, 0x80); /* 000000ff */ 1070 dd_emit(ctx, 1, 0); /* 000000ff */ 1071 } else { 1072 dd_emit(ctx, 1, 1); /* 00000001 */ 1073 dd_emit(ctx, 1, 0xf0); /* 000000ff */ 1074 dd_emit(ctx, 1, 0xff); /* 000000ff */ 1075 dd_emit(ctx, 1, 0); /* 000000ff */ 1076 dd_emit(ctx, 1, 0); /* 00000001 */ 1077 dd_emit(ctx, 1, 1); /* 00000001 */ 1078 dd_emit(ctx, 1, 0xf0); /* 000000ff */ 1079 dd_emit(ctx, 1, 0xff); /* 000000ff */ 1080 dd_emit(ctx, 1, 0); /* 000000ff */ 1081 dd_emit(ctx, 1, 9); /* 0000003f UNK114C.COMP,SIZE */ 1082 } 1083 1084 /* eng2d state */ 1085 dd_emit(ctx, 1, 0); /* 00000001 eng2d COLOR_KEY_ENABLE */ 1086 dd_emit(ctx, 1, 0); /* 00000007 eng2d COLOR_KEY_FORMAT */ 1087 dd_emit(ctx, 1, 1); /* ffffffff eng2d DST_DEPTH */ 1088 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DST_FORMAT */ 1089 dd_emit(ctx, 1, 0); /* ffffffff eng2d DST_LAYER */ 1090 dd_emit(ctx, 1, 1); /* 00000001 eng2d DST_LINEAR */ 1091 dd_emit(ctx, 1, 0); /* 00000007 eng2d PATTERN_COLOR_FORMAT */ 1092 dd_emit(ctx, 1, 0); /* 00000007 eng2d OPERATION */ 1093 dd_emit(ctx, 1, 0); /* 00000003 eng2d PATTERN_SELECT */ 1094 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SIFC_FORMAT */ 1095 dd_emit(ctx, 1, 0); /* 00000001 eng2d SIFC_BITMAP_ENABLE */ 1096 dd_emit(ctx, 1, 2); /* 00000003 eng2d SIFC_BITMAP_UNK808 */ 1097 dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DU_DX_FRACT */ 1098 dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DU_DX_INT */ 1099 dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DV_DY_FRACT */ 1100 dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DV_DY_INT */ 1101 dd_emit(ctx, 1, 0); /* 00000001 eng2d BLIT_CONTROL_FILTER */ 1102 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DRAW_COLOR_FORMAT */ 1103 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SRC_FORMAT */ 1104 dd_emit(ctx, 1, 1); /* 00000001 eng2d SRC_LINEAR #2 */ 1105 1106 num = ctx->ctxvals_pos - base; 1107 ctx->ctxvals_pos = base; 1108 if (IS_NVA3F(device->chipset)) 1109 cp_ctx(ctx, 0x404800, num); 1110 else 1111 cp_ctx(ctx, 0x405400, num); 1112 } 1113 1114 /* 1115 * xfer areas. These are a pain. 1116 * 1117 * There are 2 xfer areas: the first one is big and contains all sorts of 1118 * stuff, the second is small and contains some per-TP context. 1119 * 1120 * Each area is split into 8 "strands". The areas, when saved to grctx, 1121 * are made of 8-word blocks. Each block contains a single word from 1122 * each strand. The strands are independent of each other, their 1123 * addresses are unrelated to each other, and data in them is closely 1124 * packed together. The strand layout varies a bit between cards: here 1125 * and there, a single word is thrown out in the middle and the whole 1126 * strand is offset by a bit from corresponding one on another chipset. 1127 * For this reason, addresses of stuff in strands are almost useless. 1128 * Knowing sequence of stuff and size of gaps between them is much more 1129 * useful, and that's how we build the strands in our generator. 1130 * 1131 * NVA0 takes this mess to a whole new level by cutting the old strands 1132 * into a few dozen pieces [known as genes], rearranging them randomly, 1133 * and putting them back together to make new strands. Hopefully these 1134 * genes correspond more or less directly to the same PGRAPH subunits 1135 * as in 400040 register. 1136 * 1137 * The most common value in default context is 0, and when the genes 1138 * are separated by 0's, gene bounduaries are quite speculative... 1139 * some of them can be clearly deduced, others can be guessed, and yet 1140 * others won't be resolved without figuring out the real meaning of 1141 * given ctxval. For the same reason, ending point of each strand 1142 * is unknown. Except for strand 0, which is the longest strand and 1143 * its end corresponds to end of the whole xfer. 1144 * 1145 * An unsolved mystery is the seek instruction: it takes an argument 1146 * in bits 8-18, and that argument is clearly the place in strands to 1147 * seek to... but the offsets don't seem to correspond to offsets as 1148 * seen in grctx. Perhaps there's another, real, not randomly-changing 1149 * addressing in strands, and the xfer insn just happens to skip over 1150 * the unused bits? NV10-NV30 PIPE comes to mind... 1151 * 1152 * As far as I know, there's no way to access the xfer areas directly 1153 * without the help of ctxprog. 1154 */ 1155 1156 static void 1157 xf_emit(struct nvkm_grctx *ctx, int num, u32 val) { 1158 int i; 1159 if (val && ctx->mode == NVKM_GRCTX_VALS) { 1160 for (i = 0; i < num; i++) 1161 nvkm_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val); 1162 } 1163 ctx->ctxvals_pos += num << 3; 1164 } 1165 1166 /* Gene declarations... */ 1167 1168 static void nv50_gr_construct_gene_dispatch(struct nvkm_grctx *ctx); 1169 static void nv50_gr_construct_gene_m2mf(struct nvkm_grctx *ctx); 1170 static void nv50_gr_construct_gene_ccache(struct nvkm_grctx *ctx); 1171 static void nv50_gr_construct_gene_unk10xx(struct nvkm_grctx *ctx); 1172 static void nv50_gr_construct_gene_unk14xx(struct nvkm_grctx *ctx); 1173 static void nv50_gr_construct_gene_zcull(struct nvkm_grctx *ctx); 1174 static void nv50_gr_construct_gene_clipid(struct nvkm_grctx *ctx); 1175 static void nv50_gr_construct_gene_unk24xx(struct nvkm_grctx *ctx); 1176 static void nv50_gr_construct_gene_vfetch(struct nvkm_grctx *ctx); 1177 static void nv50_gr_construct_gene_eng2d(struct nvkm_grctx *ctx); 1178 static void nv50_gr_construct_gene_csched(struct nvkm_grctx *ctx); 1179 static void nv50_gr_construct_gene_unk1cxx(struct nvkm_grctx *ctx); 1180 static void nv50_gr_construct_gene_strmout(struct nvkm_grctx *ctx); 1181 static void nv50_gr_construct_gene_unk34xx(struct nvkm_grctx *ctx); 1182 static void nv50_gr_construct_gene_ropm1(struct nvkm_grctx *ctx); 1183 static void nv50_gr_construct_gene_ropm2(struct nvkm_grctx *ctx); 1184 static void nv50_gr_construct_gene_ropc(struct nvkm_grctx *ctx); 1185 static void nv50_gr_construct_xfer_tp(struct nvkm_grctx *ctx); 1186 1187 static void 1188 nv50_gr_construct_xfer1(struct nvkm_grctx *ctx) 1189 { 1190 struct nvkm_device *device = ctx->device; 1191 int i; 1192 int offset; 1193 int size = 0; 1194 u32 units = nvkm_rd32(device, 0x1540); 1195 1196 offset = (ctx->ctxvals_pos+0x3f)&~0x3f; 1197 ctx->ctxvals_base = offset; 1198 1199 if (device->chipset < 0xa0) { 1200 /* Strand 0 */ 1201 ctx->ctxvals_pos = offset; 1202 nv50_gr_construct_gene_dispatch(ctx); 1203 nv50_gr_construct_gene_m2mf(ctx); 1204 nv50_gr_construct_gene_unk24xx(ctx); 1205 nv50_gr_construct_gene_clipid(ctx); 1206 nv50_gr_construct_gene_zcull(ctx); 1207 if ((ctx->ctxvals_pos-offset)/8 > size) 1208 size = (ctx->ctxvals_pos-offset)/8; 1209 1210 /* Strand 1 */ 1211 ctx->ctxvals_pos = offset + 0x1; 1212 nv50_gr_construct_gene_vfetch(ctx); 1213 nv50_gr_construct_gene_eng2d(ctx); 1214 nv50_gr_construct_gene_csched(ctx); 1215 nv50_gr_construct_gene_ropm1(ctx); 1216 nv50_gr_construct_gene_ropm2(ctx); 1217 if ((ctx->ctxvals_pos-offset)/8 > size) 1218 size = (ctx->ctxvals_pos-offset)/8; 1219 1220 /* Strand 2 */ 1221 ctx->ctxvals_pos = offset + 0x2; 1222 nv50_gr_construct_gene_ccache(ctx); 1223 nv50_gr_construct_gene_unk1cxx(ctx); 1224 nv50_gr_construct_gene_strmout(ctx); 1225 nv50_gr_construct_gene_unk14xx(ctx); 1226 nv50_gr_construct_gene_unk10xx(ctx); 1227 nv50_gr_construct_gene_unk34xx(ctx); 1228 if ((ctx->ctxvals_pos-offset)/8 > size) 1229 size = (ctx->ctxvals_pos-offset)/8; 1230 1231 /* Strand 3: per-ROP group state */ 1232 ctx->ctxvals_pos = offset + 3; 1233 for (i = 0; i < 6; i++) 1234 if (units & (1 << (i + 16))) 1235 nv50_gr_construct_gene_ropc(ctx); 1236 if ((ctx->ctxvals_pos-offset)/8 > size) 1237 size = (ctx->ctxvals_pos-offset)/8; 1238 1239 /* Strands 4-7: per-TP state */ 1240 for (i = 0; i < 4; i++) { 1241 ctx->ctxvals_pos = offset + 4 + i; 1242 if (units & (1 << (2 * i))) 1243 nv50_gr_construct_xfer_tp(ctx); 1244 if (units & (1 << (2 * i + 1))) 1245 nv50_gr_construct_xfer_tp(ctx); 1246 if ((ctx->ctxvals_pos-offset)/8 > size) 1247 size = (ctx->ctxvals_pos-offset)/8; 1248 } 1249 } else { 1250 /* Strand 0 */ 1251 ctx->ctxvals_pos = offset; 1252 nv50_gr_construct_gene_dispatch(ctx); 1253 nv50_gr_construct_gene_m2mf(ctx); 1254 nv50_gr_construct_gene_unk34xx(ctx); 1255 nv50_gr_construct_gene_csched(ctx); 1256 nv50_gr_construct_gene_unk1cxx(ctx); 1257 nv50_gr_construct_gene_strmout(ctx); 1258 if ((ctx->ctxvals_pos-offset)/8 > size) 1259 size = (ctx->ctxvals_pos-offset)/8; 1260 1261 /* Strand 1 */ 1262 ctx->ctxvals_pos = offset + 1; 1263 nv50_gr_construct_gene_unk10xx(ctx); 1264 if ((ctx->ctxvals_pos-offset)/8 > size) 1265 size = (ctx->ctxvals_pos-offset)/8; 1266 1267 /* Strand 2 */ 1268 ctx->ctxvals_pos = offset + 2; 1269 if (device->chipset == 0xa0) 1270 nv50_gr_construct_gene_unk14xx(ctx); 1271 nv50_gr_construct_gene_unk24xx(ctx); 1272 if ((ctx->ctxvals_pos-offset)/8 > size) 1273 size = (ctx->ctxvals_pos-offset)/8; 1274 1275 /* Strand 3 */ 1276 ctx->ctxvals_pos = offset + 3; 1277 nv50_gr_construct_gene_vfetch(ctx); 1278 if ((ctx->ctxvals_pos-offset)/8 > size) 1279 size = (ctx->ctxvals_pos-offset)/8; 1280 1281 /* Strand 4 */ 1282 ctx->ctxvals_pos = offset + 4; 1283 nv50_gr_construct_gene_ccache(ctx); 1284 if ((ctx->ctxvals_pos-offset)/8 > size) 1285 size = (ctx->ctxvals_pos-offset)/8; 1286 1287 /* Strand 5 */ 1288 ctx->ctxvals_pos = offset + 5; 1289 nv50_gr_construct_gene_ropm2(ctx); 1290 nv50_gr_construct_gene_ropm1(ctx); 1291 /* per-ROP context */ 1292 for (i = 0; i < 8; i++) 1293 if (units & (1<<(i+16))) 1294 nv50_gr_construct_gene_ropc(ctx); 1295 if ((ctx->ctxvals_pos-offset)/8 > size) 1296 size = (ctx->ctxvals_pos-offset)/8; 1297 1298 /* Strand 6 */ 1299 ctx->ctxvals_pos = offset + 6; 1300 nv50_gr_construct_gene_zcull(ctx); 1301 nv50_gr_construct_gene_clipid(ctx); 1302 nv50_gr_construct_gene_eng2d(ctx); 1303 if (units & (1 << 0)) 1304 nv50_gr_construct_xfer_tp(ctx); 1305 if (units & (1 << 1)) 1306 nv50_gr_construct_xfer_tp(ctx); 1307 if (units & (1 << 2)) 1308 nv50_gr_construct_xfer_tp(ctx); 1309 if (units & (1 << 3)) 1310 nv50_gr_construct_xfer_tp(ctx); 1311 if ((ctx->ctxvals_pos-offset)/8 > size) 1312 size = (ctx->ctxvals_pos-offset)/8; 1313 1314 /* Strand 7 */ 1315 ctx->ctxvals_pos = offset + 7; 1316 if (device->chipset == 0xa0) { 1317 if (units & (1 << 4)) 1318 nv50_gr_construct_xfer_tp(ctx); 1319 if (units & (1 << 5)) 1320 nv50_gr_construct_xfer_tp(ctx); 1321 if (units & (1 << 6)) 1322 nv50_gr_construct_xfer_tp(ctx); 1323 if (units & (1 << 7)) 1324 nv50_gr_construct_xfer_tp(ctx); 1325 if (units & (1 << 8)) 1326 nv50_gr_construct_xfer_tp(ctx); 1327 if (units & (1 << 9)) 1328 nv50_gr_construct_xfer_tp(ctx); 1329 } else { 1330 nv50_gr_construct_gene_unk14xx(ctx); 1331 } 1332 if ((ctx->ctxvals_pos-offset)/8 > size) 1333 size = (ctx->ctxvals_pos-offset)/8; 1334 } 1335 1336 ctx->ctxvals_pos = offset + size * 8; 1337 ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f; 1338 cp_lsr (ctx, offset); 1339 cp_out (ctx, CP_SET_XFER_POINTER); 1340 cp_lsr (ctx, size); 1341 cp_out (ctx, CP_SEEK_1); 1342 cp_out (ctx, CP_XFER_1); 1343 cp_wait(ctx, XFER, BUSY); 1344 } 1345 1346 /* 1347 * non-trivial demagiced parts of ctx init go here 1348 */ 1349 1350 static void 1351 nv50_gr_construct_gene_dispatch(struct nvkm_grctx *ctx) 1352 { 1353 /* start of strand 0 */ 1354 struct nvkm_device *device = ctx->device; 1355 /* SEEK */ 1356 if (device->chipset == 0x50) 1357 xf_emit(ctx, 5, 0); 1358 else if (!IS_NVA3F(device->chipset)) 1359 xf_emit(ctx, 6, 0); 1360 else 1361 xf_emit(ctx, 4, 0); 1362 /* SEEK */ 1363 /* the PGRAPH's internal FIFO */ 1364 if (device->chipset == 0x50) 1365 xf_emit(ctx, 8*3, 0); 1366 else 1367 xf_emit(ctx, 0x100*3, 0); 1368 /* and another bonus slot?!? */ 1369 xf_emit(ctx, 3, 0); 1370 /* and YET ANOTHER bonus slot? */ 1371 if (IS_NVA3F(device->chipset)) 1372 xf_emit(ctx, 3, 0); 1373 /* SEEK */ 1374 /* CTX_SWITCH: caches of gr objects bound to subchannels. 8 values, last used index */ 1375 xf_emit(ctx, 9, 0); 1376 /* SEEK */ 1377 xf_emit(ctx, 9, 0); 1378 /* SEEK */ 1379 xf_emit(ctx, 9, 0); 1380 /* SEEK */ 1381 xf_emit(ctx, 9, 0); 1382 /* SEEK */ 1383 if (device->chipset < 0x90) 1384 xf_emit(ctx, 4, 0); 1385 /* SEEK */ 1386 xf_emit(ctx, 2, 0); 1387 /* SEEK */ 1388 xf_emit(ctx, 6*2, 0); 1389 xf_emit(ctx, 2, 0); 1390 /* SEEK */ 1391 xf_emit(ctx, 2, 0); 1392 /* SEEK */ 1393 xf_emit(ctx, 6*2, 0); 1394 xf_emit(ctx, 2, 0); 1395 /* SEEK */ 1396 if (device->chipset == 0x50) 1397 xf_emit(ctx, 0x1c, 0); 1398 else if (device->chipset < 0xa0) 1399 xf_emit(ctx, 0x1e, 0); 1400 else 1401 xf_emit(ctx, 0x22, 0); 1402 /* SEEK */ 1403 xf_emit(ctx, 0x15, 0); 1404 } 1405 1406 static void 1407 nv50_gr_construct_gene_m2mf(struct nvkm_grctx *ctx) 1408 { 1409 /* Strand 0, right after dispatch */ 1410 struct nvkm_device *device = ctx->device; 1411 int smallm2mf = 0; 1412 if (device->chipset < 0x92 || device->chipset == 0x98) 1413 smallm2mf = 1; 1414 /* SEEK */ 1415 xf_emit (ctx, 1, 0); /* DMA_NOTIFY instance >> 4 */ 1416 xf_emit (ctx, 1, 0); /* DMA_BUFFER_IN instance >> 4 */ 1417 xf_emit (ctx, 1, 0); /* DMA_BUFFER_OUT instance >> 4 */ 1418 xf_emit (ctx, 1, 0); /* OFFSET_IN */ 1419 xf_emit (ctx, 1, 0); /* OFFSET_OUT */ 1420 xf_emit (ctx, 1, 0); /* PITCH_IN */ 1421 xf_emit (ctx, 1, 0); /* PITCH_OUT */ 1422 xf_emit (ctx, 1, 0); /* LINE_LENGTH */ 1423 xf_emit (ctx, 1, 0); /* LINE_COUNT */ 1424 xf_emit (ctx, 1, 0x21); /* FORMAT: bits 0-4 INPUT_INC, bits 5-9 OUTPUT_INC */ 1425 xf_emit (ctx, 1, 1); /* LINEAR_IN */ 1426 xf_emit (ctx, 1, 0x2); /* TILING_MODE_IN: bits 0-2 y tiling, bits 3-5 z tiling */ 1427 xf_emit (ctx, 1, 0x100); /* TILING_PITCH_IN */ 1428 xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_IN */ 1429 xf_emit (ctx, 1, 1); /* TILING_DEPTH_IN */ 1430 xf_emit (ctx, 1, 0); /* TILING_POSITION_IN_Z */ 1431 xf_emit (ctx, 1, 0); /* TILING_POSITION_IN */ 1432 xf_emit (ctx, 1, 1); /* LINEAR_OUT */ 1433 xf_emit (ctx, 1, 0x2); /* TILING_MODE_OUT: bits 0-2 y tiling, bits 3-5 z tiling */ 1434 xf_emit (ctx, 1, 0x100); /* TILING_PITCH_OUT */ 1435 xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_OUT */ 1436 xf_emit (ctx, 1, 1); /* TILING_DEPTH_OUT */ 1437 xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT_Z */ 1438 xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT */ 1439 xf_emit (ctx, 1, 0); /* OFFSET_IN_HIGH */ 1440 xf_emit (ctx, 1, 0); /* OFFSET_OUT_HIGH */ 1441 /* SEEK */ 1442 if (smallm2mf) 1443 xf_emit(ctx, 0x40, 0); /* 20 * ffffffff, 3ffff */ 1444 else 1445 xf_emit(ctx, 0x100, 0); /* 80 * ffffffff, 3ffff */ 1446 xf_emit(ctx, 4, 0); /* 1f/7f, 0, 1f/7f, 0 [1f for smallm2mf, 7f otherwise] */ 1447 /* SEEK */ 1448 if (smallm2mf) 1449 xf_emit(ctx, 0x400, 0); /* ffffffff */ 1450 else 1451 xf_emit(ctx, 0x800, 0); /* ffffffff */ 1452 xf_emit(ctx, 4, 0); /* ff/1ff, 0, 0, 0 [ff for smallm2mf, 1ff otherwise] */ 1453 /* SEEK */ 1454 xf_emit(ctx, 0x40, 0); /* 20 * bits ffffffff, 3ffff */ 1455 xf_emit(ctx, 0x6, 0); /* 1f, 0, 1f, 0, 1f, 0 */ 1456 } 1457 1458 static void 1459 nv50_gr_construct_gene_ccache(struct nvkm_grctx *ctx) 1460 { 1461 struct nvkm_device *device = ctx->device; 1462 xf_emit(ctx, 2, 0); /* RO */ 1463 xf_emit(ctx, 0x800, 0); /* ffffffff */ 1464 switch (device->chipset) { 1465 case 0x50: 1466 case 0x92: 1467 case 0xa0: 1468 xf_emit(ctx, 0x2b, 0); 1469 break; 1470 case 0x84: 1471 xf_emit(ctx, 0x29, 0); 1472 break; 1473 case 0x94: 1474 case 0x96: 1475 case 0xa3: 1476 xf_emit(ctx, 0x27, 0); 1477 break; 1478 case 0x86: 1479 case 0x98: 1480 case 0xa5: 1481 case 0xa8: 1482 case 0xaa: 1483 case 0xac: 1484 case 0xaf: 1485 xf_emit(ctx, 0x25, 0); 1486 break; 1487 } 1488 /* CB bindings, 0x80 of them. first word is address >> 8, second is 1489 * size >> 4 | valid << 24 */ 1490 xf_emit(ctx, 0x100, 0); /* ffffffff CB_DEF */ 1491 xf_emit(ctx, 1, 0); /* 0000007f CB_ADDR_BUFFER */ 1492 xf_emit(ctx, 1, 0); /* 0 */ 1493 xf_emit(ctx, 0x30, 0); /* ff SET_PROGRAM_CB */ 1494 xf_emit(ctx, 1, 0); /* 3f last SET_PROGRAM_CB */ 1495 xf_emit(ctx, 4, 0); /* RO */ 1496 xf_emit(ctx, 0x100, 0); /* ffffffff */ 1497 xf_emit(ctx, 8, 0); /* 1f, 0, 0, ... */ 1498 xf_emit(ctx, 8, 0); /* ffffffff */ 1499 xf_emit(ctx, 4, 0); /* ffffffff */ 1500 xf_emit(ctx, 1, 0); /* 3 */ 1501 xf_emit(ctx, 1, 0); /* ffffffff */ 1502 xf_emit(ctx, 1, 0); /* 0000ffff DMA_CODE_CB */ 1503 xf_emit(ctx, 1, 0); /* 0000ffff DMA_TIC */ 1504 xf_emit(ctx, 1, 0); /* 0000ffff DMA_TSC */ 1505 xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */ 1506 xf_emit(ctx, 1, 0); /* 000000ff TIC_ADDRESS_HIGH */ 1507 xf_emit(ctx, 1, 0); /* ffffffff TIC_ADDRESS_LOW */ 1508 xf_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ 1509 xf_emit(ctx, 1, 0); /* 000000ff TSC_ADDRESS_HIGH */ 1510 xf_emit(ctx, 1, 0); /* ffffffff TSC_ADDRESS_LOW */ 1511 xf_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ 1512 xf_emit(ctx, 1, 0); /* 000000ff VP_ADDRESS_HIGH */ 1513 xf_emit(ctx, 1, 0); /* ffffffff VP_ADDRESS_LOW */ 1514 xf_emit(ctx, 1, 0); /* 00ffffff VP_START_ID */ 1515 xf_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */ 1516 xf_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */ 1517 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1518 xf_emit(ctx, 1, 0); /* 000000ff GP_ADDRESS_HIGH */ 1519 xf_emit(ctx, 1, 0); /* ffffffff GP_ADDRESS_LOW */ 1520 xf_emit(ctx, 1, 0); /* 00ffffff GP_START_ID */ 1521 xf_emit(ctx, 1, 0); /* 000000ff FP_ADDRESS_HIGH */ 1522 xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */ 1523 xf_emit(ctx, 1, 0); /* 00ffffff FP_START_ID */ 1524 } 1525 1526 static void 1527 nv50_gr_construct_gene_unk10xx(struct nvkm_grctx *ctx) 1528 { 1529 struct nvkm_device *device = ctx->device; 1530 int i; 1531 /* end of area 2 on pre-NVA0, area 1 on NVAx */ 1532 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1533 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1534 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1535 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ 1536 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ 1537 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1538 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ 1539 if (device->chipset == 0x50) 1540 xf_emit(ctx, 1, 0x3ff); 1541 else 1542 xf_emit(ctx, 1, 0x7ff); /* 000007ff */ 1543 xf_emit(ctx, 1, 0); /* 111/113 */ 1544 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1545 for (i = 0; i < 8; i++) { 1546 switch (device->chipset) { 1547 case 0x50: 1548 case 0x86: 1549 case 0x98: 1550 case 0xaa: 1551 case 0xac: 1552 xf_emit(ctx, 0xa0, 0); /* ffffffff */ 1553 break; 1554 case 0x84: 1555 case 0x92: 1556 case 0x94: 1557 case 0x96: 1558 xf_emit(ctx, 0x120, 0); 1559 break; 1560 case 0xa5: 1561 case 0xa8: 1562 xf_emit(ctx, 0x100, 0); /* ffffffff */ 1563 break; 1564 case 0xa0: 1565 case 0xa3: 1566 case 0xaf: 1567 xf_emit(ctx, 0x400, 0); /* ffffffff */ 1568 break; 1569 } 1570 xf_emit(ctx, 4, 0); /* 3f, 0, 0, 0 */ 1571 xf_emit(ctx, 4, 0); /* ffffffff */ 1572 } 1573 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1574 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1575 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1576 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ 1577 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_TEMP */ 1578 xf_emit(ctx, 1, 1); /* 00000001 RASTERIZE_ENABLE */ 1579 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1580 xf_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */ 1581 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 1582 xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ 1583 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1584 } 1585 1586 static void 1587 nv50_gr_construct_gene_unk34xx(struct nvkm_grctx *ctx) 1588 { 1589 struct nvkm_device *device = ctx->device; 1590 /* end of area 2 on pre-NVA0, area 1 on NVAx */ 1591 xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */ 1592 xf_emit(ctx, 1, 0); /* 00000003 VIEWPORT_CLIP_MODE */ 1593 xf_emit(ctx, 0x10, 0x04000000); /* 07ffffff VIEWPORT_CLIP_HORIZ*8, VIEWPORT_CLIP_VERT*8 */ 1594 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */ 1595 xf_emit(ctx, 0x20, 0); /* ffffffff POLYGON_STIPPLE */ 1596 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ 1597 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 1598 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */ 1599 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */ 1600 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 1601 xf_emit(ctx, 1, 0); /* 00000007 */ 1602 xf_emit(ctx, 1, 0x1fe21); /* 0001ffff tesla UNK0FAC */ 1603 if (device->chipset >= 0xa0) 1604 xf_emit(ctx, 1, 0x0fac6881); 1605 if (IS_NVA3F(device->chipset)) { 1606 xf_emit(ctx, 1, 1); 1607 xf_emit(ctx, 3, 0); 1608 } 1609 } 1610 1611 static void 1612 nv50_gr_construct_gene_unk14xx(struct nvkm_grctx *ctx) 1613 { 1614 struct nvkm_device *device = ctx->device; 1615 /* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */ 1616 if (device->chipset != 0x50) { 1617 xf_emit(ctx, 5, 0); /* ffffffff */ 1618 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1619 xf_emit(ctx, 1, 0); /* 00000001 */ 1620 xf_emit(ctx, 1, 0); /* 000003ff */ 1621 xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */ 1622 xf_emit(ctx, 1, 0); /* 00000001 */ 1623 xf_emit(ctx, 2, 4); /* 7f, ff */ 1624 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1625 } 1626 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1627 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1628 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1629 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1630 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ 1631 xf_emit(ctx, 1, 0); /* 000000ff VP_CLIP_DISTANCE_ENABLE */ 1632 if (device->chipset != 0x50) 1633 xf_emit(ctx, 1, 0); /* 3ff */ 1634 xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1940 */ 1635 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */ 1636 xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */ 1637 xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ 1638 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 1639 if (device->chipset != 0x50) 1640 xf_emit(ctx, 1, 0x7f); /* 000000ff tesla UNK0FFC */ 1641 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1642 xf_emit(ctx, 1, 1); /* 00000001 SHADE_MODEL */ 1643 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1644 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1645 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1646 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1647 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1648 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1649 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ 1650 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */ 1651 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0F8C */ 1652 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1653 xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ 1654 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1655 xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */ 1656 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1657 xf_emit(ctx, 1, 0); /* 0000000f */ 1658 if (device->chipset == 0x50) 1659 xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */ 1660 else 1661 xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */ 1662 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1663 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ 1664 xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_SCALE: X0, Y0, Z0, X1, Y1, ... */ 1665 xf_emit(ctx, 3, 0); /* f, 0, 0 */ 1666 xf_emit(ctx, 3, 0); /* ffffffff last VIEWPORT_SCALE? */ 1667 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1668 xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ 1669 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1670 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ 1671 xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ 1672 xf_emit(ctx, 1, 0); /* 00000001 */ 1673 xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_TRANSLATE */ 1674 xf_emit(ctx, 3, 0); /* f, 0, 0 */ 1675 xf_emit(ctx, 3, 0); /* ffffffff */ 1676 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1677 xf_emit(ctx, 2, 0x88); /* 000001ff tesla UNK19D8 */ 1678 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ 1679 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1680 xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ 1681 xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ 1682 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ 1683 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 1684 xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ 1685 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 1686 xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ 1687 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1688 xf_emit(ctx, 1, 0); /* 0000000f */ 1689 xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */ 1690 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 1691 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ 1692 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 1693 if (IS_NVA3F(device->chipset)) 1694 xf_emit(ctx, 1, 0); /* 00000001 */ 1695 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 1696 xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ 1697 if (device->chipset != 0x50) { 1698 xf_emit(ctx, 1, 0); /* ffffffff */ 1699 xf_emit(ctx, 1, 0); /* 00000001 */ 1700 xf_emit(ctx, 1, 0); /* 000003ff */ 1701 } 1702 xf_emit(ctx, 0x20, 0); /* 10xbits ffffffff, 3fffff. SCISSOR_* */ 1703 xf_emit(ctx, 1, 0); /* f */ 1704 xf_emit(ctx, 1, 0); /* 0? */ 1705 xf_emit(ctx, 1, 0); /* ffffffff */ 1706 xf_emit(ctx, 1, 0); /* 003fffff */ 1707 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1708 xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */ 1709 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 1710 xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ 1711 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1712 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1713 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1714 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1715 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 1716 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ 1717 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 1718 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ 1719 xf_emit(ctx, 1, 0); /* 0000000f */ 1720 } 1721 1722 static void 1723 nv50_gr_construct_gene_zcull(struct nvkm_grctx *ctx) 1724 { 1725 struct nvkm_device *device = ctx->device; 1726 /* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */ 1727 /* SEEK */ 1728 xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */ 1729 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ 1730 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 1731 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 1732 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ 1733 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ 1734 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ 1735 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ 1736 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ 1737 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ 1738 xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */ 1739 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 1740 xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */ 1741 xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ 1742 xf_emit(ctx, 1, 0); /* 00000001 */ 1743 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ 1744 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 1745 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 1746 xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ 1747 xf_emit(ctx, 1, 0); /* 0000ffff */ 1748 xf_emit(ctx, 1, 0); /* 00000001 UNK0FB0 */ 1749 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */ 1750 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 1751 xf_emit(ctx, 1, 0); /* ffffffff */ 1752 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 1753 xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */ 1754 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ 1755 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ 1756 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ 1757 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 1758 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ 1759 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 1760 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 1761 xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ 1762 xf_emit(ctx, 1, 0); /* 00000007 */ 1763 if (device->chipset != 0x50) 1764 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1108 */ 1765 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 1766 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 1767 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 1768 xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */ 1769 /* SEEK */ 1770 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ 1771 xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ 1772 xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ 1773 xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ 1774 xf_emit(ctx, 1, 0x10); /* 7f/ff/3ff VIEW_VOLUME_CLIP_CTRL */ 1775 xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */ 1776 xf_emit(ctx, 1, 3); /* 00000003 FP_CTRL_UNK196C */ 1777 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1968 */ 1778 if (device->chipset != 0x50) 1779 xf_emit(ctx, 1, 0); /* 0fffffff tesla UNK1104 */ 1780 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK151C */ 1781 } 1782 1783 static void 1784 nv50_gr_construct_gene_clipid(struct nvkm_grctx *ctx) 1785 { 1786 /* middle of strand 0 on pre-NVA0 [after 24xx], middle of area 6 on NVAx */ 1787 /* SEEK */ 1788 xf_emit(ctx, 1, 0); /* 00000007 UNK0FB4 */ 1789 /* SEEK */ 1790 xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_HORIZ */ 1791 xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_VERT */ 1792 xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ 1793 xf_emit(ctx, 2, 0x04000000); /* 07ffffff UNK1508 */ 1794 xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */ 1795 xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_WIDTH */ 1796 xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ID */ 1797 xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ADDRESS_HIGH */ 1798 xf_emit(ctx, 1, 0); /* ffffffff CLIPID_ADDRESS_LOW */ 1799 xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_HEIGHT */ 1800 xf_emit(ctx, 1, 0); /* 0000ffff DMA_CLIPID */ 1801 } 1802 1803 static void 1804 nv50_gr_construct_gene_unk24xx(struct nvkm_grctx *ctx) 1805 { 1806 struct nvkm_device *device = ctx->device; 1807 int i; 1808 /* middle of strand 0 on pre-NVA0 [after m2mf], end of strand 2 on NVAx */ 1809 /* SEEK */ 1810 xf_emit(ctx, 0x33, 0); 1811 /* SEEK */ 1812 xf_emit(ctx, 2, 0); 1813 /* SEEK */ 1814 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1815 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1816 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1817 /* SEEK */ 1818 if (IS_NVA3F(device->chipset)) { 1819 xf_emit(ctx, 4, 0); /* RO */ 1820 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ 1821 xf_emit(ctx, 1, 0); /* 1ff */ 1822 xf_emit(ctx, 8, 0); /* 0? */ 1823 xf_emit(ctx, 9, 0); /* ffffffff, 7ff */ 1824 1825 xf_emit(ctx, 4, 0); /* RO */ 1826 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ 1827 xf_emit(ctx, 1, 0); /* 1ff */ 1828 xf_emit(ctx, 8, 0); /* 0? */ 1829 xf_emit(ctx, 9, 0); /* ffffffff, 7ff */ 1830 } else { 1831 xf_emit(ctx, 0xc, 0); /* RO */ 1832 /* SEEK */ 1833 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ 1834 xf_emit(ctx, 1, 0); /* 1ff */ 1835 xf_emit(ctx, 8, 0); /* 0? */ 1836 1837 /* SEEK */ 1838 xf_emit(ctx, 0xc, 0); /* RO */ 1839 /* SEEK */ 1840 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ 1841 xf_emit(ctx, 1, 0); /* 1ff */ 1842 xf_emit(ctx, 8, 0); /* 0? */ 1843 } 1844 /* SEEK */ 1845 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1846 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1847 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1848 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1849 if (device->chipset != 0x50) 1850 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ 1851 /* SEEK */ 1852 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1853 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1854 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ 1855 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1856 xf_emit(ctx, 1, 1); /* 00000001 */ 1857 /* SEEK */ 1858 if (device->chipset >= 0xa0) 1859 xf_emit(ctx, 2, 4); /* 000000ff */ 1860 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1861 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ 1862 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ 1863 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1864 xf_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM_ID */ 1865 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1866 xf_emit(ctx, 1, 0); /* 0000000f */ 1867 xf_emit(ctx, 1, 1); /* 00000001 */ 1868 for (i = 0; i < 10; i++) { 1869 /* SEEK */ 1870 xf_emit(ctx, 0x40, 0); /* ffffffff */ 1871 xf_emit(ctx, 0x10, 0); /* 3, 0, 0.... */ 1872 xf_emit(ctx, 0x10, 0); /* ffffffff */ 1873 } 1874 /* SEEK */ 1875 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_CTRL */ 1876 xf_emit(ctx, 1, 1); /* 00000001 */ 1877 xf_emit(ctx, 1, 0); /* ffffffff */ 1878 xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */ 1879 xf_emit(ctx, 0x10, 0); /* 00ffffff POINT_COORD_REPLACE_MAP */ 1880 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 1881 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1882 if (device->chipset != 0x50) 1883 xf_emit(ctx, 1, 0); /* 000003ff */ 1884 } 1885 1886 static void 1887 nv50_gr_construct_gene_vfetch(struct nvkm_grctx *ctx) 1888 { 1889 struct nvkm_device *device = ctx->device; 1890 int acnt = 0x10, rep, i; 1891 /* beginning of strand 1 on pre-NVA0, strand 3 on NVAx */ 1892 if (IS_NVA3F(device->chipset)) 1893 acnt = 0x20; 1894 /* SEEK */ 1895 if (device->chipset >= 0xa0) { 1896 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK13A4 */ 1897 xf_emit(ctx, 1, 1); /* 00000fff tesla UNK1318 */ 1898 } 1899 xf_emit(ctx, 1, 0); /* ffffffff VERTEX_BUFFER_FIRST */ 1900 xf_emit(ctx, 1, 0); /* 00000001 PRIMITIVE_RESTART_ENABLE */ 1901 xf_emit(ctx, 1, 0); /* 00000001 UNK0DE8 */ 1902 xf_emit(ctx, 1, 0); /* ffffffff PRIMITIVE_RESTART_INDEX */ 1903 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ 1904 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ 1905 xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATR_MASK_UNK0DD0 */ 1906 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ 1907 xf_emit(ctx, 1, 0x20); /* 0000ffff tesla UNK129C */ 1908 xf_emit(ctx, 1, 0); /* 000000ff turing UNK370??? */ 1909 xf_emit(ctx, 1, 0); /* 0000ffff turing USER_PARAM_COUNT */ 1910 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1911 /* SEEK */ 1912 if (IS_NVA3F(device->chipset)) 1913 xf_emit(ctx, 0xb, 0); /* RO */ 1914 else if (device->chipset >= 0xa0) 1915 xf_emit(ctx, 0x9, 0); /* RO */ 1916 else 1917 xf_emit(ctx, 0x8, 0); /* RO */ 1918 /* SEEK */ 1919 xf_emit(ctx, 1, 0); /* 00000001 EDGE_FLAG */ 1920 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ 1921 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1922 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 1923 /* SEEK */ 1924 xf_emit(ctx, 0xc, 0); /* RO */ 1925 /* SEEK */ 1926 xf_emit(ctx, 1, 0); /* 7f/ff */ 1927 xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ 1928 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ 1929 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ 1930 xf_emit(ctx, 1, 4); /* 000001ff UNK1A28 */ 1931 xf_emit(ctx, 1, 8); /* 000001ff UNK0DF0 */ 1932 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1933 if (device->chipset == 0x50) 1934 xf_emit(ctx, 1, 0x3ff); /* 3ff tesla UNK0D68 */ 1935 else 1936 xf_emit(ctx, 1, 0x7ff); /* 7ff tesla UNK0D68 */ 1937 if (device->chipset == 0xa8) 1938 xf_emit(ctx, 1, 0x1e00); /* 7fff */ 1939 /* SEEK */ 1940 xf_emit(ctx, 0xc, 0); /* RO or close */ 1941 /* SEEK */ 1942 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ 1943 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ 1944 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ 1945 if (device->chipset > 0x50 && device->chipset < 0xa0) 1946 xf_emit(ctx, 2, 0); /* ffffffff */ 1947 else 1948 xf_emit(ctx, 1, 0); /* ffffffff */ 1949 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0FD8 */ 1950 /* SEEK */ 1951 if (IS_NVA3F(device->chipset)) { 1952 xf_emit(ctx, 0x10, 0); /* 0? */ 1953 xf_emit(ctx, 2, 0); /* weird... */ 1954 xf_emit(ctx, 2, 0); /* RO */ 1955 } else { 1956 xf_emit(ctx, 8, 0); /* 0? */ 1957 xf_emit(ctx, 1, 0); /* weird... */ 1958 xf_emit(ctx, 2, 0); /* RO */ 1959 } 1960 /* SEEK */ 1961 xf_emit(ctx, 1, 0); /* ffffffff VB_ELEMENT_BASE */ 1962 xf_emit(ctx, 1, 0); /* ffffffff UNK1438 */ 1963 xf_emit(ctx, acnt, 0); /* 1 tesla UNK1000 */ 1964 if (device->chipset >= 0xa0) 1965 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1118? */ 1966 /* SEEK */ 1967 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */ 1968 xf_emit(ctx, 1, 0); /* f/1f */ 1969 /* SEEK */ 1970 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */ 1971 xf_emit(ctx, 1, 0); /* f/1f */ 1972 /* SEEK */ 1973 xf_emit(ctx, acnt, 0); /* RO */ 1974 xf_emit(ctx, 2, 0); /* RO */ 1975 /* SEEK */ 1976 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK111C? */ 1977 xf_emit(ctx, 1, 0); /* RO */ 1978 /* SEEK */ 1979 xf_emit(ctx, 1, 0); /* 000000ff UNK15F4_ADDRESS_HIGH */ 1980 xf_emit(ctx, 1, 0); /* ffffffff UNK15F4_ADDRESS_LOW */ 1981 xf_emit(ctx, 1, 0); /* 000000ff UNK0F84_ADDRESS_HIGH */ 1982 xf_emit(ctx, 1, 0); /* ffffffff UNK0F84_ADDRESS_LOW */ 1983 /* SEEK */ 1984 xf_emit(ctx, acnt, 0); /* 00003fff VERTEX_ARRAY_ATTRIB_OFFSET */ 1985 xf_emit(ctx, 3, 0); /* f/1f */ 1986 /* SEEK */ 1987 xf_emit(ctx, acnt, 0); /* 00000fff VERTEX_ARRAY_STRIDE */ 1988 xf_emit(ctx, 3, 0); /* f/1f */ 1989 /* SEEK */ 1990 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_LOW */ 1991 xf_emit(ctx, 3, 0); /* f/1f */ 1992 /* SEEK */ 1993 xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_ARRAY_HIGH */ 1994 xf_emit(ctx, 3, 0); /* f/1f */ 1995 /* SEEK */ 1996 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_LIMIT_LOW */ 1997 xf_emit(ctx, 3, 0); /* f/1f */ 1998 /* SEEK */ 1999 xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_LIMIT_HIGH */ 2000 xf_emit(ctx, 3, 0); /* f/1f */ 2001 /* SEEK */ 2002 if (IS_NVA3F(device->chipset)) { 2003 xf_emit(ctx, acnt, 0); /* f */ 2004 xf_emit(ctx, 3, 0); /* f/1f */ 2005 } 2006 /* SEEK */ 2007 if (IS_NVA3F(device->chipset)) 2008 xf_emit(ctx, 2, 0); /* RO */ 2009 else 2010 xf_emit(ctx, 5, 0); /* RO */ 2011 /* SEEK */ 2012 xf_emit(ctx, 1, 0); /* ffff DMA_VTXBUF */ 2013 /* SEEK */ 2014 if (device->chipset < 0xa0) { 2015 xf_emit(ctx, 0x41, 0); /* RO */ 2016 /* SEEK */ 2017 xf_emit(ctx, 0x11, 0); /* RO */ 2018 } else if (!IS_NVA3F(device->chipset)) 2019 xf_emit(ctx, 0x50, 0); /* RO */ 2020 else 2021 xf_emit(ctx, 0x58, 0); /* RO */ 2022 /* SEEK */ 2023 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ 2024 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ 2025 xf_emit(ctx, 1, 1); /* 1 UNK0DEC */ 2026 /* SEEK */ 2027 xf_emit(ctx, acnt*4, 0); /* ffffffff VTX_ATTR */ 2028 xf_emit(ctx, 4, 0); /* f/1f, 0, 0, 0 */ 2029 /* SEEK */ 2030 if (IS_NVA3F(device->chipset)) 2031 xf_emit(ctx, 0x1d, 0); /* RO */ 2032 else 2033 xf_emit(ctx, 0x16, 0); /* RO */ 2034 /* SEEK */ 2035 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ 2036 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ 2037 /* SEEK */ 2038 if (device->chipset < 0xa0) 2039 xf_emit(ctx, 8, 0); /* RO */ 2040 else if (IS_NVA3F(device->chipset)) 2041 xf_emit(ctx, 0xc, 0); /* RO */ 2042 else 2043 xf_emit(ctx, 7, 0); /* RO */ 2044 /* SEEK */ 2045 xf_emit(ctx, 0xa, 0); /* RO */ 2046 if (device->chipset == 0xa0) 2047 rep = 0xc; 2048 else 2049 rep = 4; 2050 for (i = 0; i < rep; i++) { 2051 /* SEEK */ 2052 if (IS_NVA3F(device->chipset)) 2053 xf_emit(ctx, 0x20, 0); /* ffffffff */ 2054 xf_emit(ctx, 0x200, 0); /* ffffffff */ 2055 xf_emit(ctx, 4, 0); /* 7f/ff, 0, 0, 0 */ 2056 xf_emit(ctx, 4, 0); /* ffffffff */ 2057 } 2058 /* SEEK */ 2059 xf_emit(ctx, 1, 0); /* 113/111 */ 2060 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ 2061 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ 2062 xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATTR_MASK_UNK0DD0 */ 2063 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ 2064 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2065 /* SEEK */ 2066 if (IS_NVA3F(device->chipset)) 2067 xf_emit(ctx, 7, 0); /* weird... */ 2068 else 2069 xf_emit(ctx, 5, 0); /* weird... */ 2070 } 2071 2072 static void 2073 nv50_gr_construct_gene_eng2d(struct nvkm_grctx *ctx) 2074 { 2075 struct nvkm_device *device = ctx->device; 2076 /* middle of strand 1 on pre-NVA0 [after vfetch], middle of strand 6 on NVAx */ 2077 /* SEEK */ 2078 xf_emit(ctx, 2, 0); /* 0001ffff CLIP_X, CLIP_Y */ 2079 xf_emit(ctx, 2, 0); /* 0000ffff CLIP_W, CLIP_H */ 2080 xf_emit(ctx, 1, 0); /* 00000001 CLIP_ENABLE */ 2081 if (device->chipset < 0xa0) { 2082 /* this is useless on everything but the original NV50, 2083 * guess they forgot to nuke it. Or just didn't bother. */ 2084 xf_emit(ctx, 2, 0); /* 0000ffff IFC_CLIP_X, Y */ 2085 xf_emit(ctx, 2, 1); /* 0000ffff IFC_CLIP_W, H */ 2086 xf_emit(ctx, 1, 0); /* 00000001 IFC_CLIP_ENABLE */ 2087 } 2088 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2089 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */ 2090 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */ 2091 xf_emit(ctx, 1, 0x11); /* 3f[NV50]/7f[NV84+] DST_FORMAT */ 2092 xf_emit(ctx, 1, 0); /* 0001ffff DRAW_POINT_X */ 2093 xf_emit(ctx, 1, 8); /* 0000000f DRAW_UNK58C */ 2094 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_X_FRACT */ 2095 xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_X_INT */ 2096 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_Y_FRACT */ 2097 xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_Y_INT */ 2098 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DX_DU_FRACT */ 2099 xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DX_DU_INT */ 2100 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DY_DV_FRACT */ 2101 xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DY_DV_INT */ 2102 xf_emit(ctx, 1, 1); /* 0000ffff SIFC_WIDTH */ 2103 xf_emit(ctx, 1, 1); /* 0000ffff SIFC_HEIGHT */ 2104 xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */ 2105 xf_emit(ctx, 1, 2); /* 00000003 SIFC_BITMAP_UNK808 */ 2106 xf_emit(ctx, 1, 0); /* 00000003 SIFC_BITMAP_LINE_PACK_MODE */ 2107 xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_LSB_FIRST */ 2108 xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_ENABLE */ 2109 xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_X */ 2110 xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_Y */ 2111 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */ 2112 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */ 2113 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */ 2114 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */ 2115 xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_W */ 2116 xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_H */ 2117 xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_X_FRACT */ 2118 xf_emit(ctx, 1, 0); /* 0001ffff BLIT_SRC_X_INT */ 2119 xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_Y_FRACT */ 2120 xf_emit(ctx, 1, 0); /* 00000001 UNK888 */ 2121 xf_emit(ctx, 1, 4); /* 0000003f UNK884 */ 2122 xf_emit(ctx, 1, 0); /* 00000007 UNK880 */ 2123 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK0FB8 */ 2124 xf_emit(ctx, 1, 0x15); /* 000000ff tesla UNK128C */ 2125 xf_emit(ctx, 2, 0); /* 00000007, ffff0ff3 */ 2126 xf_emit(ctx, 1, 0); /* 00000001 UNK260 */ 2127 xf_emit(ctx, 1, 0x4444480); /* 1fffffff UNK870 */ 2128 /* SEEK */ 2129 xf_emit(ctx, 0x10, 0); 2130 /* SEEK */ 2131 xf_emit(ctx, 0x27, 0); 2132 } 2133 2134 static void 2135 nv50_gr_construct_gene_csched(struct nvkm_grctx *ctx) 2136 { 2137 struct nvkm_device *device = ctx->device; 2138 /* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */ 2139 /* SEEK */ 2140 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY... what is it doing here??? */ 2141 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ 2142 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 2143 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 2144 xf_emit(ctx, 1, 0); /* 000003ff */ 2145 /* SEEK */ 2146 xf_emit(ctx, 1, 0); /* ffffffff turing UNK364 */ 2147 xf_emit(ctx, 1, 0); /* 0000000f turing UNK36C */ 2148 xf_emit(ctx, 1, 0); /* 0000ffff USER_PARAM_COUNT */ 2149 xf_emit(ctx, 1, 0x100); /* 00ffffff turing UNK384 */ 2150 xf_emit(ctx, 1, 0); /* 0000000f turing UNK2A0 */ 2151 xf_emit(ctx, 1, 0); /* 0000ffff GRIDID */ 2152 xf_emit(ctx, 1, 0x10001); /* ffffffff GRIDDIM_XY */ 2153 xf_emit(ctx, 1, 0); /* ffffffff */ 2154 xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */ 2155 xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */ 2156 xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */ 2157 xf_emit(ctx, 1, 1); /* 00000001 LANES32 */ 2158 xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ 2159 xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ 2160 /* SEEK */ 2161 xf_emit(ctx, 0x40, 0); /* ffffffff USER_PARAM */ 2162 switch (device->chipset) { 2163 case 0x50: 2164 case 0x92: 2165 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2166 xf_emit(ctx, 0x80, 0); /* fff */ 2167 xf_emit(ctx, 2, 0); /* ff, fff */ 2168 xf_emit(ctx, 0x10*2, 0); /* ffffffff, 1f */ 2169 break; 2170 case 0x84: 2171 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2172 xf_emit(ctx, 0x60, 0); /* fff */ 2173 xf_emit(ctx, 2, 0); /* ff, fff */ 2174 xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */ 2175 break; 2176 case 0x94: 2177 case 0x96: 2178 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2179 xf_emit(ctx, 0x40, 0); /* fff */ 2180 xf_emit(ctx, 2, 0); /* ff, fff */ 2181 xf_emit(ctx, 8*2, 0); /* ffffffff, 1f */ 2182 break; 2183 case 0x86: 2184 case 0x98: 2185 xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */ 2186 xf_emit(ctx, 0x10, 0); /* fff */ 2187 xf_emit(ctx, 2, 0); /* ff, fff */ 2188 xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */ 2189 break; 2190 case 0xa0: 2191 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2192 xf_emit(ctx, 0xf0, 0); /* fff */ 2193 xf_emit(ctx, 2, 0); /* ff, fff */ 2194 xf_emit(ctx, 0x1e*2, 0); /* ffffffff, 1f */ 2195 break; 2196 case 0xa3: 2197 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2198 xf_emit(ctx, 0x60, 0); /* fff */ 2199 xf_emit(ctx, 2, 0); /* ff, fff */ 2200 xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */ 2201 break; 2202 case 0xa5: 2203 case 0xaf: 2204 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2205 xf_emit(ctx, 0x30, 0); /* fff */ 2206 xf_emit(ctx, 2, 0); /* ff, fff */ 2207 xf_emit(ctx, 6*2, 0); /* ffffffff, 1f */ 2208 break; 2209 case 0xaa: 2210 xf_emit(ctx, 0x12, 0); 2211 break; 2212 case 0xa8: 2213 case 0xac: 2214 xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */ 2215 xf_emit(ctx, 0x10, 0); /* fff */ 2216 xf_emit(ctx, 2, 0); /* ff, fff */ 2217 xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */ 2218 break; 2219 } 2220 xf_emit(ctx, 1, 0); /* 0000000f */ 2221 xf_emit(ctx, 1, 0); /* 00000000 */ 2222 xf_emit(ctx, 1, 0); /* ffffffff */ 2223 xf_emit(ctx, 1, 0); /* 0000001f */ 2224 xf_emit(ctx, 4, 0); /* ffffffff */ 2225 xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */ 2226 xf_emit(ctx, 1, 0); /* ffffffff */ 2227 xf_emit(ctx, 4, 0); /* ffffffff */ 2228 xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */ 2229 xf_emit(ctx, 1, 0); /* ffffffff */ 2230 xf_emit(ctx, 1, 0); /* 000000ff */ 2231 } 2232 2233 static void 2234 nv50_gr_construct_gene_unk1cxx(struct nvkm_grctx *ctx) 2235 { 2236 struct nvkm_device *device = ctx->device; 2237 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ 2238 xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */ 2239 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ 2240 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */ 2241 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */ 2242 xf_emit(ctx, 3, 0); /* 00000001 POLYGON_OFFSET_*_ENABLE */ 2243 xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ 2244 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 2245 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2246 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ 2247 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */ 2248 xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ 2249 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2250 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 2251 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ 2252 xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_UNITS */ 2253 xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_FACTOR */ 2254 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */ 2255 xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ 2256 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 2257 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2258 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2259 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2260 xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */ 2261 xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */ 2262 xf_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_LINEAR */ 2263 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 2264 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ 2265 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ 2266 if (IS_NVA3F(device->chipset)) 2267 xf_emit(ctx, 1, 3); /* 00000003 UNK16B4 */ 2268 else if (device->chipset >= 0xa0) 2269 xf_emit(ctx, 1, 1); /* 00000001 UNK16B4 */ 2270 xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ 2271 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */ 2272 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ 2273 xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */ 2274 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 2275 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2276 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 2277 xf_emit(ctx, 1, 5); /* 0000000f UNK1408 */ 2278 xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */ 2279 xf_emit(ctx, 1, 0); /* ffffffff POINT_SIZE */ 2280 xf_emit(ctx, 1, 0); /* 00000001 */ 2281 xf_emit(ctx, 1, 0); /* 00000007 tesla UNK0FB4 */ 2282 if (device->chipset != 0x50) { 2283 xf_emit(ctx, 1, 0); /* 3ff */ 2284 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK1110 */ 2285 } 2286 if (IS_NVA3F(device->chipset)) 2287 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */ 2288 xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ 2289 xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ 2290 xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ 2291 xf_emit(ctx, 0x20, 0); /* 07ffffff VIEWPORT_HORIZ, then VIEWPORT_VERT. (W&0x3fff)<<13 | (X&0x1fff). */ 2292 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK187C */ 2293 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 2294 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2295 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2296 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2297 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ 2298 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 2299 xf_emit(ctx, 1, 5); /* 0000000f tesla UNK1220 */ 2300 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2301 xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1A20 */ 2302 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2303 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ 2304 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ 2305 if (device->chipset != 0x50) 2306 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ 2307 if (device->chipset < 0xa0) 2308 xf_emit(ctx, 0x1c, 0); /* RO */ 2309 else if (IS_NVA3F(device->chipset)) 2310 xf_emit(ctx, 0x9, 0); 2311 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ 2312 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ 2313 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 2314 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ 2315 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 2316 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 2317 if (device->chipset != 0x50) { 2318 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ 2319 xf_emit(ctx, 1, 0); /* 3ff */ 2320 } 2321 /* XXX: the following block could belong either to unk1cxx, or 2322 * to STRMOUT. Rather hard to tell. */ 2323 if (device->chipset < 0xa0) 2324 xf_emit(ctx, 0x25, 0); 2325 else 2326 xf_emit(ctx, 0x3b, 0); 2327 } 2328 2329 static void 2330 nv50_gr_construct_gene_strmout(struct nvkm_grctx *ctx) 2331 { 2332 struct nvkm_device *device = ctx->device; 2333 xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */ 2334 xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */ 2335 xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */ 2336 if (device->chipset >= 0xa0) { 2337 xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */ 2338 xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */ 2339 } 2340 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 2341 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 2342 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2343 if (device->chipset == 0x50) 2344 xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */ 2345 else 2346 xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */ 2347 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2348 /* SEEK */ 2349 xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */ 2350 xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */ 2351 xf_emit(ctx, 4, 0); /* 000000ff STRMOUT_ADDRESS_HIGH */ 2352 xf_emit(ctx, 4, 0); /* ffffffff STRMOUT_ADDRESS_LOW */ 2353 xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */ 2354 if (device->chipset >= 0xa0) { 2355 xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */ 2356 xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */ 2357 } 2358 xf_emit(ctx, 1, 0); /* 0000ffff DMA_STRMOUT */ 2359 xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ 2360 xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ 2361 xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW QUERY_COUNTER */ 2362 xf_emit(ctx, 2, 0); /* ffffffff */ 2363 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2364 /* SEEK */ 2365 xf_emit(ctx, 0x20, 0); /* ffffffff STRMOUT_MAP */ 2366 xf_emit(ctx, 1, 0); /* 0000000f */ 2367 xf_emit(ctx, 1, 0); /* 00000000? */ 2368 xf_emit(ctx, 2, 0); /* ffffffff */ 2369 } 2370 2371 static void 2372 nv50_gr_construct_gene_ropm1(struct nvkm_grctx *ctx) 2373 { 2374 struct nvkm_device *device = ctx->device; 2375 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */ 2376 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */ 2377 xf_emit(ctx, 1, 0); /* 00000007 */ 2378 xf_emit(ctx, 1, 0); /* 000003ff */ 2379 if (IS_NVA3F(device->chipset)) 2380 xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */ 2381 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2382 } 2383 2384 static void 2385 nv50_gr_construct_gene_ropm2(struct nvkm_grctx *ctx) 2386 { 2387 struct nvkm_device *device = ctx->device; 2388 /* SEEK */ 2389 xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ 2390 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2391 xf_emit(ctx, 2, 0); /* ffffffff */ 2392 xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ 2393 xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */ 2394 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 2395 xf_emit(ctx, 1, 0); /* 7 */ 2396 /* SEEK */ 2397 xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ 2398 xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ 2399 xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */ 2400 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */ 2401 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */ 2402 xf_emit(ctx, 1, 0); /* 00000001 eng2d UNK260 */ 2403 xf_emit(ctx, 1, 0); /* ff/3ff */ 2404 xf_emit(ctx, 1, 0); /* 00000007 */ 2405 if (IS_NVA3F(device->chipset)) 2406 xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */ 2407 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2408 } 2409 2410 static void 2411 nv50_gr_construct_gene_ropc(struct nvkm_grctx *ctx) 2412 { 2413 struct nvkm_device *device = ctx->device; 2414 int magic2; 2415 if (device->chipset == 0x50) { 2416 magic2 = 0x00003e60; 2417 } else if (!IS_NVA3F(device->chipset)) { 2418 magic2 = 0x001ffe67; 2419 } else { 2420 magic2 = 0x00087e67; 2421 } 2422 xf_emit(ctx, 1, 0); /* f/7 MUTISAMPLE_SAMPLES_LOG2 */ 2423 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2424 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ 2425 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ 2426 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ 2427 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ 2428 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ 2429 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2430 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ 2431 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2432 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ 2433 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2434 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2435 if (IS_NVA3F(device->chipset)) 2436 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2437 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ 2438 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ 2439 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 2440 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ 2441 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2442 if (device->chipset >= 0xa0 && !IS_NVAAF(device->chipset)) 2443 xf_emit(ctx, 1, 0x15); /* 000000ff */ 2444 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2445 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2446 xf_emit(ctx, 1, 0x10); /* 3ff/ff VIEW_VOLUME_CLIP_CTRL */ 2447 xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ 2448 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2449 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2450 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2451 if (device->chipset == 0x86 || device->chipset == 0x92 || device->chipset == 0x98 || device->chipset >= 0xa0) { 2452 xf_emit(ctx, 3, 0); /* ff, ffffffff, ffffffff */ 2453 xf_emit(ctx, 1, 4); /* 7 */ 2454 xf_emit(ctx, 1, 0x400); /* fffffff */ 2455 xf_emit(ctx, 1, 0x300); /* ffff */ 2456 xf_emit(ctx, 1, 0x1001); /* 1fff */ 2457 if (device->chipset != 0xa0) { 2458 if (IS_NVA3F(device->chipset)) 2459 xf_emit(ctx, 1, 0); /* 0000000f UNK15C8 */ 2460 else 2461 xf_emit(ctx, 1, 0x15); /* ff */ 2462 } 2463 } 2464 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2465 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2466 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ 2467 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ 2468 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2469 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ 2470 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2471 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ 2472 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2473 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2474 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ 2475 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ 2476 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2477 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2478 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2479 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ 2480 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2481 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2482 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2483 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2484 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 2485 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ 2486 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ 2487 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ 2488 xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ 2489 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2490 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ 2491 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2492 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2493 xf_emit(ctx, 1, 0); /* 0000000f */ 2494 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ 2495 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ 2496 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ 2497 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ 2498 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2499 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2500 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ 2501 xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ 2502 xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ 2503 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2504 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2505 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ 2506 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ 2507 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ 2508 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ 2509 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ 2510 xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ 2511 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2512 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ 2513 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2514 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2515 xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */ 2516 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ 2517 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ 2518 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ 2519 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 2520 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ 2521 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2522 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2523 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ 2524 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2525 xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */ 2526 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2527 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2528 xf_emit(ctx, 2, 0); /* ffff0ff3, ffff */ 2529 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ 2530 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 2531 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2532 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2533 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2534 xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ 2535 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ 2536 if (device->chipset >= 0xa0) { 2537 xf_emit(ctx, 2, 0); 2538 xf_emit(ctx, 1, 0x1001); 2539 xf_emit(ctx, 0xb, 0); 2540 } else { 2541 xf_emit(ctx, 1, 0); /* 00000007 */ 2542 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2543 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2544 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 2545 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2546 } 2547 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2548 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2549 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2550 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2551 xf_emit(ctx, 1, 0x11); /* 3f/7f */ 2552 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 2553 if (device->chipset != 0x50) { 2554 xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */ 2555 xf_emit(ctx, 1, 0); /* 000000ff */ 2556 } 2557 xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ 2558 xf_emit(ctx, 1, 0); /* ff/3ff */ 2559 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ 2560 xf_emit(ctx, 2, 1); /* 00000007 BLEND_EQUATION_RGB, ALPHA */ 2561 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ 2562 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ 2563 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ 2564 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ 2565 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ 2566 xf_emit(ctx, 1, 0); /* 00000001 */ 2567 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ 2568 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2569 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2570 if (IS_NVA3F(device->chipset)) { 2571 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK12E4 */ 2572 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ 2573 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ 2574 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ 2575 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ 2576 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ 2577 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ 2578 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ 2579 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */ 2580 xf_emit(ctx, 2, 0); /* 00000001 */ 2581 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2582 xf_emit(ctx, 1, 0); /* 0000000f */ 2583 xf_emit(ctx, 1, 0); /* 00000003 */ 2584 xf_emit(ctx, 1, 0); /* ffffffff */ 2585 xf_emit(ctx, 2, 0); /* 00000001 */ 2586 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2587 xf_emit(ctx, 1, 0); /* 00000001 */ 2588 xf_emit(ctx, 1, 0); /* 000003ff */ 2589 } else if (device->chipset >= 0xa0) { 2590 xf_emit(ctx, 2, 0); /* 00000001 */ 2591 xf_emit(ctx, 1, 0); /* 00000007 */ 2592 xf_emit(ctx, 1, 0); /* 00000003 */ 2593 xf_emit(ctx, 1, 0); /* ffffffff */ 2594 xf_emit(ctx, 2, 0); /* 00000001 */ 2595 } else { 2596 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2597 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1430 */ 2598 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2599 } 2600 xf_emit(ctx, 4, 0); /* ffffffff CLEAR_COLOR */ 2601 xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR A R G B */ 2602 xf_emit(ctx, 1, 0); /* 00000fff eng2d UNK2B0 */ 2603 if (device->chipset >= 0xa0) 2604 xf_emit(ctx, 2, 0); /* 00000001 */ 2605 xf_emit(ctx, 1, 0); /* 000003ff */ 2606 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 2607 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ 2608 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ 2609 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ 2610 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ 2611 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ 2612 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ 2613 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ 2614 xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */ 2615 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 2616 xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */ 2617 if (device->chipset >= 0xa0) 2618 xf_emit(ctx, 1, 0); /* 00000001 UNK12E4? NVA3+ only? */ 2619 if (IS_NVA3F(device->chipset)) { 2620 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ 2621 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ 2622 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ 2623 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ 2624 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ 2625 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ 2626 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ 2627 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK15C4 */ 2628 xf_emit(ctx, 1, 0); /* 00000001 */ 2629 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */ 2630 } 2631 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2632 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2633 xf_emit(ctx, 1, 0); /* 00000007 PATTERN_COLOR_FORMAT */ 2634 xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_COLOR */ 2635 xf_emit(ctx, 1, 0); /* 00000001 PATTERN_MONO_FORMAT */ 2636 xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_BITMAP */ 2637 xf_emit(ctx, 1, 0); /* 00000003 PATTERN_SELECT */ 2638 xf_emit(ctx, 1, 0); /* 000000ff ROP */ 2639 xf_emit(ctx, 1, 0); /* ffffffff BETA1 */ 2640 xf_emit(ctx, 1, 0); /* ffffffff BETA4 */ 2641 xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ 2642 xf_emit(ctx, 0x50, 0); /* 10x ffffff, ffffff, ffffff, ffffff, 3 PATTERN */ 2643 } 2644 2645 static void 2646 nv50_gr_construct_xfer_unk84xx(struct nvkm_grctx *ctx) 2647 { 2648 struct nvkm_device *device = ctx->device; 2649 int magic3; 2650 switch (device->chipset) { 2651 case 0x50: 2652 magic3 = 0x1000; 2653 break; 2654 case 0x86: 2655 case 0x98: 2656 case 0xa8: 2657 case 0xaa: 2658 case 0xac: 2659 case 0xaf: 2660 magic3 = 0x1e00; 2661 break; 2662 default: 2663 magic3 = 0; 2664 } 2665 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2666 xf_emit(ctx, 1, 4); /* 7f/ff[NVA0+] VP_REG_ALLOC_RESULT */ 2667 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2668 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2669 xf_emit(ctx, 1, 0); /* 111/113[NVA0+] */ 2670 if (IS_NVA3F(device->chipset)) 2671 xf_emit(ctx, 0x1f, 0); /* ffffffff */ 2672 else if (device->chipset >= 0xa0) 2673 xf_emit(ctx, 0x0f, 0); /* ffffffff */ 2674 else 2675 xf_emit(ctx, 0x10, 0); /* fffffff VP_RESULT_MAP_1 up */ 2676 xf_emit(ctx, 2, 0); /* f/1f[NVA3], fffffff/ffffffff[NVA0+] */ 2677 xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ 2678 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ 2679 if (device->chipset >= 0xa0) 2680 xf_emit(ctx, 1, 0x03020100); /* ffffffff */ 2681 else 2682 xf_emit(ctx, 1, 0x00608080); /* fffffff VP_RESULT_MAP_0 */ 2683 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2684 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2685 xf_emit(ctx, 2, 0); /* 111/113, 7f/ff */ 2686 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ 2687 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2688 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2689 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ 2690 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 2691 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ 2692 if (magic3) 2693 xf_emit(ctx, 1, magic3); /* 00007fff tesla UNK141C */ 2694 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ 2695 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2696 xf_emit(ctx, 1, 0); /* 111/113 */ 2697 xf_emit(ctx, 0x1f, 0); /* ffffffff GP_RESULT_MAP_1 up */ 2698 xf_emit(ctx, 1, 0); /* 0000001f */ 2699 xf_emit(ctx, 1, 0); /* ffffffff */ 2700 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2701 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ 2702 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ 2703 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 2704 xf_emit(ctx, 1, 0x03020100); /* ffffffff GP_RESULT_MAP_0 */ 2705 xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ 2706 if (magic3) 2707 xf_emit(ctx, 1, magic3); /* 7fff tesla UNK141C */ 2708 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ 2709 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ 2710 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2711 xf_emit(ctx, 1, 0); /* 111/113 */ 2712 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2713 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 2714 xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ 2715 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ 2716 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2717 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK13A0 */ 2718 xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ 2719 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2720 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2721 xf_emit(ctx, 1, 0); /* 111/113 */ 2722 if (device->chipset == 0x94 || device->chipset == 0x96) 2723 xf_emit(ctx, 0x1020, 0); /* 4 x (0x400 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */ 2724 else if (device->chipset < 0xa0) 2725 xf_emit(ctx, 0xa20, 0); /* 4 x (0x280 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */ 2726 else if (!IS_NVA3F(device->chipset)) 2727 xf_emit(ctx, 0x210, 0); /* ffffffff */ 2728 else 2729 xf_emit(ctx, 0x410, 0); /* ffffffff */ 2730 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2731 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 2732 xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ 2733 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ 2734 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2735 } 2736 2737 static void 2738 nv50_gr_construct_xfer_tprop(struct nvkm_grctx *ctx) 2739 { 2740 struct nvkm_device *device = ctx->device; 2741 int magic1, magic2; 2742 if (device->chipset == 0x50) { 2743 magic1 = 0x3ff; 2744 magic2 = 0x00003e60; 2745 } else if (!IS_NVA3F(device->chipset)) { 2746 magic1 = 0x7ff; 2747 magic2 = 0x001ffe67; 2748 } else { 2749 magic1 = 0x7ff; 2750 magic2 = 0x00087e67; 2751 } 2752 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ 2753 xf_emit(ctx, 1, 0); /* ffffffff ALPHA_TEST_REF */ 2754 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ 2755 if (IS_NVA3F(device->chipset)) 2756 xf_emit(ctx, 1, 1); /* 0000000f UNK16A0 */ 2757 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2758 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2759 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ 2760 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ 2761 xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR */ 2762 xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */ 2763 xf_emit(ctx, 1, 0); /* 00000001 UNK0FDC */ 2764 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2765 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2766 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2767 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2768 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 2769 xf_emit(ctx, 1, 0); /* ff[NV50]/3ff[NV84+] */ 2770 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 2771 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ 2772 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 2773 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ 2774 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2775 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2776 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ 2777 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ 2778 xf_emit(ctx, 1, 0); /* 7 */ 2779 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 2780 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2781 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2782 xf_emit(ctx, 1, 0); /* ffffffff COLOR_KEY */ 2783 xf_emit(ctx, 1, 0); /* 00000001 COLOR_KEY_ENABLE */ 2784 xf_emit(ctx, 1, 0); /* 00000007 COLOR_KEY_FORMAT */ 2785 xf_emit(ctx, 2, 0); /* ffffffff SIFC_BITMAP_COLOR */ 2786 xf_emit(ctx, 1, 1); /* 00000001 SIFC_BITMAP_WRITE_BIT0_ENABLE */ 2787 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ 2788 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ 2789 if (IS_NVA3F(device->chipset)) { 2790 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */ 2791 xf_emit(ctx, 1, 0); /* 00000003 */ 2792 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1298 */ 2793 } else if (device->chipset >= 0xa0) { 2794 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK16B4 */ 2795 xf_emit(ctx, 1, 0); /* 00000003 */ 2796 } else { 2797 xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ 2798 } 2799 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2800 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 2801 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ 2802 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ 2803 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ 2804 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ 2805 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ 2806 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ 2807 if (IS_NVA3F(device->chipset)) { 2808 xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */ 2809 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ 2810 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ 2811 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ 2812 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_RGB */ 2813 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_RGB */ 2814 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_ALPHA */ 2815 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_ALPHA */ 2816 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ 2817 } 2818 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ 2819 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2820 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2821 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2822 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2823 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 2824 xf_emit(ctx, 1, 0); /* ff/3ff */ 2825 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 2826 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ 2827 xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ 2828 xf_emit(ctx, 1, 0); /* 7 */ 2829 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2830 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2831 xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ 2832 xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */ 2833 xf_emit(ctx, 1, 0xcf); /* 000000ff DRAW_COLOR_FORMAT */ 2834 xf_emit(ctx, 1, 0xcf); /* 000000ff SRC_FORMAT */ 2835 if (IS_NVA3F(device->chipset)) 2836 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2837 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2838 xf_emit(ctx, 1, 0); /* 7/f[NVA3] MULTISAMPLE_SAMPLES_LOG2 */ 2839 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 2840 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ 2841 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ 2842 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ 2843 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ 2844 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ 2845 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ 2846 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ 2847 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2848 xf_emit(ctx, 8, 1); /* 00000001 UNK19E0 */ 2849 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2850 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2851 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2852 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2853 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2854 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ 2855 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2856 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2857 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2858 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2859 if (IS_NVA3F(device->chipset)) 2860 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2861 if (device->chipset == 0x50) 2862 xf_emit(ctx, 1, 0); /* ff */ 2863 else 2864 xf_emit(ctx, 3, 0); /* 1, 7, 3ff */ 2865 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 2866 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ 2867 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2868 xf_emit(ctx, 1, 0); /* 00000007 */ 2869 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 2870 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2871 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2872 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2873 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2874 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2875 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2876 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2877 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2878 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2879 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2880 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2881 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2882 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2883 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2884 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */ 2885 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */ 2886 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */ 2887 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */ 2888 xf_emit(ctx, 1, 0); /* ff/3ff */ 2889 xf_emit(ctx, 1, magic1); /* 3ff/7ff tesla UNK0D68 */ 2890 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2891 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2892 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2893 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2894 xf_emit(ctx, 1, 0); /* 00000007 */ 2895 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2896 if (IS_NVA3F(device->chipset)) 2897 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2898 xf_emit(ctx, 8, 0); /* 0000ffff DMA_COLOR */ 2899 xf_emit(ctx, 1, 0); /* 0000ffff DMA_GLOBAL */ 2900 xf_emit(ctx, 1, 0); /* 0000ffff DMA_LOCAL */ 2901 xf_emit(ctx, 1, 0); /* 0000ffff DMA_STACK */ 2902 xf_emit(ctx, 1, 0); /* ff/3ff */ 2903 xf_emit(ctx, 1, 0); /* 0000ffff DMA_DST */ 2904 xf_emit(ctx, 1, 0); /* 7 */ 2905 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2906 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2907 xf_emit(ctx, 8, 0); /* 000000ff RT_ADDRESS_HIGH */ 2908 xf_emit(ctx, 8, 0); /* ffffffff RT_LAYER_STRIDE */ 2909 xf_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */ 2910 xf_emit(ctx, 8, 8); /* 0000007f RT_TILE_MODE */ 2911 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2912 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2913 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2914 xf_emit(ctx, 8, 0x400); /* 0fffffff RT_HORIZ */ 2915 xf_emit(ctx, 8, 0x300); /* 0000ffff RT_VERT */ 2916 xf_emit(ctx, 1, 1); /* 00001fff RT_ARRAY_MODE */ 2917 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2918 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2919 xf_emit(ctx, 1, 0x20); /* 00000fff DST_TILE_MODE */ 2920 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2921 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */ 2922 xf_emit(ctx, 1, 0); /* 000007ff DST_LAYER */ 2923 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2924 xf_emit(ctx, 1, 0); /* ffffffff DST_ADDRESS_LOW */ 2925 xf_emit(ctx, 1, 0); /* 000000ff DST_ADDRESS_HIGH */ 2926 xf_emit(ctx, 1, 0x40); /* 0007ffff DST_PITCH */ 2927 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */ 2928 xf_emit(ctx, 1, 0); /* 0000ffff */ 2929 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK15AC */ 2930 xf_emit(ctx, 1, 0); /* ff/3ff */ 2931 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 2932 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ 2933 xf_emit(ctx, 1, 0); /* 00000007 */ 2934 if (IS_NVA3F(device->chipset)) 2935 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2936 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ 2937 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2938 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2939 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2940 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ 2941 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2942 xf_emit(ctx, 1, 0); /* 0000ffff DMA_ZETA */ 2943 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2944 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2945 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2946 xf_emit(ctx, 2, 0); /* ffff, ff/3ff */ 2947 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 2948 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2949 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 2950 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2951 xf_emit(ctx, 1, 0); /* 00000007 */ 2952 xf_emit(ctx, 1, 0); /* ffffffff ZETA_LAYER_STRIDE */ 2953 xf_emit(ctx, 1, 0); /* 000000ff ZETA_ADDRESS_HIGH */ 2954 xf_emit(ctx, 1, 0); /* ffffffff ZETA_ADDRESS_LOW */ 2955 xf_emit(ctx, 1, 4); /* 00000007 ZETA_TILE_MODE */ 2956 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2957 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2958 xf_emit(ctx, 1, 0x400); /* 0fffffff ZETA_HORIZ */ 2959 xf_emit(ctx, 1, 0x300); /* 0000ffff ZETA_VERT */ 2960 xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */ 2961 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2962 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2963 if (IS_NVA3F(device->chipset)) 2964 xf_emit(ctx, 1, 0); /* 00000001 */ 2965 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2966 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2967 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2968 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2969 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2970 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2971 xf_emit(ctx, 1, 0); /* ff/3ff */ 2972 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 2973 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ 2974 xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ 2975 xf_emit(ctx, 1, 0); /* 7 */ 2976 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 2977 if (IS_NVA3F(device->chipset)) { 2978 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ 2979 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2980 } 2981 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2982 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ 2983 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2984 if (device->chipset >= 0xa0) 2985 xf_emit(ctx, 1, 0x0fac6881); /* fffffff */ 2986 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ 2987 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2988 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2989 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2990 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2991 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ 2992 xf_emit(ctx, 1, 0); /* ff/3ff */ 2993 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 2994 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2995 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2996 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ 2997 xf_emit(ctx, 1, 0); /* 00000007 */ 2998 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 2999 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 3000 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 3001 if (IS_NVA3F(device->chipset)) { 3002 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 3003 xf_emit(ctx, 1, 0); /* 0000000f tesla UNK15C8 */ 3004 } 3005 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 3006 if (device->chipset >= 0xa0) { 3007 xf_emit(ctx, 3, 0); /* 7/f, 1, ffff0ff3 */ 3008 xf_emit(ctx, 1, 0xfac6881); /* fffffff */ 3009 xf_emit(ctx, 4, 0); /* 1, 1, 1, 3ff */ 3010 xf_emit(ctx, 1, 4); /* 7 */ 3011 xf_emit(ctx, 1, 0); /* 1 */ 3012 xf_emit(ctx, 2, 1); /* 1 */ 3013 xf_emit(ctx, 2, 0); /* 7, f */ 3014 xf_emit(ctx, 1, 1); /* 1 */ 3015 xf_emit(ctx, 1, 0); /* 7/f */ 3016 if (IS_NVA3F(device->chipset)) 3017 xf_emit(ctx, 0x9, 0); /* 1 */ 3018 else 3019 xf_emit(ctx, 0x8, 0); /* 1 */ 3020 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 3021 xf_emit(ctx, 8, 1); /* 1 */ 3022 xf_emit(ctx, 1, 0x11); /* 7f */ 3023 xf_emit(ctx, 7, 0); /* 7f */ 3024 xf_emit(ctx, 1, 0xfac6881); /* fffffff */ 3025 xf_emit(ctx, 1, 0xf); /* f */ 3026 xf_emit(ctx, 7, 0); /* f */ 3027 xf_emit(ctx, 1, 0x11); /* 7f */ 3028 xf_emit(ctx, 1, 1); /* 1 */ 3029 xf_emit(ctx, 5, 0); /* 1, 7, 3ff, 3, 7 */ 3030 if (IS_NVA3F(device->chipset)) { 3031 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ 3032 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 3033 } 3034 } 3035 } 3036 3037 static void 3038 nv50_gr_construct_xfer_tex(struct nvkm_grctx *ctx) 3039 { 3040 struct nvkm_device *device = ctx->device; 3041 xf_emit(ctx, 2, 0); /* 1 LINKED_TSC. yes, 2. */ 3042 if (device->chipset != 0x50) 3043 xf_emit(ctx, 1, 0); /* 3 */ 3044 xf_emit(ctx, 1, 1); /* 1ffff BLIT_DU_DX_INT */ 3045 xf_emit(ctx, 1, 0); /* fffff BLIT_DU_DX_FRACT */ 3046 xf_emit(ctx, 1, 1); /* 1ffff BLIT_DV_DY_INT */ 3047 xf_emit(ctx, 1, 0); /* fffff BLIT_DV_DY_FRACT */ 3048 if (device->chipset == 0x50) 3049 xf_emit(ctx, 1, 0); /* 3 BLIT_CONTROL */ 3050 else 3051 xf_emit(ctx, 2, 0); /* 3ff, 1 */ 3052 xf_emit(ctx, 1, 0x2a712488); /* ffffffff SRC_TIC_0 */ 3053 xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_1 */ 3054 xf_emit(ctx, 1, 0x4085c000); /* ffffffff SRC_TIC_2 */ 3055 xf_emit(ctx, 1, 0x40); /* ffffffff SRC_TIC_3 */ 3056 xf_emit(ctx, 1, 0x100); /* ffffffff SRC_TIC_4 */ 3057 xf_emit(ctx, 1, 0x10100); /* ffffffff SRC_TIC_5 */ 3058 xf_emit(ctx, 1, 0x02800000); /* ffffffff SRC_TIC_6 */ 3059 xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_7 */ 3060 if (device->chipset == 0x50) { 3061 xf_emit(ctx, 1, 0); /* 00000001 turing UNK358 */ 3062 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */ 3063 xf_emit(ctx, 1, 0); /* 00000003 turing UNK37C tesla UNK1690 */ 3064 xf_emit(ctx, 1, 0); /* 00000003 BLIT_CONTROL */ 3065 xf_emit(ctx, 1, 0); /* 00000001 turing UNK32C tesla UNK0F94 */ 3066 } else if (!IS_NVAAF(device->chipset)) { 3067 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */ 3068 xf_emit(ctx, 1, 0); /* 00000003 */ 3069 xf_emit(ctx, 1, 0); /* 000003ff */ 3070 xf_emit(ctx, 1, 0); /* 00000003 */ 3071 xf_emit(ctx, 1, 0); /* 000003ff */ 3072 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1664 / turing UNK03E8 */ 3073 xf_emit(ctx, 1, 0); /* 00000003 */ 3074 xf_emit(ctx, 1, 0); /* 000003ff */ 3075 } else { 3076 xf_emit(ctx, 0x6, 0); 3077 } 3078 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */ 3079 xf_emit(ctx, 1, 0); /* 0000ffff DMA_TEXTURE */ 3080 xf_emit(ctx, 1, 0); /* 0000ffff DMA_SRC */ 3081 } 3082 3083 static void 3084 nv50_gr_construct_xfer_unk8cxx(struct nvkm_grctx *ctx) 3085 { 3086 struct nvkm_device *device = ctx->device; 3087 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ 3088 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 3089 xf_emit(ctx, 2, 0); /* 7, ffff0ff3 */ 3090 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 3091 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */ 3092 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */ 3093 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */ 3094 xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */ 3095 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 3096 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ 3097 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK0F98 */ 3098 if (IS_NVA3F(device->chipset)) 3099 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 3100 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */ 3101 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 3102 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ 3103 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */ 3104 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ 3105 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 3106 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */ 3107 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ 3108 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 3109 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 3110 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */ 3111 xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */ 3112 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ 3113 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */ 3114 xf_emit(ctx, 1, 0x30201000); /* ffffffff tesla UNK1670 */ 3115 xf_emit(ctx, 1, 0x70605040); /* ffffffff tesla UNK1670 */ 3116 xf_emit(ctx, 1, 0xb8a89888); /* ffffffff tesla UNK1670 */ 3117 xf_emit(ctx, 1, 0xf8e8d8c8); /* ffffffff tesla UNK1670 */ 3118 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ 3119 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 3120 } 3121 3122 static void 3123 nv50_gr_construct_xfer_tp(struct nvkm_grctx *ctx) 3124 { 3125 struct nvkm_device *device = ctx->device; 3126 if (device->chipset < 0xa0) { 3127 nv50_gr_construct_xfer_unk84xx(ctx); 3128 nv50_gr_construct_xfer_tprop(ctx); 3129 nv50_gr_construct_xfer_tex(ctx); 3130 nv50_gr_construct_xfer_unk8cxx(ctx); 3131 } else { 3132 nv50_gr_construct_xfer_tex(ctx); 3133 nv50_gr_construct_xfer_tprop(ctx); 3134 nv50_gr_construct_xfer_unk8cxx(ctx); 3135 nv50_gr_construct_xfer_unk84xx(ctx); 3136 } 3137 } 3138 3139 static void 3140 nv50_gr_construct_xfer_mpc(struct nvkm_grctx *ctx) 3141 { 3142 struct nvkm_device *device = ctx->device; 3143 int i, mpcnt = 2; 3144 switch (device->chipset) { 3145 case 0x98: 3146 case 0xaa: 3147 mpcnt = 1; 3148 break; 3149 case 0x50: 3150 case 0x84: 3151 case 0x86: 3152 case 0x92: 3153 case 0x94: 3154 case 0x96: 3155 case 0xa8: 3156 case 0xac: 3157 mpcnt = 2; 3158 break; 3159 case 0xa0: 3160 case 0xa3: 3161 case 0xa5: 3162 case 0xaf: 3163 mpcnt = 3; 3164 break; 3165 } 3166 for (i = 0; i < mpcnt; i++) { 3167 xf_emit(ctx, 1, 0); /* ff */ 3168 xf_emit(ctx, 1, 0x80); /* ffffffff tesla UNK1404 */ 3169 xf_emit(ctx, 1, 0x80007004); /* ffffffff tesla UNK12B0 */ 3170 xf_emit(ctx, 1, 0x04000400); /* ffffffff */ 3171 if (device->chipset >= 0xa0) 3172 xf_emit(ctx, 1, 0xc0); /* 00007fff tesla UNK152C */ 3173 xf_emit(ctx, 1, 0x1000); /* 0000ffff tesla UNK0D60 */ 3174 xf_emit(ctx, 1, 0); /* ff/3ff */ 3175 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 3176 if (device->chipset == 0x86 || device->chipset == 0x98 || device->chipset == 0xa8 || IS_NVAAF(device->chipset)) { 3177 xf_emit(ctx, 1, 0xe00); /* 7fff */ 3178 xf_emit(ctx, 1, 0x1e00); /* 7fff */ 3179 } 3180 xf_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP */ 3181 xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */ 3182 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 3183 if (device->chipset == 0x50) 3184 xf_emit(ctx, 2, 0x1000); /* 7fff tesla UNK141C */ 3185 xf_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP */ 3186 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 3187 xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ 3188 xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ 3189 if (IS_NVAAF(device->chipset)) 3190 xf_emit(ctx, 0xb, 0); /* RO */ 3191 else if (device->chipset >= 0xa0) 3192 xf_emit(ctx, 0xc, 0); /* RO */ 3193 else 3194 xf_emit(ctx, 0xa, 0); /* RO */ 3195 } 3196 xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 3197 xf_emit(ctx, 1, 0); /* ff/3ff */ 3198 if (device->chipset >= 0xa0) { 3199 xf_emit(ctx, 1, 0x1fe21); /* 0003ffff tesla UNK0FAC */ 3200 } 3201 xf_emit(ctx, 3, 0); /* 7fff, 0, 0 */ 3202 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 3203 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 3204 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ 3205 xf_emit(ctx, 1, 1); /* 00000001 LANES32 */ 3206 xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */ 3207 xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */ 3208 xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */ 3209 xf_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */ 3210 xf_emit(ctx, 1, 0x1fe21); /* 1ffff/3ffff[NVA0+] tesla UNk0FAC */ 3211 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */ 3212 if (IS_NVA3F(device->chipset)) 3213 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 3214 xf_emit(ctx, 1, 0); /* ff/3ff */ 3215 xf_emit(ctx, 1, 0); /* 1 LINKED_TSC */ 3216 xf_emit(ctx, 1, 0); /* ff FP_ADDRESS_HIGH */ 3217 xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */ 3218 xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 3219 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 3220 xf_emit(ctx, 1, 0); /* 000000ff FRAG_COLOR_CLAMP_EN */ 3221 xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ 3222 xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */ 3223 xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */ 3224 xf_emit(ctx, 1, 0); /* 00000007 */ 3225 xf_emit(ctx, 1, 0xfac6881); /* 0fffffff RT_CONTROL */ 3226 xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ 3227 if (IS_NVA3F(device->chipset)) 3228 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */ 3229 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ 3230 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ 3231 xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ 3232 xf_emit(ctx, 1, 4); /* ffffffff tesla UNK1400 */ 3233 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 3234 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 3235 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ 3236 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ 3237 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ 3238 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ 3239 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ 3240 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ 3241 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ 3242 if (IS_NVA3F(device->chipset)) { 3243 xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */ 3244 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ 3245 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ 3246 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ 3247 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ 3248 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ 3249 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ 3250 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ 3251 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */ 3252 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ 3253 } 3254 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */ 3255 xf_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */ 3256 /* XXX: demagic this part some day */ 3257 if (device->chipset == 0x50) 3258 xf_emit(ctx, 0x3a0, 0); 3259 else if (device->chipset < 0x94) 3260 xf_emit(ctx, 0x3a2, 0); 3261 else if (device->chipset == 0x98 || device->chipset == 0xaa) 3262 xf_emit(ctx, 0x39f, 0); 3263 else 3264 xf_emit(ctx, 0x3a3, 0); 3265 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 3266 xf_emit(ctx, 1, 0); /* 7 OPERATION */ 3267 xf_emit(ctx, 1, 1); /* 1 DST_LINEAR */ 3268 xf_emit(ctx, 0x2d, 0); 3269 } 3270 3271 static void 3272 nv50_gr_construct_xfer2(struct nvkm_grctx *ctx) 3273 { 3274 struct nvkm_device *device = ctx->device; 3275 int i; 3276 u32 offset; 3277 u32 units = nvkm_rd32(device, 0x1540); 3278 int size = 0; 3279 3280 offset = (ctx->ctxvals_pos+0x3f)&~0x3f; 3281 3282 if (device->chipset < 0xa0) { 3283 for (i = 0; i < 8; i++) { 3284 ctx->ctxvals_pos = offset + i; 3285 /* that little bugger belongs to csched. No idea 3286 * what it's doing here. */ 3287 if (i == 0) 3288 xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */ 3289 if (units & (1 << i)) 3290 nv50_gr_construct_xfer_mpc(ctx); 3291 if ((ctx->ctxvals_pos-offset)/8 > size) 3292 size = (ctx->ctxvals_pos-offset)/8; 3293 } 3294 } else { 3295 /* Strand 0: TPs 0, 1 */ 3296 ctx->ctxvals_pos = offset; 3297 /* that little bugger belongs to csched. No idea 3298 * what it's doing here. */ 3299 xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */ 3300 if (units & (1 << 0)) 3301 nv50_gr_construct_xfer_mpc(ctx); 3302 if (units & (1 << 1)) 3303 nv50_gr_construct_xfer_mpc(ctx); 3304 if ((ctx->ctxvals_pos-offset)/8 > size) 3305 size = (ctx->ctxvals_pos-offset)/8; 3306 3307 /* Strand 1: TPs 2, 3 */ 3308 ctx->ctxvals_pos = offset + 1; 3309 if (units & (1 << 2)) 3310 nv50_gr_construct_xfer_mpc(ctx); 3311 if (units & (1 << 3)) 3312 nv50_gr_construct_xfer_mpc(ctx); 3313 if ((ctx->ctxvals_pos-offset)/8 > size) 3314 size = (ctx->ctxvals_pos-offset)/8; 3315 3316 /* Strand 2: TPs 4, 5, 6 */ 3317 ctx->ctxvals_pos = offset + 2; 3318 if (units & (1 << 4)) 3319 nv50_gr_construct_xfer_mpc(ctx); 3320 if (units & (1 << 5)) 3321 nv50_gr_construct_xfer_mpc(ctx); 3322 if (units & (1 << 6)) 3323 nv50_gr_construct_xfer_mpc(ctx); 3324 if ((ctx->ctxvals_pos-offset)/8 > size) 3325 size = (ctx->ctxvals_pos-offset)/8; 3326 3327 /* Strand 3: TPs 7, 8, 9 */ 3328 ctx->ctxvals_pos = offset + 3; 3329 if (units & (1 << 7)) 3330 nv50_gr_construct_xfer_mpc(ctx); 3331 if (units & (1 << 8)) 3332 nv50_gr_construct_xfer_mpc(ctx); 3333 if (units & (1 << 9)) 3334 nv50_gr_construct_xfer_mpc(ctx); 3335 if ((ctx->ctxvals_pos-offset)/8 > size) 3336 size = (ctx->ctxvals_pos-offset)/8; 3337 } 3338 ctx->ctxvals_pos = offset + size * 8; 3339 ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f; 3340 cp_lsr (ctx, offset); 3341 cp_out (ctx, CP_SET_XFER_POINTER); 3342 cp_lsr (ctx, size); 3343 cp_out (ctx, CP_SEEK_2); 3344 cp_out (ctx, CP_XFER_2); 3345 cp_wait(ctx, XFER, BUSY); 3346 } 3347