1 /*
2  * Copyright 2018 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 #include "ctxgf100.h"
23 
24 /*******************************************************************************
25  * PGRAPH context implementation
26  ******************************************************************************/
27 
28 static const struct gf100_gr_init
29 gv100_grctx_init_sw_veid_bundle_init_0[] = {
30 	{ 0x00001000, 64, 0x00100000, 0x00000008 },
31 	{ 0x00000941, 64, 0x00100000, 0x00000000 },
32 	{ 0x0000097e, 64, 0x00100000, 0x00000000 },
33 	{ 0x0000097f, 64, 0x00100000, 0x00000100 },
34 	{ 0x0000035c, 64, 0x00100000, 0x00000000 },
35 	{ 0x0000035d, 64, 0x00100000, 0x00000000 },
36 	{ 0x00000a08, 64, 0x00100000, 0x00000000 },
37 	{ 0x00000a09, 64, 0x00100000, 0x00000000 },
38 	{ 0x00000a0a, 64, 0x00100000, 0x00000000 },
39 	{ 0x00000352, 64, 0x00100000, 0x00000000 },
40 	{ 0x00000353, 64, 0x00100000, 0x00000000 },
41 	{ 0x00000358, 64, 0x00100000, 0x00000000 },
42 	{ 0x00000359, 64, 0x00100000, 0x00000000 },
43 	{ 0x00000370, 64, 0x00100000, 0x00000000 },
44 	{ 0x00000371, 64, 0x00100000, 0x00000000 },
45 	{ 0x00000372, 64, 0x00100000, 0x000fffff },
46 	{ 0x00000366, 64, 0x00100000, 0x00000000 },
47 	{ 0x00000367, 64, 0x00100000, 0x00000000 },
48 	{ 0x00000368, 64, 0x00100000, 0x00000fff },
49 	{ 0x00000623, 64, 0x00100000, 0x00000000 },
50 	{ 0x00000624, 64, 0x00100000, 0x00000000 },
51 	{ 0x0001e100,  1, 0x00000001, 0x02000001 },
52 	{}
53 };
54 
55 static const struct gf100_gr_pack
56 gv100_grctx_pack_sw_veid_bundle_init[] = {
57 	{ gv100_grctx_init_sw_veid_bundle_init_0 },
58 	{}
59 };
60 
61 void
62 gv100_grctx_generate_attrib(struct gf100_gr_chan *chan)
63 {
64 	struct gf100_gr *gr = chan->gr;
65 	const struct gf100_grctx_func *grctx = gr->func->grctx;
66 	const u32  alpha = grctx->alpha_nr;
67 	const u32 attrib = grctx->attrib_nr;
68 	const u32   gfxp = grctx->gfxp_nr;
69 	const int max_batches = 0xffff;
70 	u32 size = grctx->alpha_nr_max * gr->tpc_total;
71 	u32 ao = 0;
72 	u32 bo = ao + size;
73 	int gpc, ppc, n = 0;
74 
75 	gf100_grctx_patch_wr32(chan, 0x405830, attrib);
76 	gf100_grctx_patch_wr32(chan, 0x40585c, alpha);
77 	gf100_grctx_patch_wr32(chan, 0x4064c4, ((alpha / 4) << 16) | max_batches);
78 
79 	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
80 		for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) {
81 			const u32 as =  alpha * gr->ppc_tpc_nr[gpc][ppc];
82 			const u32 bs = attrib * gr->ppc_tpc_max;
83 			const u32 gs =   gfxp * gr->ppc_tpc_max;
84 			const u32 u = 0x418ea0 + (n * 0x04);
85 			const u32 o = PPC_UNIT(gpc, ppc, 0);
86 
87 			if (!(gr->ppc_mask[gpc] & (1 << ppc)))
88 				continue;
89 
90 			gf100_grctx_patch_wr32(chan, o + 0xc0, gs);
91 			gf100_grctx_patch_wr32(chan, o + 0xf4, bo);
92 			gf100_grctx_patch_wr32(chan, o + 0xf0, bs);
93 			bo += gs;
94 			gf100_grctx_patch_wr32(chan, o + 0xe4, as);
95 			gf100_grctx_patch_wr32(chan, o + 0xf8, ao);
96 			ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
97 			gf100_grctx_patch_wr32(chan, u, bs);
98 		}
99 	}
100 
101 	gf100_grctx_patch_wr32(chan, 0x4181e4, 0x00000100);
102 	gf100_grctx_patch_wr32(chan, 0x41befc, 0x00000100);
103 }
104 
105 void
106 gv100_grctx_generate_attrib_cb(struct gf100_gr_chan *chan, u64 addr, u32 size)
107 {
108 	gm107_grctx_generate_attrib_cb(chan, addr, size);
109 
110 	gf100_grctx_patch_wr32(chan, 0x419e00, 0x00000000 | addr >> 12);
111 	gf100_grctx_patch_wr32(chan, 0x419e04, 0x80000000 | size >> 7);
112 }
113 
114 void
115 gv100_grctx_generate_rop_mapping(struct gf100_gr *gr)
116 {
117 	struct nvkm_device *device = gr->base.engine.subdev.device;
118 	const u32 mapregs = DIV_ROUND_UP(gr->func->gpc_nr * gr->func->tpc_nr, 6);
119 	u32 data;
120 	int i, j;
121 
122 	/* Pack tile map into register format. */
123 	nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
124 				     gr->screen_tile_row_offset);
125 	for (i = 0; i < mapregs; i++) {
126 		for (data = 0, j = 0; j < 6; j++)
127 			data |= (gr->tile[i * 6 + j] & 0x1f) << (j * 5);
128 		nvkm_wr32(device, 0x418b08 + (i * 4), data);
129 		nvkm_wr32(device, 0x41bf00 + (i * 4), data);
130 		nvkm_wr32(device, 0x40780c + (i * 4), data);
131 	}
132 
133 	/* GPC_BROADCAST.TP_BROADCAST */
134 	nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) |
135 				     gr->screen_tile_row_offset);
136 	for (i = 0, j = 1; i < 5; i++, j += 4) {
137 		u8 v19 = (1 << (j + 0)) % gr->tpc_total;
138 		u8 v20 = (1 << (j + 1)) % gr->tpc_total;
139 		u8 v21 = (1 << (j + 2)) % gr->tpc_total;
140 		u8 v22 = (1 << (j + 3)) % gr->tpc_total;
141 		nvkm_wr32(device, 0x41bfb0 + (i * 4), (v22 << 24) |
142 						      (v21 << 16) |
143 						      (v20 <<  8) |
144 						       v19);
145 	}
146 
147 	/* UNK78xx */
148 	nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
149 				     gr->screen_tile_row_offset);
150 }
151 
152 void
153 gv100_grctx_generate_r400088(struct gf100_gr *gr, bool on)
154 {
155 	struct nvkm_device *device = gr->base.engine.subdev.device;
156 	nvkm_mask(device, 0x400088, 0x00060000, on ? 0x00060000 : 0x00000000);
157 }
158 
159 static void
160 gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
161 {
162 	struct nvkm_device *device = gr->base.engine.subdev.device;
163 
164 	tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc);
165 
166 	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);
167 	nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm);
168 	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
169 }
170 
171 void
172 gv100_grctx_generate_unkn(struct gf100_gr *gr)
173 {
174 	struct nvkm_device *device = gr->base.engine.subdev.device;
175 	nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010);
176 	nvkm_mask(device, 0x41be08, 0x00000004, 0x00000004);
177 	nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000);
178 	nvkm_mask(device, 0x405800, 0x08000000, 0x08000000);
179 	nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008);
180 }
181 
182 void
183 gv100_grctx_unkn88c(struct gf100_gr *gr, bool on)
184 {
185 	struct nvkm_device *device = gr->base.engine.subdev.device;
186 	const u32 mask = 0x00000010, data = on ? mask : 0x00000000;
187 	nvkm_mask(device, 0x40988c, mask, data);
188 	nvkm_rd32(device, 0x40988c);
189 	nvkm_mask(device, 0x41a88c, mask, data);
190 	nvkm_rd32(device, 0x41a88c);
191 	nvkm_mask(device, 0x408a14, mask, data);
192 	nvkm_rd32(device, 0x408a14);
193 }
194 
195 const struct gf100_grctx_func
196 gv100_grctx = {
197 	.unkn88c = gv100_grctx_unkn88c,
198 	.main = gf100_grctx_generate_main,
199 	.unkn = gv100_grctx_generate_unkn,
200 	.sw_veid_bundle_init = gv100_grctx_pack_sw_veid_bundle_init,
201 	.bundle = gm107_grctx_generate_bundle,
202 	.bundle_size = 0x3000,
203 	.bundle_min_gpm_fifo_depth = 0x180,
204 	.bundle_token_limit = 0x1680,
205 	.pagepool = gp100_grctx_generate_pagepool,
206 	.pagepool_size = 0x20000,
207 	.attrib_cb_size = gp102_grctx_generate_attrib_cb_size,
208 	.attrib_cb = gv100_grctx_generate_attrib_cb,
209 	.attrib = gv100_grctx_generate_attrib,
210 	.attrib_nr_max = 0x6c0,
211 	.attrib_nr = 0x480,
212 	.alpha_nr_max = 0xc00,
213 	.alpha_nr = 0x800,
214 	.gfxp_nr = 0xd10,
215 	.sm_id = gv100_grctx_generate_sm_id,
216 	.rop_mapping = gv100_grctx_generate_rop_mapping,
217 	.dist_skip_table = gm200_grctx_generate_dist_skip_table,
218 	.r406500 = gm200_grctx_generate_r406500,
219 	.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
220 	.smid_config = gp100_grctx_generate_smid_config,
221 	.r400088 = gv100_grctx_generate_r400088,
222 };
223