1 /* 2 * Copyright 2016 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs <bskeggs@redhat.com> 23 */ 24 #include "ctxgf100.h" 25 26 #include <subdev/fb.h> 27 28 /******************************************************************************* 29 * PGRAPH context implementation 30 ******************************************************************************/ 31 32 static void 33 gp100_grctx_generate_pagepool(struct gf100_grctx *info) 34 { 35 const struct gf100_grctx_func *grctx = info->gr->func->grctx; 36 const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; 37 const int s = 8; 38 const int b = mmio_vram(info, grctx->pagepool_size, (1 << s), access); 39 mmio_refn(info, 0x40800c, 0x00000000, s, b); 40 mmio_wr32(info, 0x408010, 0x80000000); 41 mmio_refn(info, 0x419004, 0x00000000, s, b); 42 mmio_wr32(info, 0x419008, 0x00000000); 43 } 44 45 static void 46 gp100_grctx_generate_attrib(struct gf100_grctx *info) 47 { 48 struct gf100_gr *gr = info->gr; 49 const struct gf100_grctx_func *grctx = gr->func->grctx; 50 const u32 alpha = grctx->alpha_nr; 51 const u32 attrib = grctx->attrib_nr; 52 const u32 pertpc = 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max); 53 const u32 size = roundup(gr->tpc_total * pertpc, 0x80); 54 const u32 access = NV_MEM_ACCESS_RW; 55 const int s = 12; 56 const int b = mmio_vram(info, size, (1 << s), access); 57 const int max_batches = 0xffff; 58 u32 ao = 0; 59 u32 bo = ao + grctx->alpha_nr_max * gr->tpc_total; 60 int gpc, ppc, n = 0; 61 62 mmio_refn(info, 0x418810, 0x80000000, s, b); 63 mmio_refn(info, 0x419848, 0x10000000, s, b); 64 mmio_refn(info, 0x419c2c, 0x10000000, s, b); 65 mmio_refn(info, 0x419b00, 0x00000000, s, b); 66 mmio_wr32(info, 0x419b04, 0x80000000 | size >> 7); 67 mmio_wr32(info, 0x405830, attrib); 68 mmio_wr32(info, 0x40585c, alpha); 69 mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); 70 71 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 72 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { 73 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; 74 const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; 75 const u32 u = 0x418ea0 + (n * 0x04); 76 const u32 o = PPC_UNIT(gpc, ppc, 0); 77 if (!(gr->ppc_mask[gpc] & (1 << ppc))) 78 continue; 79 mmio_wr32(info, o + 0xc0, bs); 80 mmio_wr32(info, o + 0xf4, bo); 81 mmio_wr32(info, o + 0xf0, bs); 82 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; 83 mmio_wr32(info, o + 0xe4, as); 84 mmio_wr32(info, o + 0xf8, ao); 85 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; 86 mmio_wr32(info, u, bs); 87 } 88 } 89 90 mmio_wr32(info, 0x418eec, 0x00000000); 91 mmio_wr32(info, 0x41befc, 0x00000000); 92 } 93 94 static void 95 gp100_grctx_generate_405b60(struct gf100_gr *gr) 96 { 97 struct nvkm_device *device = gr->base.engine.subdev.device; 98 const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4); 99 u32 dist[TPC_MAX / 4] = {}; 100 u32 gpcs[GPC_MAX * 2] = {}; 101 u8 tpcnr[GPC_MAX]; 102 int tpc, gpc, i; 103 104 memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); 105 106 /* won't result in the same distribution as the binary driver where 107 * some of the gpcs have more tpcs than others, but this shall do 108 * for the moment. the code for earlier gpus has this issue too. 109 */ 110 for (gpc = -1, i = 0; i < gr->tpc_total; i++) { 111 do { 112 gpc = (gpc + 1) % gr->gpc_nr; 113 } while(!tpcnr[gpc]); 114 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; 115 116 dist[i / 4] |= ((gpc << 4) | tpc) << ((i % 4) * 8); 117 gpcs[gpc + (gr->gpc_nr * (tpc / 4))] |= i << (tpc * 8); 118 } 119 120 for (i = 0; i < dist_nr; i++) 121 nvkm_wr32(device, 0x405b60 + (i * 4), dist[i]); 122 for (i = 0; i < gr->gpc_nr * 2; i++) 123 nvkm_wr32(device, 0x405ba0 + (i * 4), gpcs[i]); 124 } 125 126 static void 127 gp100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) 128 { 129 struct nvkm_device *device = gr->base.engine.subdev.device; 130 const struct gf100_grctx_func *grctx = gr->func->grctx; 131 u32 idle_timeout, tmp; 132 int i; 133 134 gf100_gr_mmio(gr, gr->fuc_sw_ctx); 135 136 idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000); 137 138 grctx->pagepool(info); 139 grctx->bundle(info); 140 grctx->attrib(info); 141 grctx->unkn(gr); 142 143 gm200_grctx_generate_tpcid(gr); 144 gf100_grctx_generate_r406028(gr); 145 gk104_grctx_generate_r418bb8(gr); 146 147 for (i = 0; i < 8; i++) 148 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); 149 nvkm_wr32(device, 0x406500, 0x00000000); 150 151 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); 152 153 for (tmp = 0, i = 0; i < gr->gpc_nr; i++) 154 tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 5); 155 nvkm_wr32(device, 0x4041c4, tmp); 156 157 gp100_grctx_generate_405b60(gr); 158 159 gf100_gr_icmd(gr, gr->fuc_bundle); 160 nvkm_wr32(device, 0x404154, idle_timeout); 161 gf100_gr_mthd(gr, gr->fuc_method); 162 } 163 164 const struct gf100_grctx_func 165 gp100_grctx = { 166 .main = gp100_grctx_generate_main, 167 .unkn = gk104_grctx_generate_unkn, 168 .bundle = gm107_grctx_generate_bundle, 169 .bundle_size = 0x3000, 170 .bundle_min_gpm_fifo_depth = 0x180, 171 .bundle_token_limit = 0x1080, 172 .pagepool = gp100_grctx_generate_pagepool, 173 .pagepool_size = 0x20000, 174 .attrib = gp100_grctx_generate_attrib, 175 .attrib_nr_max = 0x660, 176 .attrib_nr = 0x440, 177 .alpha_nr_max = 0xc00, 178 .alpha_nr = 0x800, 179 }; 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