1 /* 2 * Copyright 2016 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs <bskeggs@redhat.com> 23 */ 24 #include "ctxgf100.h" 25 26 #include <subdev/fb.h> 27 28 /******************************************************************************* 29 * PGRAPH context implementation 30 ******************************************************************************/ 31 32 void 33 gp100_grctx_generate_pagepool(struct gf100_grctx *info) 34 { 35 const struct gf100_grctx_func *grctx = info->gr->func->grctx; 36 const int s = 8; 37 const int b = mmio_vram(info, grctx->pagepool_size, (1 << s), true); 38 mmio_refn(info, 0x40800c, 0x00000000, s, b); 39 mmio_wr32(info, 0x408010, 0x8007d800); 40 mmio_refn(info, 0x419004, 0x00000000, s, b); 41 mmio_wr32(info, 0x419008, 0x00000000); 42 } 43 44 static void 45 gp100_grctx_generate_attrib(struct gf100_grctx *info) 46 { 47 struct gf100_gr *gr = info->gr; 48 const struct gf100_grctx_func *grctx = gr->func->grctx; 49 const u32 alpha = grctx->alpha_nr; 50 const u32 attrib = grctx->attrib_nr; 51 const int s = 12; 52 const int max_batches = 0xffff; 53 u32 size = grctx->alpha_nr_max * gr->tpc_total; 54 u32 ao = 0; 55 u32 bo = ao + size; 56 int gpc, ppc, b, n = 0; 57 58 for (gpc = 0; gpc < gr->gpc_nr; gpc++) 59 size += grctx->attrib_nr_max * gr->ppc_nr[gpc] * gr->ppc_tpc_max; 60 size = ((size * 0x20) + 128) & ~127; 61 b = mmio_vram(info, size, (1 << s), false); 62 63 mmio_refn(info, 0x418810, 0x80000000, s, b); 64 mmio_refn(info, 0x419848, 0x10000000, s, b); 65 mmio_refn(info, 0x419c2c, 0x10000000, s, b); 66 mmio_refn(info, 0x419b00, 0x00000000, s, b); 67 mmio_wr32(info, 0x419b04, 0x80000000 | size >> 7); 68 mmio_wr32(info, 0x405830, attrib); 69 mmio_wr32(info, 0x40585c, alpha); 70 mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); 71 72 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 73 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { 74 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; 75 const u32 bs = attrib * gr->ppc_tpc_max; 76 const u32 u = 0x418ea0 + (n * 0x04); 77 const u32 o = PPC_UNIT(gpc, ppc, 0); 78 if (!(gr->ppc_mask[gpc] & (1 << ppc))) 79 continue; 80 mmio_wr32(info, o + 0xc0, bs); 81 mmio_wr32(info, o + 0xf4, bo); 82 mmio_wr32(info, o + 0xf0, bs); 83 bo += grctx->attrib_nr_max * gr->ppc_tpc_max; 84 mmio_wr32(info, o + 0xe4, as); 85 mmio_wr32(info, o + 0xf8, ao); 86 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; 87 mmio_wr32(info, u, bs); 88 } 89 } 90 91 mmio_wr32(info, 0x418eec, 0x00000000); 92 mmio_wr32(info, 0x41befc, 0x00000000); 93 } 94 95 void 96 gp100_grctx_generate_smid_config(struct gf100_gr *gr) 97 { 98 struct nvkm_device *device = gr->base.engine.subdev.device; 99 const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4); 100 u32 dist[TPC_MAX / 4] = {}, gpcs[16] = {}; 101 u8 sm, i; 102 103 for (sm = 0; sm < gr->sm_nr; sm++) { 104 const u8 gpc = gr->sm[sm].gpc; 105 const u8 tpc = gr->sm[sm].tpc; 106 dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8); 107 gpcs[gpc + (gr->func->gpc_nr * (tpc / 4))] |= sm << ((tpc % 4) * 8); 108 } 109 110 for (i = 0; i < dist_nr; i++) 111 nvkm_wr32(device, 0x405b60 + (i * 4), dist[i]); 112 for (i = 0; i < ARRAY_SIZE(gpcs); i++) 113 nvkm_wr32(device, 0x405ba0 + (i * 4), gpcs[i]); 114 } 115 116 const struct gf100_grctx_func 117 gp100_grctx = { 118 .main = gf100_grctx_generate_main, 119 .unkn = gk104_grctx_generate_unkn, 120 .bundle = gm107_grctx_generate_bundle, 121 .bundle_size = 0x3000, 122 .bundle_min_gpm_fifo_depth = 0x180, 123 .bundle_token_limit = 0x1080, 124 .pagepool = gp100_grctx_generate_pagepool, 125 .pagepool_size = 0x20000, 126 .attrib = gp100_grctx_generate_attrib, 127 .attrib_nr_max = 0x660, 128 .attrib_nr = 0x440, 129 .alpha_nr_max = 0xc00, 130 .alpha_nr = 0x800, 131 .sm_id = gm107_grctx_generate_sm_id, 132 .rop_mapping = gf117_grctx_generate_rop_mapping, 133 .dist_skip_table = gm200_grctx_generate_dist_skip_table, 134 .r406500 = gm200_grctx_generate_r406500, 135 .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, 136 .tpc_mask = gm200_grctx_generate_tpc_mask, 137 .smid_config = gp100_grctx_generate_smid_config, 138 .r419a3c = gm200_grctx_generate_r419a3c, 139 }; 140