1 /* 2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 #include "ctxgf100.h" 23 24 static void 25 gm20b_grctx_generate_r406028(struct gf100_gr_priv *priv) 26 { 27 u32 tpc_per_gpc = 0; 28 int i; 29 30 for (i = 0; i < priv->gpc_nr; i++) 31 tpc_per_gpc |= priv->tpc_nr[i] << (4 * i); 32 33 nv_wr32(priv, 0x406028, tpc_per_gpc); 34 nv_wr32(priv, 0x405870, tpc_per_gpc); 35 } 36 37 static void 38 gm20b_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) 39 { 40 struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; 41 int idle_timeout_save; 42 int i, tmp; 43 44 gf100_gr_mmio(priv, priv->fuc_sw_ctx); 45 46 gf100_gr_wait_idle(priv); 47 48 idle_timeout_save = nv_rd32(priv, 0x404154); 49 nv_wr32(priv, 0x404154, 0x00000000); 50 51 oclass->attrib(info); 52 53 oclass->unkn(priv); 54 55 gm204_grctx_generate_tpcid(priv); 56 gm20b_grctx_generate_r406028(priv); 57 gk104_grctx_generate_r418bb8(priv); 58 59 for (i = 0; i < 8; i++) 60 nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); 61 62 nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); 63 64 gk104_grctx_generate_rop_active_fbps(priv); 65 nv_wr32(priv, 0x408908, nv_rd32(priv, 0x410108) | 0x80000000); 66 67 for (tmp = 0, i = 0; i < priv->gpc_nr; i++) 68 tmp |= ((1 << priv->tpc_nr[i]) - 1) << (i * 4); 69 nv_wr32(priv, 0x4041c4, tmp); 70 71 gm204_grctx_generate_405b60(priv); 72 73 gf100_gr_wait_idle(priv); 74 75 nv_wr32(priv, 0x404154, idle_timeout_save); 76 gf100_gr_wait_idle(priv); 77 78 gf100_gr_mthd(priv, priv->fuc_method); 79 gf100_gr_wait_idle(priv); 80 81 gf100_gr_icmd(priv, priv->fuc_bundle); 82 oclass->pagepool(info); 83 oclass->bundle(info); 84 } 85 86 struct nvkm_oclass * 87 gm20b_grctx_oclass = &(struct gf100_grctx_oclass) { 88 .base.handle = NV_ENGCTX(GR, 0x2b), 89 .base.ofuncs = &(struct nvkm_ofuncs) { 90 .ctor = gf100_gr_context_ctor, 91 .dtor = gf100_gr_context_dtor, 92 .init = _nvkm_gr_context_init, 93 .fini = _nvkm_gr_context_fini, 94 .rd32 = _nvkm_gr_context_rd32, 95 .wr32 = _nvkm_gr_context_wr32, 96 }, 97 .main = gm20b_grctx_generate_main, 98 .unkn = gk104_grctx_generate_unkn, 99 .bundle = gm107_grctx_generate_bundle, 100 .bundle_size = 0x1800, 101 .bundle_min_gpm_fifo_depth = 0x182, 102 .bundle_token_limit = 0x1c0, 103 .pagepool = gm107_grctx_generate_pagepool, 104 .pagepool_size = 0x8000, 105 .attrib = gm107_grctx_generate_attrib, 106 .attrib_nr_max = 0x600, 107 .attrib_nr = 0x400, 108 .alpha_nr_max = 0xc00, 109 .alpha_nr = 0x800, 110 }.base;