1 /* 2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include "ctxgf100.h" 24 #include "gk20a.h" 25 26 #include <subdev/mc.h> 27 28 static void 29 gk20a_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) 30 { 31 struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; 32 int idle_timeout_save; 33 int i; 34 35 gf100_gr_mmio(priv, priv->fuc_sw_ctx); 36 37 gf100_gr_wait_idle(priv); 38 39 idle_timeout_save = nv_rd32(priv, 0x404154); 40 nv_wr32(priv, 0x404154, 0x00000000); 41 42 oclass->attrib(info); 43 44 oclass->unkn(priv); 45 46 gf100_grctx_generate_tpcid(priv); 47 gf100_grctx_generate_r406028(priv); 48 gk104_grctx_generate_r418bb8(priv); 49 gf100_grctx_generate_r406800(priv); 50 51 for (i = 0; i < 8; i++) 52 nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); 53 54 nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); 55 56 gk104_grctx_generate_rop_active_fbps(priv); 57 58 nv_mask(priv, 0x5044b0, 0x8000000, 0x8000000); 59 60 gf100_gr_wait_idle(priv); 61 62 nv_wr32(priv, 0x404154, idle_timeout_save); 63 gf100_gr_wait_idle(priv); 64 65 gf100_gr_mthd(priv, priv->fuc_method); 66 gf100_gr_wait_idle(priv); 67 68 gf100_gr_icmd(priv, priv->fuc_bundle); 69 oclass->pagepool(info); 70 oclass->bundle(info); 71 } 72 73 struct nvkm_oclass * 74 gk20a_grctx_oclass = &(struct gf100_grctx_oclass) { 75 .base.handle = NV_ENGCTX(GR, 0xea), 76 .base.ofuncs = &(struct nvkm_ofuncs) { 77 .ctor = gf100_gr_context_ctor, 78 .dtor = gf100_gr_context_dtor, 79 .init = _nvkm_gr_context_init, 80 .fini = _nvkm_gr_context_fini, 81 .rd32 = _nvkm_gr_context_rd32, 82 .wr32 = _nvkm_gr_context_wr32, 83 }, 84 .main = gk20a_grctx_generate_main, 85 .unkn = gk104_grctx_generate_unkn, 86 .bundle = gk104_grctx_generate_bundle, 87 .bundle_size = 0x1800, 88 .bundle_min_gpm_fifo_depth = 0x62, 89 .bundle_token_limit = 0x100, 90 .pagepool = gk104_grctx_generate_pagepool, 91 .pagepool_size = 0x8000, 92 .attrib = gf117_grctx_generate_attrib, 93 .attrib_nr_max = 0x240, 94 .attrib_nr = 0x240, 95 .alpha_nr_max = 0x648 + (0x648 / 2), 96 .alpha_nr = 0x648, 97 }.base; 98