1 /*
2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22 #include "ctxgf100.h"
23 #include "gf100.h"
24
25 #include <subdev/mc.h>
26
27 static void
gk20a_grctx_generate_main(struct gf100_gr_chan * chan)28 gk20a_grctx_generate_main(struct gf100_gr_chan *chan)
29 {
30 struct gf100_gr *gr = chan->gr;
31 struct nvkm_device *device = gr->base.engine.subdev.device;
32 const struct gf100_grctx_func *grctx = gr->func->grctx;
33 u32 idle_timeout;
34 int i;
35
36 gf100_gr_mmio(gr, gr->sw_ctx);
37
38 gf100_gr_wait_idle(gr);
39
40 idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000);
41
42 grctx->attrib_cb(chan, chan->attrib_cb->addr, grctx->attrib_cb_size(gr));
43 grctx->attrib(chan);
44
45 grctx->unkn(gr);
46
47 gf100_grctx_generate_floorsweep(gr);
48
49 for (i = 0; i < 8; i++)
50 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
51
52 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
53
54 nvkm_mask(device, 0x5044b0, 0x08000000, 0x08000000);
55
56 gf100_gr_wait_idle(gr);
57
58 nvkm_wr32(device, 0x404154, idle_timeout);
59 gf100_gr_wait_idle(gr);
60
61 gf100_gr_mthd(gr, gr->method);
62 gf100_gr_wait_idle(gr);
63
64 gf100_gr_icmd(gr, gr->bundle);
65 grctx->pagepool(chan, chan->pagepool->addr);
66 grctx->bundle(chan, chan->bundle_cb->addr, grctx->bundle_size);
67 }
68
69 const struct gf100_grctx_func
70 gk20a_grctx = {
71 .main = gk20a_grctx_generate_main,
72 .unkn = gk104_grctx_generate_unkn,
73 .bundle = gk104_grctx_generate_bundle,
74 .bundle_size = 0x1800,
75 .bundle_min_gpm_fifo_depth = 0x62,
76 .bundle_token_limit = 0x100,
77 .pagepool = gk104_grctx_generate_pagepool,
78 .pagepool_size = 0x8000,
79 .attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
80 .attrib_cb = gf100_grctx_generate_attrib_cb,
81 .attrib = gf117_grctx_generate_attrib,
82 .attrib_nr_max = 0x240,
83 .attrib_nr = 0x240,
84 .alpha_nr_max = 0x648 + (0x648 / 2),
85 .alpha_nr = 0x648,
86 .sm_id = gf100_grctx_generate_sm_id,
87 .tpc_nr = gf100_grctx_generate_tpc_nr,
88 .rop_mapping = gf117_grctx_generate_rop_mapping,
89 .alpha_beta_tables = gk104_grctx_generate_alpha_beta_tables,
90 };
91