1 /* 2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include "ctxgf100.h" 24 #include "gk20a.h" 25 26 #include <subdev/mc.h> 27 28 static void 29 gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) 30 { 31 struct nvkm_device *device = gr->base.engine.subdev.device; 32 const struct gf100_grctx_func *grctx = gr->func->grctx; 33 int idle_timeout_save; 34 int i; 35 36 gf100_gr_mmio(gr, gr->fuc_sw_ctx); 37 38 gf100_gr_wait_idle(gr); 39 40 idle_timeout_save = nvkm_rd32(device, 0x404154); 41 nvkm_wr32(device, 0x404154, 0x00000000); 42 43 grctx->attrib(info); 44 45 grctx->unkn(gr); 46 47 gf100_grctx_generate_tpcid(gr); 48 gf100_grctx_generate_r406028(gr); 49 gk104_grctx_generate_r418bb8(gr); 50 gf100_grctx_generate_r406800(gr); 51 52 for (i = 0; i < 8; i++) 53 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); 54 55 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); 56 57 gk104_grctx_generate_rop_active_fbps(gr); 58 59 nvkm_mask(device, 0x5044b0, 0x8000000, 0x8000000); 60 61 gf100_gr_wait_idle(gr); 62 63 nvkm_wr32(device, 0x404154, idle_timeout_save); 64 gf100_gr_wait_idle(gr); 65 66 gf100_gr_mthd(gr, gr->fuc_method); 67 gf100_gr_wait_idle(gr); 68 69 gf100_gr_icmd(gr, gr->fuc_bundle); 70 grctx->pagepool(info); 71 grctx->bundle(info); 72 } 73 74 const struct gf100_grctx_func 75 gk20a_grctx = { 76 .main = gk20a_grctx_generate_main, 77 .unkn = gk104_grctx_generate_unkn, 78 .bundle = gk104_grctx_generate_bundle, 79 .bundle_size = 0x1800, 80 .bundle_min_gpm_fifo_depth = 0x62, 81 .bundle_token_limit = 0x100, 82 .pagepool = gk104_grctx_generate_pagepool, 83 .pagepool_size = 0x8000, 84 .attrib = gf117_grctx_generate_attrib, 85 .attrib_nr_max = 0x240, 86 .attrib_nr = 0x240, 87 .alpha_nr_max = 0x648 + (0x648 / 2), 88 .alpha_nr = 0x648, 89 }; 90