1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25 #include <core/client.h> 26 #include <core/device.h> 27 #include <nvif/unpack.h> 28 #include <nvif/class.h> 29 #include <core/engctx.h> 30 #include <core/ramht.h> 31 32 #include <subdev/instmem.h> 33 #include <subdev/instmem/nv04.h> 34 #include <subdev/fb.h> 35 36 #include <engine/fifo.h> 37 38 #include "nv04.h" 39 40 static struct ramfc_desc 41 nv40_ramfc[] = { 42 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, 43 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, 44 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, 45 { 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, 46 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, 47 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_STATE }, 48 { 28, 0, 0x18, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, 49 { 2, 28, 0x18, 28, 0x002058 }, 50 { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_ENGINE }, 51 { 32, 0, 0x20, 0, NV04_PFIFO_CACHE1_PULL1 }, 52 { 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE }, 53 { 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP }, 54 { 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT }, 55 { 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_SEMAPHORE }, 56 { 32, 0, 0x34, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE }, 57 { 32, 0, 0x38, 0, NV40_PFIFO_GRCTX_INSTANCE }, 58 { 17, 0, 0x3c, 0, NV04_PFIFO_DMA_TIMESLICE }, 59 { 32, 0, 0x40, 0, 0x0032e4 }, 60 { 32, 0, 0x44, 0, 0x0032e8 }, 61 { 32, 0, 0x4c, 0, 0x002088 }, 62 { 32, 0, 0x50, 0, 0x003300 }, 63 { 32, 0, 0x54, 0, 0x00330c }, 64 {} 65 }; 66 67 /******************************************************************************* 68 * FIFO channel objects 69 ******************************************************************************/ 70 71 static int 72 nv40_fifo_object_attach(struct nouveau_object *parent, 73 struct nouveau_object *object, u32 handle) 74 { 75 struct nv04_fifo_priv *priv = (void *)parent->engine; 76 struct nv04_fifo_chan *chan = (void *)parent; 77 u32 context, chid = chan->base.chid; 78 int ret; 79 80 if (nv_iclass(object, NV_GPUOBJ_CLASS)) 81 context = nv_gpuobj(object)->addr >> 4; 82 else 83 context = 0x00000004; /* just non-zero */ 84 85 switch (nv_engidx(object->engine)) { 86 case NVDEV_ENGINE_DMAOBJ: 87 case NVDEV_ENGINE_SW: 88 context |= 0x00000000; 89 break; 90 case NVDEV_ENGINE_GR: 91 context |= 0x00100000; 92 break; 93 case NVDEV_ENGINE_MPEG: 94 context |= 0x00200000; 95 break; 96 default: 97 return -EINVAL; 98 } 99 100 context |= chid << 23; 101 102 mutex_lock(&nv_subdev(priv)->mutex); 103 ret = nouveau_ramht_insert(priv->ramht, chid, handle, context); 104 mutex_unlock(&nv_subdev(priv)->mutex); 105 return ret; 106 } 107 108 static int 109 nv40_fifo_context_attach(struct nouveau_object *parent, 110 struct nouveau_object *engctx) 111 { 112 struct nv04_fifo_priv *priv = (void *)parent->engine; 113 struct nv04_fifo_chan *chan = (void *)parent; 114 unsigned long flags; 115 u32 reg, ctx; 116 117 switch (nv_engidx(engctx->engine)) { 118 case NVDEV_ENGINE_SW: 119 return 0; 120 case NVDEV_ENGINE_GR: 121 reg = 0x32e0; 122 ctx = 0x38; 123 break; 124 case NVDEV_ENGINE_MPEG: 125 reg = 0x330c; 126 ctx = 0x54; 127 break; 128 default: 129 return -EINVAL; 130 } 131 132 spin_lock_irqsave(&priv->base.lock, flags); 133 nv_engctx(engctx)->addr = nv_gpuobj(engctx)->addr >> 4; 134 nv_mask(priv, 0x002500, 0x00000001, 0x00000000); 135 136 if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid) 137 nv_wr32(priv, reg, nv_engctx(engctx)->addr); 138 nv_wo32(priv->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr); 139 140 nv_mask(priv, 0x002500, 0x00000001, 0x00000001); 141 spin_unlock_irqrestore(&priv->base.lock, flags); 142 return 0; 143 } 144 145 static int 146 nv40_fifo_context_detach(struct nouveau_object *parent, bool suspend, 147 struct nouveau_object *engctx) 148 { 149 struct nv04_fifo_priv *priv = (void *)parent->engine; 150 struct nv04_fifo_chan *chan = (void *)parent; 151 unsigned long flags; 152 u32 reg, ctx; 153 154 switch (nv_engidx(engctx->engine)) { 155 case NVDEV_ENGINE_SW: 156 return 0; 157 case NVDEV_ENGINE_GR: 158 reg = 0x32e0; 159 ctx = 0x38; 160 break; 161 case NVDEV_ENGINE_MPEG: 162 reg = 0x330c; 163 ctx = 0x54; 164 break; 165 default: 166 return -EINVAL; 167 } 168 169 spin_lock_irqsave(&priv->base.lock, flags); 170 nv_mask(priv, 0x002500, 0x00000001, 0x00000000); 171 172 if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid) 173 nv_wr32(priv, reg, 0x00000000); 174 nv_wo32(priv->ramfc, chan->ramfc + ctx, 0x00000000); 175 176 nv_mask(priv, 0x002500, 0x00000001, 0x00000001); 177 spin_unlock_irqrestore(&priv->base.lock, flags); 178 return 0; 179 } 180 181 static int 182 nv40_fifo_chan_ctor(struct nouveau_object *parent, 183 struct nouveau_object *engine, 184 struct nouveau_oclass *oclass, void *data, u32 size, 185 struct nouveau_object **pobject) 186 { 187 union { 188 struct nv03_channel_dma_v0 v0; 189 } *args = data; 190 struct nv04_fifo_priv *priv = (void *)engine; 191 struct nv04_fifo_chan *chan; 192 int ret; 193 194 nv_ioctl(parent, "create channel dma size %d\n", size); 195 if (nvif_unpack(args->v0, 0, 0, false)) { 196 nv_ioctl(parent, "create channel dma vers %d pushbuf %08x " 197 "offset %016llx\n", args->v0.version, 198 args->v0.pushbuf, args->v0.offset); 199 } else 200 return ret; 201 202 ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, 203 0x1000, args->v0.pushbuf, 204 (1ULL << NVDEV_ENGINE_DMAOBJ) | 205 (1ULL << NVDEV_ENGINE_SW) | 206 (1ULL << NVDEV_ENGINE_GR) | 207 (1ULL << NVDEV_ENGINE_MPEG), &chan); 208 *pobject = nv_object(chan); 209 if (ret) 210 return ret; 211 212 args->v0.chid = chan->base.chid; 213 214 nv_parent(chan)->context_attach = nv40_fifo_context_attach; 215 nv_parent(chan)->context_detach = nv40_fifo_context_detach; 216 nv_parent(chan)->object_attach = nv40_fifo_object_attach; 217 nv_parent(chan)->object_detach = nv04_fifo_object_detach; 218 chan->ramfc = chan->base.chid * 128; 219 220 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); 221 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); 222 nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); 223 nv_wo32(priv->ramfc, chan->ramfc + 0x18, 0x30000000 | 224 NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | 225 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | 226 #ifdef __BIG_ENDIAN 227 NV_PFIFO_CACHE1_BIG_ENDIAN | 228 #endif 229 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); 230 nv_wo32(priv->ramfc, chan->ramfc + 0x3c, 0x0001ffff); 231 return 0; 232 } 233 234 static struct nouveau_ofuncs 235 nv40_fifo_ofuncs = { 236 .ctor = nv40_fifo_chan_ctor, 237 .dtor = nv04_fifo_chan_dtor, 238 .init = nv04_fifo_chan_init, 239 .fini = nv04_fifo_chan_fini, 240 .map = _nouveau_fifo_channel_map, 241 .rd32 = _nouveau_fifo_channel_rd32, 242 .wr32 = _nouveau_fifo_channel_wr32, 243 .ntfy = _nouveau_fifo_channel_ntfy 244 }; 245 246 static struct nouveau_oclass 247 nv40_fifo_sclass[] = { 248 { NV40_CHANNEL_DMA, &nv40_fifo_ofuncs }, 249 {} 250 }; 251 252 /******************************************************************************* 253 * FIFO context - basically just the instmem reserved for the channel 254 ******************************************************************************/ 255 256 static struct nouveau_oclass 257 nv40_fifo_cclass = { 258 .handle = NV_ENGCTX(FIFO, 0x40), 259 .ofuncs = &(struct nouveau_ofuncs) { 260 .ctor = nv04_fifo_context_ctor, 261 .dtor = _nouveau_fifo_context_dtor, 262 .init = _nouveau_fifo_context_init, 263 .fini = _nouveau_fifo_context_fini, 264 .rd32 = _nouveau_fifo_context_rd32, 265 .wr32 = _nouveau_fifo_context_wr32, 266 }, 267 }; 268 269 /******************************************************************************* 270 * PFIFO engine 271 ******************************************************************************/ 272 273 static int 274 nv40_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 275 struct nouveau_oclass *oclass, void *data, u32 size, 276 struct nouveau_object **pobject) 277 { 278 struct nv04_instmem_priv *imem = nv04_instmem(parent); 279 struct nv04_fifo_priv *priv; 280 int ret; 281 282 ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv); 283 *pobject = nv_object(priv); 284 if (ret) 285 return ret; 286 287 nouveau_ramht_ref(imem->ramht, &priv->ramht); 288 nouveau_gpuobj_ref(imem->ramro, &priv->ramro); 289 nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); 290 291 nv_subdev(priv)->unit = 0x00000100; 292 nv_subdev(priv)->intr = nv04_fifo_intr; 293 nv_engine(priv)->cclass = &nv40_fifo_cclass; 294 nv_engine(priv)->sclass = nv40_fifo_sclass; 295 priv->base.pause = nv04_fifo_pause; 296 priv->base.start = nv04_fifo_start; 297 priv->ramfc_desc = nv40_ramfc; 298 return 0; 299 } 300 301 static int 302 nv40_fifo_init(struct nouveau_object *object) 303 { 304 struct nv04_fifo_priv *priv = (void *)object; 305 struct nouveau_fb *pfb = nouveau_fb(object); 306 int ret; 307 308 ret = nouveau_fifo_init(&priv->base); 309 if (ret) 310 return ret; 311 312 nv_wr32(priv, 0x002040, 0x000000ff); 313 nv_wr32(priv, 0x002044, 0x2101ffff); 314 nv_wr32(priv, 0x002058, 0x00000001); 315 316 nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | 317 ((priv->ramht->bits - 9) << 16) | 318 (priv->ramht->gpuobj.addr >> 8)); 319 nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); 320 321 switch (nv_device(priv)->chipset) { 322 case 0x47: 323 case 0x49: 324 case 0x4b: 325 nv_wr32(priv, 0x002230, 0x00000001); 326 case 0x40: 327 case 0x41: 328 case 0x42: 329 case 0x43: 330 case 0x45: 331 case 0x48: 332 nv_wr32(priv, 0x002220, 0x00030002); 333 break; 334 default: 335 nv_wr32(priv, 0x002230, 0x00000000); 336 nv_wr32(priv, 0x002220, ((pfb->ram->size - 512 * 1024 + 337 priv->ramfc->addr) >> 16) | 338 0x00030000); 339 break; 340 } 341 342 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); 343 344 nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff); 345 nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff); 346 347 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); 348 nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); 349 nv_wr32(priv, NV03_PFIFO_CACHES, 1); 350 return 0; 351 } 352 353 struct nouveau_oclass * 354 nv40_fifo_oclass = &(struct nouveau_oclass) { 355 .handle = NV_ENGINE(FIFO, 0x40), 356 .ofuncs = &(struct nouveau_ofuncs) { 357 .ctor = nv40_fifo_ctor, 358 .dtor = nv04_fifo_dtor, 359 .init = nv40_fifo_init, 360 .fini = _nouveau_fifo_fini, 361 }, 362 }; 363