1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "chan.h" 25 #include "chid.h" 26 27 #include "nv04.h" 28 #include "channv04.h" 29 #include "regsnv04.h" 30 31 #include <core/ramht.h> 32 #include <subdev/instmem.h> 33 34 #include <nvif/class.h> 35 36 static const struct nv04_fifo_ramfc 37 nv17_fifo_ramfc[] = { 38 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, 39 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, 40 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, 41 { 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, 42 { 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, 43 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE }, 44 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, 45 { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE }, 46 { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 }, 47 { 32, 0, 0x20, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE }, 48 { 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP }, 49 { 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT }, 50 { 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_SEMAPHORE }, 51 { 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE }, 52 {} 53 }; 54 55 static const struct nvkm_chan_func 56 nv17_chan = { 57 }; 58 59 static void 60 nv17_fifo_init(struct nvkm_fifo *fifo) 61 { 62 struct nvkm_device *device = fifo->engine.subdev.device; 63 struct nvkm_instmem *imem = device->imem; 64 struct nvkm_ramht *ramht = imem->ramht; 65 struct nvkm_memory *ramro = imem->ramro; 66 struct nvkm_memory *ramfc = imem->ramfc; 67 68 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff); 69 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); 70 71 nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | 72 ((ramht->bits - 9) << 16) | 73 (ramht->gpuobj->addr >> 8)); 74 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); 75 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8 | 76 0x00010000); 77 78 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask); 79 80 nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff); 81 nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff); 82 83 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); 84 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 85 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); 86 } 87 88 static const struct nvkm_fifo_func 89 nv17_fifo = { 90 .chid_nr = nv10_fifo_chid_nr, 91 .chid_ctor = nv04_fifo_chid_ctor, 92 .runl_ctor = nv04_fifo_runl_ctor, 93 .init = nv17_fifo_init, 94 .intr = nv04_fifo_intr, 95 .engine_id = nv04_fifo_engine_id, 96 .id_engine = nv04_fifo_id_engine, 97 .pause = nv04_fifo_pause, 98 .start = nv04_fifo_start, 99 .runl = &nv04_runl, 100 .engn = &nv04_engn, 101 .engn_sw = &nv04_engn, 102 .cgrp = {{ }, &nv04_cgrp }, 103 .chan = {{ 0, 0, NV17_CHANNEL_DMA }, &nv17_chan, .oclass = &nv17_fifo_dma_oclass }, 104 }; 105 106 int 107 nv17_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 108 struct nvkm_fifo **pfifo) 109 { 110 return nv04_fifo_new_(&nv17_fifo, device, type, inst, 32, nv17_fifo_ramfc, pfifo); 111 } 112