1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv04.h" 25 26 #include <core/client.h> 27 #include <core/engctx.h> 28 #include <core/ramht.h> 29 #include <subdev/instmem.h> 30 31 #include <nvif/class.h> 32 #include <nvif/unpack.h> 33 34 static struct ramfc_desc 35 nv17_ramfc[] = { 36 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, 37 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, 38 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, 39 { 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, 40 { 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, 41 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE }, 42 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, 43 { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE }, 44 { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 }, 45 { 32, 0, 0x20, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE }, 46 { 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP }, 47 { 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT }, 48 { 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_SEMAPHORE }, 49 { 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE }, 50 {} 51 }; 52 53 /******************************************************************************* 54 * FIFO channel objects 55 ******************************************************************************/ 56 57 static int 58 nv17_fifo_chan_ctor(struct nvkm_object *parent, 59 struct nvkm_object *engine, 60 struct nvkm_oclass *oclass, void *data, u32 size, 61 struct nvkm_object **pobject) 62 { 63 union { 64 struct nv03_channel_dma_v0 v0; 65 } *args = data; 66 struct nv04_fifo *fifo = (void *)engine; 67 struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; 68 struct nv04_fifo_chan *chan; 69 int ret; 70 71 nvif_ioctl(parent, "create channel dma size %d\n", size); 72 if (nvif_unpack(args->v0, 0, 0, false)) { 73 nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " 74 "offset %08x\n", args->v0.version, 75 args->v0.pushbuf, args->v0.offset); 76 } else 77 return ret; 78 79 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, 80 0x10000, args->v0.pushbuf, 81 (1ULL << NVDEV_ENGINE_DMAOBJ) | 82 (1ULL << NVDEV_ENGINE_SW) | 83 (1ULL << NVDEV_ENGINE_GR) | 84 (1ULL << NVDEV_ENGINE_MPEG), /* NV31- */ 85 &chan); 86 *pobject = nv_object(chan); 87 if (ret) 88 return ret; 89 90 args->v0.chid = chan->base.chid; 91 92 nv_parent(chan)->object_attach = nv04_fifo_object_attach; 93 nv_parent(chan)->object_detach = nv04_fifo_object_detach; 94 nv_parent(chan)->context_attach = nv04_fifo_context_attach; 95 chan->ramfc = chan->base.chid * 64; 96 97 nvkm_kmap(imem->ramfc); 98 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); 99 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); 100 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); 101 nvkm_wo32(imem->ramfc, chan->ramfc + 0x14, 102 NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | 103 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | 104 #ifdef __BIG_ENDIAN 105 NV_PFIFO_CACHE1_BIG_ENDIAN | 106 #endif 107 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); 108 nvkm_done(imem->ramfc); 109 return 0; 110 } 111 112 static struct nvkm_ofuncs 113 nv17_fifo_ofuncs = { 114 .ctor = nv17_fifo_chan_ctor, 115 .dtor = nv04_fifo_chan_dtor, 116 .init = nv04_fifo_chan_init, 117 .fini = nv04_fifo_chan_fini, 118 .map = _nvkm_fifo_channel_map, 119 .rd32 = _nvkm_fifo_channel_rd32, 120 .wr32 = _nvkm_fifo_channel_wr32, 121 .ntfy = _nvkm_fifo_channel_ntfy 122 }; 123 124 static struct nvkm_oclass 125 nv17_fifo_sclass[] = { 126 { NV17_CHANNEL_DMA, &nv17_fifo_ofuncs }, 127 {} 128 }; 129 130 /******************************************************************************* 131 * FIFO context - basically just the instmem reserved for the channel 132 ******************************************************************************/ 133 134 static struct nvkm_oclass 135 nv17_fifo_cclass = { 136 .handle = NV_ENGCTX(FIFO, 0x17), 137 .ofuncs = &(struct nvkm_ofuncs) { 138 .ctor = nv04_fifo_context_ctor, 139 .dtor = _nvkm_fifo_context_dtor, 140 .init = _nvkm_fifo_context_init, 141 .fini = _nvkm_fifo_context_fini, 142 .rd32 = _nvkm_fifo_context_rd32, 143 .wr32 = _nvkm_fifo_context_wr32, 144 }, 145 }; 146 147 /******************************************************************************* 148 * PFIFO engine 149 ******************************************************************************/ 150 151 static int 152 nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 153 struct nvkm_oclass *oclass, void *data, u32 size, 154 struct nvkm_object **pobject) 155 { 156 struct nv04_fifo *fifo; 157 int ret; 158 159 ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo); 160 *pobject = nv_object(fifo); 161 if (ret) 162 return ret; 163 164 nv_subdev(fifo)->unit = 0x00000100; 165 nv_subdev(fifo)->intr = nv04_fifo_intr; 166 nv_engine(fifo)->cclass = &nv17_fifo_cclass; 167 nv_engine(fifo)->sclass = nv17_fifo_sclass; 168 fifo->base.pause = nv04_fifo_pause; 169 fifo->base.start = nv04_fifo_start; 170 fifo->ramfc_desc = nv17_ramfc; 171 return 0; 172 } 173 174 static int 175 nv17_fifo_init(struct nvkm_object *object) 176 { 177 struct nv04_fifo *fifo = (void *)object; 178 struct nvkm_device *device = fifo->base.engine.subdev.device; 179 struct nvkm_instmem *imem = device->imem; 180 struct nvkm_ramht *ramht = imem->ramht; 181 struct nvkm_memory *ramro = imem->ramro; 182 struct nvkm_memory *ramfc = imem->ramfc; 183 int ret; 184 185 ret = nvkm_fifo_init(&fifo->base); 186 if (ret) 187 return ret; 188 189 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff); 190 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); 191 192 nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | 193 ((ramht->bits - 9) << 16) | 194 (ramht->gpuobj->addr >> 8)); 195 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); 196 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8 | 197 0x00010000); 198 199 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max); 200 201 nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff); 202 nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff); 203 204 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); 205 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 206 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); 207 return 0; 208 } 209 210 struct nvkm_oclass * 211 nv17_fifo_oclass = &(struct nvkm_oclass) { 212 .handle = NV_ENGINE(FIFO, 0x17), 213 .ofuncs = &(struct nvkm_ofuncs) { 214 .ctor = nv17_fifo_ctor, 215 .dtor = nv04_fifo_dtor, 216 .init = nv17_fifo_init, 217 .fini = _nvkm_fifo_fini, 218 }, 219 }; 220