1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "chan.h" 25 26 #include "nv04.h" 27 #include "channv04.h" 28 #include "regsnv04.h" 29 30 #include <nvif/class.h> 31 32 static const struct nv04_fifo_ramfc 33 nv10_fifo_ramfc[] = { 34 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, 35 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, 36 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, 37 { 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, 38 { 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, 39 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE }, 40 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, 41 { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE }, 42 { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 }, 43 {} 44 }; 45 46 static const struct nvkm_chan_func 47 nv10_chan = { 48 }; 49 50 int 51 nv10_fifo_chid_nr(struct nvkm_fifo *fifo) 52 { 53 return 32; 54 } 55 56 static const struct nvkm_fifo_func 57 nv10_fifo = { 58 .chid_nr = nv10_fifo_chid_nr, 59 .chid_ctor = nv04_fifo_chid_ctor, 60 .runl_ctor = nv04_fifo_runl_ctor, 61 .init = nv04_fifo_init, 62 .intr = nv04_fifo_intr, 63 .engine_id = nv04_fifo_engine_id, 64 .pause = nv04_fifo_pause, 65 .start = nv04_fifo_start, 66 .runl = &nv04_runl, 67 .engn = &nv04_engn, 68 .engn_sw = &nv04_engn, 69 .cgrp = {{ }, &nv04_cgrp }, 70 .chan = {{ 0, 0, NV10_CHANNEL_DMA }, &nv10_chan, .oclass = &nv10_fifo_dma_oclass }, 71 }; 72 73 int 74 nv10_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 75 struct nvkm_fifo **pfifo) 76 { 77 return nv04_fifo_new_(&nv10_fifo, device, type, inst, 32, nv10_fifo_ramfc, pfifo); 78 } 79