1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv04.h" 25 #include "channv04.h" 26 #include "regsnv04.h" 27 28 #include <core/client.h> 29 #include <core/ramht.h> 30 #include <subdev/instmem.h> 31 #include <subdev/timer.h> 32 #include <engine/sw.h> 33 34 static const struct nv04_fifo_ramfc 35 nv04_fifo_ramfc[] = { 36 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, 37 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, 38 { 16, 0, 0x08, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, 39 { 16, 16, 0x08, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, 40 { 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_STATE }, 41 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, 42 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_ENGINE }, 43 { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_PULL1 }, 44 {} 45 }; 46 47 void 48 nv04_fifo_pause(struct nvkm_fifo *base, unsigned long *pflags) 49 __acquires(fifo->base.lock) 50 { 51 struct nv04_fifo *fifo = nv04_fifo(base); 52 struct nvkm_device *device = fifo->base.engine.subdev.device; 53 unsigned long flags; 54 55 spin_lock_irqsave(&fifo->base.lock, flags); 56 *pflags = flags; 57 58 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000000); 59 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000); 60 61 /* in some cases the puller may be left in an inconsistent state 62 * if you try to stop it while it's busy translating handles. 63 * sometimes you get a CACHE_ERROR, sometimes it just fails 64 * silently; sending incorrect instance offsets to PGRAPH after 65 * it's started up again. 66 * 67 * to avoid this, we invalidate the most recently calculated 68 * instance. 69 */ 70 nvkm_msec(device, 2000, 71 u32 tmp = nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0); 72 if (!(tmp & NV04_PFIFO_CACHE1_PULL0_HASH_BUSY)) 73 break; 74 ); 75 76 if (nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0) & 77 NV04_PFIFO_CACHE1_PULL0_HASH_FAILED) 78 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); 79 80 nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0x00000000); 81 } 82 83 void 84 nv04_fifo_start(struct nvkm_fifo *base, unsigned long *pflags) 85 __releases(fifo->base.lock) 86 { 87 struct nv04_fifo *fifo = nv04_fifo(base); 88 struct nvkm_device *device = fifo->base.engine.subdev.device; 89 unsigned long flags = *pflags; 90 91 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001); 92 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000001); 93 94 spin_unlock_irqrestore(&fifo->base.lock, flags); 95 } 96 97 struct nvkm_engine * 98 nv04_fifo_id_engine(struct nvkm_fifo *fifo, int engi) 99 { 100 enum nvkm_subdev_type type; 101 102 switch (engi) { 103 case NV04_FIFO_ENGN_SW : type = NVKM_ENGINE_SW; break; 104 case NV04_FIFO_ENGN_GR : type = NVKM_ENGINE_GR; break; 105 case NV04_FIFO_ENGN_MPEG: type = NVKM_ENGINE_MPEG; break; 106 case NV04_FIFO_ENGN_DMA : type = NVKM_ENGINE_DMAOBJ; break; 107 default: 108 WARN_ON(1); 109 return NULL; 110 } 111 112 return nvkm_device_engine(fifo->engine.subdev.device, type, 0); 113 } 114 115 int 116 nv04_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine) 117 { 118 switch (engine->subdev.type) { 119 case NVKM_ENGINE_SW : return NV04_FIFO_ENGN_SW; 120 case NVKM_ENGINE_GR : return NV04_FIFO_ENGN_GR; 121 case NVKM_ENGINE_MPEG : return NV04_FIFO_ENGN_MPEG; 122 case NVKM_ENGINE_DMAOBJ: return NV04_FIFO_ENGN_DMA; 123 default: 124 WARN_ON(1); 125 return 0; 126 } 127 } 128 129 static const char * 130 nv_dma_state_err(u32 state) 131 { 132 static const char * const desc[] = { 133 "NONE", "CALL_SUBR_ACTIVE", "INVALID_MTHD", "RET_SUBR_INACTIVE", 134 "INVALID_CMD", "IB_EMPTY"/* NV50+ */, "MEM_FAULT", "UNK" 135 }; 136 return desc[(state >> 29) & 0x7]; 137 } 138 139 static bool 140 nv04_fifo_swmthd(struct nvkm_device *device, u32 chid, u32 addr, u32 data) 141 { 142 struct nvkm_sw *sw = device->sw; 143 const int subc = (addr & 0x0000e000) >> 13; 144 const int mthd = (addr & 0x00001ffc); 145 const u32 mask = 0x0000000f << (subc * 4); 146 u32 engine = nvkm_rd32(device, 0x003280); 147 bool handled = false; 148 149 switch (mthd) { 150 case 0x0000 ... 0x0000: /* subchannel's engine -> software */ 151 nvkm_wr32(device, 0x003280, (engine &= ~mask)); 152 fallthrough; 153 case 0x0180 ... 0x01fc: /* handle -> instance */ 154 data = nvkm_rd32(device, 0x003258) & 0x0000ffff; 155 fallthrough; 156 case 0x0100 ... 0x017c: 157 case 0x0200 ... 0x1ffc: /* pass method down to sw */ 158 if (!(engine & mask) && sw) 159 handled = nvkm_sw_mthd(sw, chid, subc, mthd, data); 160 break; 161 default: 162 break; 163 } 164 165 return handled; 166 } 167 168 static void 169 nv04_fifo_cache_error(struct nv04_fifo *fifo, u32 chid, u32 get) 170 { 171 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 172 struct nvkm_device *device = subdev->device; 173 struct nvkm_fifo_chan *chan; 174 unsigned long flags; 175 u32 pull0 = nvkm_rd32(device, 0x003250); 176 u32 mthd, data; 177 int ptr; 178 179 /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before wrapping on my 180 * G80 chips, but CACHE1 isn't big enough for this much data.. Tests 181 * show that it wraps around to the start at GET=0x800.. No clue as to 182 * why.. 183 */ 184 ptr = (get & 0x7ff) >> 2; 185 186 if (device->card_type < NV_40) { 187 mthd = nvkm_rd32(device, NV04_PFIFO_CACHE1_METHOD(ptr)); 188 data = nvkm_rd32(device, NV04_PFIFO_CACHE1_DATA(ptr)); 189 } else { 190 mthd = nvkm_rd32(device, NV40_PFIFO_CACHE1_METHOD(ptr)); 191 data = nvkm_rd32(device, NV40_PFIFO_CACHE1_DATA(ptr)); 192 } 193 194 if (!(pull0 & 0x00000100) || 195 !nv04_fifo_swmthd(device, chid, mthd, data)) { 196 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); 197 nvkm_error(subdev, "CACHE_ERROR - " 198 "ch %d [%s] subc %d mthd %04x data %08x\n", 199 chid, chan ? chan->object.client->name : "unknown", 200 (mthd >> 13) & 7, mthd & 0x1ffc, data); 201 nvkm_fifo_chan_put(&fifo->base, flags, &chan); 202 } 203 204 nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0); 205 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); 206 207 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 208 nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) & ~1); 209 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4); 210 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 211 nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) | 1); 212 nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0); 213 214 nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 215 nvkm_rd32(device, NV04_PFIFO_CACHE1_DMA_PUSH) | 1); 216 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 217 } 218 219 static void 220 nv04_fifo_dma_pusher(struct nv04_fifo *fifo, u32 chid) 221 { 222 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 223 struct nvkm_device *device = subdev->device; 224 u32 dma_get = nvkm_rd32(device, 0x003244); 225 u32 dma_put = nvkm_rd32(device, 0x003240); 226 u32 push = nvkm_rd32(device, 0x003220); 227 u32 state = nvkm_rd32(device, 0x003228); 228 struct nvkm_fifo_chan *chan; 229 unsigned long flags; 230 const char *name; 231 232 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); 233 name = chan ? chan->object.client->name : "unknown"; 234 if (device->card_type == NV_50) { 235 u32 ho_get = nvkm_rd32(device, 0x003328); 236 u32 ho_put = nvkm_rd32(device, 0x003320); 237 u32 ib_get = nvkm_rd32(device, 0x003334); 238 u32 ib_put = nvkm_rd32(device, 0x003330); 239 240 nvkm_error(subdev, "DMA_PUSHER - " 241 "ch %d [%s] get %02x%08x put %02x%08x ib_get %08x " 242 "ib_put %08x state %08x (err: %s) push %08x\n", 243 chid, name, ho_get, dma_get, ho_put, dma_put, 244 ib_get, ib_put, state, nv_dma_state_err(state), 245 push); 246 247 /* METHOD_COUNT, in DMA_STATE on earlier chipsets */ 248 nvkm_wr32(device, 0x003364, 0x00000000); 249 if (dma_get != dma_put || ho_get != ho_put) { 250 nvkm_wr32(device, 0x003244, dma_put); 251 nvkm_wr32(device, 0x003328, ho_put); 252 } else 253 if (ib_get != ib_put) 254 nvkm_wr32(device, 0x003334, ib_put); 255 } else { 256 nvkm_error(subdev, "DMA_PUSHER - ch %d [%s] get %08x put %08x " 257 "state %08x (err: %s) push %08x\n", 258 chid, name, dma_get, dma_put, state, 259 nv_dma_state_err(state), push); 260 261 if (dma_get != dma_put) 262 nvkm_wr32(device, 0x003244, dma_put); 263 } 264 nvkm_fifo_chan_put(&fifo->base, flags, &chan); 265 266 nvkm_wr32(device, 0x003228, 0x00000000); 267 nvkm_wr32(device, 0x003220, 0x00000001); 268 nvkm_wr32(device, 0x002100, NV_PFIFO_INTR_DMA_PUSHER); 269 } 270 271 void 272 nv04_fifo_intr(struct nvkm_fifo *base) 273 { 274 struct nv04_fifo *fifo = nv04_fifo(base); 275 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 276 struct nvkm_device *device = subdev->device; 277 u32 mask = nvkm_rd32(device, NV03_PFIFO_INTR_EN_0); 278 u32 stat = nvkm_rd32(device, NV03_PFIFO_INTR_0) & mask; 279 u32 reassign, chid, get, sem; 280 281 reassign = nvkm_rd32(device, NV03_PFIFO_CACHES) & 1; 282 nvkm_wr32(device, NV03_PFIFO_CACHES, 0); 283 284 chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & (fifo->base.nr - 1); 285 get = nvkm_rd32(device, NV03_PFIFO_CACHE1_GET); 286 287 if (stat & NV_PFIFO_INTR_CACHE_ERROR) { 288 nv04_fifo_cache_error(fifo, chid, get); 289 stat &= ~NV_PFIFO_INTR_CACHE_ERROR; 290 } 291 292 if (stat & NV_PFIFO_INTR_DMA_PUSHER) { 293 nv04_fifo_dma_pusher(fifo, chid); 294 stat &= ~NV_PFIFO_INTR_DMA_PUSHER; 295 } 296 297 if (stat & NV_PFIFO_INTR_SEMAPHORE) { 298 stat &= ~NV_PFIFO_INTR_SEMAPHORE; 299 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE); 300 301 sem = nvkm_rd32(device, NV10_PFIFO_CACHE1_SEMAPHORE); 302 nvkm_wr32(device, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); 303 304 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4); 305 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 306 } 307 308 if (device->card_type == NV_50) { 309 if (stat & 0x00000010) { 310 stat &= ~0x00000010; 311 nvkm_wr32(device, 0x002100, 0x00000010); 312 } 313 314 if (stat & 0x40000000) { 315 nvkm_wr32(device, 0x002100, 0x40000000); 316 nvkm_fifo_uevent(&fifo->base); 317 stat &= ~0x40000000; 318 } 319 } 320 321 if (stat) { 322 nvkm_warn(subdev, "intr %08x\n", stat); 323 nvkm_mask(device, NV03_PFIFO_INTR_EN_0, stat, 0x00000000); 324 nvkm_wr32(device, NV03_PFIFO_INTR_0, stat); 325 } 326 327 nvkm_wr32(device, NV03_PFIFO_CACHES, reassign); 328 } 329 330 void 331 nv04_fifo_init(struct nvkm_fifo *base) 332 { 333 struct nv04_fifo *fifo = nv04_fifo(base); 334 struct nvkm_device *device = fifo->base.engine.subdev.device; 335 struct nvkm_instmem *imem = device->imem; 336 struct nvkm_ramht *ramht = imem->ramht; 337 struct nvkm_memory *ramro = imem->ramro; 338 struct nvkm_memory *ramfc = imem->ramfc; 339 340 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff); 341 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); 342 343 nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | 344 ((ramht->bits - 9) << 16) | 345 (ramht->gpuobj->addr >> 8)); 346 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); 347 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8); 348 349 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1); 350 351 nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff); 352 nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff); 353 354 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); 355 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 356 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); 357 } 358 359 int 360 nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, 361 enum nvkm_subdev_type type, int inst, int nr, const struct nv04_fifo_ramfc *ramfc, 362 struct nvkm_fifo **pfifo) 363 { 364 struct nv04_fifo *fifo; 365 int ret; 366 367 if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL))) 368 return -ENOMEM; 369 fifo->ramfc = ramfc; 370 *pfifo = &fifo->base; 371 372 ret = nvkm_fifo_ctor(func, device, type, inst, nr, &fifo->base); 373 if (ret) 374 return ret; 375 376 set_bit(nr - 1, fifo->base.mask); /* inactive channel */ 377 return 0; 378 } 379 380 static const struct nvkm_fifo_func 381 nv04_fifo = { 382 .init = nv04_fifo_init, 383 .intr = nv04_fifo_intr, 384 .engine_id = nv04_fifo_engine_id, 385 .id_engine = nv04_fifo_id_engine, 386 .pause = nv04_fifo_pause, 387 .start = nv04_fifo_start, 388 .chan = { 389 &nv04_fifo_dma_oclass, 390 NULL 391 }, 392 }; 393 394 int 395 nv04_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 396 struct nvkm_fifo **pfifo) 397 { 398 return nv04_fifo_new_(&nv04_fifo, device, type, inst, 16, nv04_fifo_ramfc, pfifo); 399 } 400