1c39f472eSBen Skeggs /*
2c39f472eSBen Skeggs * Copyright 2012 Red Hat Inc.
3c39f472eSBen Skeggs *
4c39f472eSBen Skeggs * Permission is hereby granted, free of charge, to any person obtaining a
5c39f472eSBen Skeggs * copy of this software and associated documentation files (the "Software"),
6c39f472eSBen Skeggs * to deal in the Software without restriction, including without limitation
7c39f472eSBen Skeggs * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8c39f472eSBen Skeggs * and/or sell copies of the Software, and to permit persons to whom the
9c39f472eSBen Skeggs * Software is furnished to do so, subject to the following conditions:
10c39f472eSBen Skeggs *
11c39f472eSBen Skeggs * The above copyright notice and this permission notice shall be included in
12c39f472eSBen Skeggs * all copies or substantial portions of the Software.
13c39f472eSBen Skeggs *
14c39f472eSBen Skeggs * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15c39f472eSBen Skeggs * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16c39f472eSBen Skeggs * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17c39f472eSBen Skeggs * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18c39f472eSBen Skeggs * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19c39f472eSBen Skeggs * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20c39f472eSBen Skeggs * OTHER DEALINGS IN THE SOFTWARE.
21c39f472eSBen Skeggs *
22c39f472eSBen Skeggs * Authors: Ben Skeggs
23c39f472eSBen Skeggs */
24*06db7fdeSBen Skeggs #include "priv.h"
25f5e45689SBen Skeggs #include "cgrp.h"
26f5e45689SBen Skeggs #include "chan.h"
27800ac1f8SBen Skeggs #include "chid.h"
28d94470e9SBen Skeggs #include "runl.h"
29f5e45689SBen Skeggs
309a65a38cSBen Skeggs #include "regsnv04.h"
31c39f472eSBen Skeggs
32c39f472eSBen Skeggs #include <core/ramht.h>
33d8e83994SBen Skeggs #include <subdev/instmem.h>
342fc71a05SBen Skeggs #include <subdev/mc.h>
35c39f472eSBen Skeggs #include <subdev/timer.h>
3661570911SBen Skeggs #include <engine/sw.h>
37c39f472eSBen Skeggs
38f5e45689SBen Skeggs #include <nvif/class.h>
39f5e45689SBen Skeggs
40fd67738aSBen Skeggs void
nv04_chan_stop(struct nvkm_chan * chan)4167059b9fSBen Skeggs nv04_chan_stop(struct nvkm_chan *chan)
42fd67738aSBen Skeggs {
433647c53bSBen Skeggs struct nvkm_fifo *fifo = chan->cgrp->runl->fifo;
443647c53bSBen Skeggs struct nvkm_device *device = fifo->engine.subdev.device;
45fd67738aSBen Skeggs struct nvkm_memory *fctx = device->imem->ramfc;
463647c53bSBen Skeggs const struct nvkm_ramfc_layout *c;
47fd67738aSBen Skeggs unsigned long flags;
483647c53bSBen Skeggs u32 data = chan->ramfc_offset;
49fd67738aSBen Skeggs u32 chid;
50fd67738aSBen Skeggs
51fd67738aSBen Skeggs /* prevent fifo context switches */
523647c53bSBen Skeggs spin_lock_irqsave(&fifo->lock, flags);
53fd67738aSBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHES, 0);
54fd67738aSBen Skeggs
55fd67738aSBen Skeggs /* if this channel is active, replace it with a null context */
563647c53bSBen Skeggs chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->chid->mask;
5767059b9fSBen Skeggs if (chid == chan->id) {
58fd67738aSBen Skeggs nvkm_mask(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0);
59fd67738aSBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0);
60fd67738aSBen Skeggs nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0);
61fd67738aSBen Skeggs
623647c53bSBen Skeggs c = chan->func->ramfc->layout;
63fd67738aSBen Skeggs nvkm_kmap(fctx);
64fd67738aSBen Skeggs do {
65fd67738aSBen Skeggs u32 rm = ((1ULL << c->bits) - 1) << c->regs;
66fd67738aSBen Skeggs u32 cm = ((1ULL << c->bits) - 1) << c->ctxs;
67fd67738aSBen Skeggs u32 rv = (nvkm_rd32(device, c->regp) & rm) >> c->regs;
68fd67738aSBen Skeggs u32 cv = (nvkm_ro32(fctx, c->ctxp + data) & ~cm);
69fd67738aSBen Skeggs nvkm_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs));
70fd67738aSBen Skeggs } while ((++c)->bits);
71fd67738aSBen Skeggs nvkm_done(fctx);
72fd67738aSBen Skeggs
733647c53bSBen Skeggs c = chan->func->ramfc->layout;
74fd67738aSBen Skeggs do {
75fd67738aSBen Skeggs nvkm_wr32(device, c->regp, 0x00000000);
76fd67738aSBen Skeggs } while ((++c)->bits);
77fd67738aSBen Skeggs
78fd67738aSBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, 0);
79fd67738aSBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHE1_PUT, 0);
803647c53bSBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask);
81fd67738aSBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
82fd67738aSBen Skeggs nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
83fd67738aSBen Skeggs }
84fd67738aSBen Skeggs
85fd67738aSBen Skeggs /* restore normal operation, after disabling dma mode */
8667059b9fSBen Skeggs nvkm_mask(device, NV04_PFIFO_MODE, BIT(chan->id), 0);
87fd67738aSBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
883647c53bSBen Skeggs spin_unlock_irqrestore(&fifo->lock, flags);
89fd67738aSBen Skeggs }
90fd67738aSBen Skeggs
91fd67738aSBen Skeggs void
nv04_chan_start(struct nvkm_chan * chan)9267059b9fSBen Skeggs nv04_chan_start(struct nvkm_chan *chan)
93fd67738aSBen Skeggs {
9467059b9fSBen Skeggs struct nvkm_fifo *fifo = chan->cgrp->runl->fifo;
95fd67738aSBen Skeggs unsigned long flags;
9667059b9fSBen Skeggs
9767059b9fSBen Skeggs spin_lock_irqsave(&fifo->lock, flags);
9867059b9fSBen Skeggs nvkm_mask(fifo->engine.subdev.device, NV04_PFIFO_MODE, BIT(chan->id), BIT(chan->id));
9967059b9fSBen Skeggs spin_unlock_irqrestore(&fifo->lock, flags);
100fd67738aSBen Skeggs }
101fd67738aSBen Skeggs
1023647c53bSBen Skeggs void
nv04_chan_ramfc_clear(struct nvkm_chan * chan)1033647c53bSBen Skeggs nv04_chan_ramfc_clear(struct nvkm_chan *chan)
1043647c53bSBen Skeggs {
1053647c53bSBen Skeggs struct nvkm_memory *ramfc = chan->cgrp->runl->fifo->engine.subdev.device->imem->ramfc;
1063647c53bSBen Skeggs const struct nvkm_ramfc_layout *c = chan->func->ramfc->layout;
1073647c53bSBen Skeggs
1083647c53bSBen Skeggs nvkm_kmap(ramfc);
1093647c53bSBen Skeggs do {
1103647c53bSBen Skeggs nvkm_wo32(ramfc, chan->ramfc_offset + c->ctxp, 0x00000000);
1113647c53bSBen Skeggs } while ((++c)->bits);
1123647c53bSBen Skeggs nvkm_done(ramfc);
1133647c53bSBen Skeggs }
1143647c53bSBen Skeggs
1153647c53bSBen Skeggs static int
nv04_chan_ramfc_write(struct nvkm_chan * chan,u64 offset,u64 length,u32 devm,bool priv)1163647c53bSBen Skeggs nv04_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv)
1173647c53bSBen Skeggs {
1183647c53bSBen Skeggs struct nvkm_memory *ramfc = chan->cgrp->runl->fifo->engine.subdev.device->imem->ramfc;
1193647c53bSBen Skeggs const u32 base = chan->id * 32;
1203647c53bSBen Skeggs
1213647c53bSBen Skeggs chan->ramfc_offset = base;
1223647c53bSBen Skeggs
1233647c53bSBen Skeggs nvkm_kmap(ramfc);
1243647c53bSBen Skeggs nvkm_wo32(ramfc, base + 0x00, offset);
1253647c53bSBen Skeggs nvkm_wo32(ramfc, base + 0x04, offset);
1263647c53bSBen Skeggs nvkm_wo32(ramfc, base + 0x08, chan->push->addr >> 4);
1273647c53bSBen Skeggs nvkm_wo32(ramfc, base + 0x10, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
1283647c53bSBen Skeggs NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
1293647c53bSBen Skeggs #ifdef __BIG_ENDIAN
1303647c53bSBen Skeggs NV_PFIFO_CACHE1_BIG_ENDIAN |
1313647c53bSBen Skeggs #endif
1323647c53bSBen Skeggs NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
1333647c53bSBen Skeggs nvkm_done(ramfc);
1343647c53bSBen Skeggs return 0;
1353647c53bSBen Skeggs }
1363647c53bSBen Skeggs
1373647c53bSBen Skeggs static const struct nvkm_chan_func_ramfc
1383647c53bSBen Skeggs nv04_chan_ramfc = {
1393647c53bSBen Skeggs .layout = (const struct nvkm_ramfc_layout[]) {
1403647c53bSBen Skeggs { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
1413647c53bSBen Skeggs { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
1423647c53bSBen Skeggs { 16, 0, 0x08, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
1433647c53bSBen Skeggs { 16, 16, 0x08, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
1443647c53bSBen Skeggs { 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_STATE },
1453647c53bSBen Skeggs { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_FETCH },
1463647c53bSBen Skeggs { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_ENGINE },
1473647c53bSBen Skeggs { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_PULL1 },
1483647c53bSBen Skeggs {}
1493647c53bSBen Skeggs },
1503647c53bSBen Skeggs .write = nv04_chan_ramfc_write,
1513647c53bSBen Skeggs .clear = nv04_chan_ramfc_clear,
1523647c53bSBen Skeggs .ctxdma = true,
1533647c53bSBen Skeggs };
1543647c53bSBen Skeggs
155fbe9f433SBen Skeggs const struct nvkm_chan_func_userd
156fbe9f433SBen Skeggs nv04_chan_userd = {
157fbe9f433SBen Skeggs .bar = 0,
158fbe9f433SBen Skeggs .base = 0x800000,
159fbe9f433SBen Skeggs .size = 0x010000,
160fbe9f433SBen Skeggs };
161fbe9f433SBen Skeggs
162d3e7a439SBen Skeggs const struct nvkm_chan_func_inst
163d3e7a439SBen Skeggs nv04_chan_inst = {
164d3e7a439SBen Skeggs .size = 0x1000,
165d3e7a439SBen Skeggs };
166d3e7a439SBen Skeggs
167f5e45689SBen Skeggs static const struct nvkm_chan_func
168f5e45689SBen Skeggs nv04_chan = {
169d3e7a439SBen Skeggs .inst = &nv04_chan_inst,
170fbe9f433SBen Skeggs .userd = &nv04_chan_userd,
1713647c53bSBen Skeggs .ramfc = &nv04_chan_ramfc,
17267059b9fSBen Skeggs .start = nv04_chan_start,
17367059b9fSBen Skeggs .stop = nv04_chan_stop,
174f5e45689SBen Skeggs };
175f5e45689SBen Skeggs
176f5e45689SBen Skeggs const struct nvkm_cgrp_func
177f5e45689SBen Skeggs nv04_cgrp = {
178f5e45689SBen Skeggs };
179f5e45689SBen Skeggs
1807ac29332SBen Skeggs void
nv04_eobj_ramht_del(struct nvkm_chan * chan,int hash)1817ac29332SBen Skeggs nv04_eobj_ramht_del(struct nvkm_chan *chan, int hash)
1827ac29332SBen Skeggs {
1837ac29332SBen Skeggs struct nvkm_fifo *fifo = chan->cgrp->runl->fifo;
1847ac29332SBen Skeggs struct nvkm_instmem *imem = fifo->engine.subdev.device->imem;
1857ac29332SBen Skeggs
1867ac29332SBen Skeggs mutex_lock(&fifo->mutex);
1877ac29332SBen Skeggs nvkm_ramht_remove(imem->ramht, hash);
1887ac29332SBen Skeggs mutex_unlock(&fifo->mutex);
1897ac29332SBen Skeggs }
1907ac29332SBen Skeggs
1917ac29332SBen Skeggs static int
nv04_eobj_ramht_add(struct nvkm_engn * engn,struct nvkm_object * eobj,struct nvkm_chan * chan)1927ac29332SBen Skeggs nv04_eobj_ramht_add(struct nvkm_engn *engn, struct nvkm_object *eobj, struct nvkm_chan *chan)
1937ac29332SBen Skeggs {
1947ac29332SBen Skeggs struct nvkm_fifo *fifo = chan->cgrp->runl->fifo;
1957ac29332SBen Skeggs struct nvkm_instmem *imem = fifo->engine.subdev.device->imem;
1967ac29332SBen Skeggs u32 context = 0x80000000 | chan->id << 24 | engn->id << 16;
1977ac29332SBen Skeggs int hash;
1987ac29332SBen Skeggs
1997ac29332SBen Skeggs mutex_lock(&fifo->mutex);
2007ac29332SBen Skeggs hash = nvkm_ramht_insert(imem->ramht, eobj, chan->id, 4, eobj->handle, context);
2017ac29332SBen Skeggs mutex_unlock(&fifo->mutex);
2027ac29332SBen Skeggs return hash;
2037ac29332SBen Skeggs }
2047ac29332SBen Skeggs
205d94470e9SBen Skeggs const struct nvkm_engn_func
206d94470e9SBen Skeggs nv04_engn = {
2077ac29332SBen Skeggs .ramht_add = nv04_eobj_ramht_add,
2087ac29332SBen Skeggs .ramht_del = nv04_eobj_ramht_del,
209d94470e9SBen Skeggs };
210d94470e9SBen Skeggs
211c39f472eSBen Skeggs void
nv04_fifo_pause(struct nvkm_fifo * fifo,unsigned long * pflags)2123a6bc9c2SBen Skeggs nv04_fifo_pause(struct nvkm_fifo *fifo, unsigned long *pflags)
2133a6bc9c2SBen Skeggs __acquires(fifo->lock)
214c39f472eSBen Skeggs {
2153a6bc9c2SBen Skeggs struct nvkm_device *device = fifo->engine.subdev.device;
216c39f472eSBen Skeggs unsigned long flags;
217c39f472eSBen Skeggs
2183a6bc9c2SBen Skeggs spin_lock_irqsave(&fifo->lock, flags);
219c39f472eSBen Skeggs *pflags = flags;
220c39f472eSBen Skeggs
22187744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000000);
22287744403SBen Skeggs nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000);
223c39f472eSBen Skeggs
224c39f472eSBen Skeggs /* in some cases the puller may be left in an inconsistent state
225c39f472eSBen Skeggs * if you try to stop it while it's busy translating handles.
226c39f472eSBen Skeggs * sometimes you get a CACHE_ERROR, sometimes it just fails
227c39f472eSBen Skeggs * silently; sending incorrect instance offsets to PGRAPH after
228c39f472eSBen Skeggs * it's started up again.
229c39f472eSBen Skeggs *
230c39f472eSBen Skeggs * to avoid this, we invalidate the most recently calculated
231c39f472eSBen Skeggs * instance.
232c39f472eSBen Skeggs */
233af3082b3SBen Skeggs nvkm_msec(device, 2000,
234af3082b3SBen Skeggs u32 tmp = nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0);
235af3082b3SBen Skeggs if (!(tmp & NV04_PFIFO_CACHE1_PULL0_HASH_BUSY))
236af3082b3SBen Skeggs break;
237af3082b3SBen Skeggs );
238c39f472eSBen Skeggs
23987744403SBen Skeggs if (nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0) &
240c39f472eSBen Skeggs NV04_PFIFO_CACHE1_PULL0_HASH_FAILED)
24187744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
242c39f472eSBen Skeggs
24387744403SBen Skeggs nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0x00000000);
244c39f472eSBen Skeggs }
245c39f472eSBen Skeggs
246c39f472eSBen Skeggs void
nv04_fifo_start(struct nvkm_fifo * fifo,unsigned long * pflags)2473a6bc9c2SBen Skeggs nv04_fifo_start(struct nvkm_fifo *fifo, unsigned long *pflags)
2483a6bc9c2SBen Skeggs __releases(fifo->lock)
249c39f472eSBen Skeggs {
2503a6bc9c2SBen Skeggs struct nvkm_device *device = fifo->engine.subdev.device;
251c39f472eSBen Skeggs unsigned long flags = *pflags;
252c39f472eSBen Skeggs
25387744403SBen Skeggs nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001);
25487744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000001);
255c39f472eSBen Skeggs
2563a6bc9c2SBen Skeggs spin_unlock_irqrestore(&fifo->lock, flags);
257c39f472eSBen Skeggs }
258c39f472eSBen Skeggs
259d94470e9SBen Skeggs const struct nvkm_runl_func
260d94470e9SBen Skeggs nv04_runl = {
261d94470e9SBen Skeggs };
262d94470e9SBen Skeggs
263c39f472eSBen Skeggs static const char *
nv_dma_state_err(u32 state)264c39f472eSBen Skeggs nv_dma_state_err(u32 state)
265c39f472eSBen Skeggs {
266c39f472eSBen Skeggs static const char * const desc[] = {
267c39f472eSBen Skeggs "NONE", "CALL_SUBR_ACTIVE", "INVALID_MTHD", "RET_SUBR_INACTIVE",
268c39f472eSBen Skeggs "INVALID_CMD", "IB_EMPTY"/* NV50+ */, "MEM_FAULT", "UNK"
269c39f472eSBen Skeggs };
270c39f472eSBen Skeggs return desc[(state >> 29) & 0x7];
271c39f472eSBen Skeggs }
272c39f472eSBen Skeggs
273c39f472eSBen Skeggs static bool
nv04_fifo_swmthd(struct nvkm_device * device,u32 chid,u32 addr,u32 data)27461570911SBen Skeggs nv04_fifo_swmthd(struct nvkm_device *device, u32 chid, u32 addr, u32 data)
275c39f472eSBen Skeggs {
27661570911SBen Skeggs struct nvkm_sw *sw = device->sw;
27761570911SBen Skeggs const int subc = (addr & 0x0000e000) >> 13;
27861570911SBen Skeggs const int mthd = (addr & 0x00001ffc);
27961570911SBen Skeggs const u32 mask = 0x0000000f << (subc * 4);
28061570911SBen Skeggs u32 engine = nvkm_rd32(device, 0x003280);
281c39f472eSBen Skeggs bool handled = false;
282c39f472eSBen Skeggs
283c39f472eSBen Skeggs switch (mthd) {
28461570911SBen Skeggs case 0x0000 ... 0x0000: /* subchannel's engine -> software */
28561570911SBen Skeggs nvkm_wr32(device, 0x003280, (engine &= ~mask));
286f6e7393eSGustavo A. R. Silva fallthrough;
28761570911SBen Skeggs case 0x0180 ... 0x01fc: /* handle -> instance */
28861570911SBen Skeggs data = nvkm_rd32(device, 0x003258) & 0x0000ffff;
289f6e7393eSGustavo A. R. Silva fallthrough;
29061570911SBen Skeggs case 0x0100 ... 0x017c:
29161570911SBen Skeggs case 0x0200 ... 0x1ffc: /* pass method down to sw */
29261570911SBen Skeggs if (!(engine & mask) && sw)
29361570911SBen Skeggs handled = nvkm_sw_mthd(sw, chid, subc, mthd, data);
294c39f472eSBen Skeggs break;
295c39f472eSBen Skeggs default:
296c39f472eSBen Skeggs break;
297c39f472eSBen Skeggs }
298c39f472eSBen Skeggs
299c39f472eSBen Skeggs return handled;
300c39f472eSBen Skeggs }
301c39f472eSBen Skeggs
302c39f472eSBen Skeggs static void
nv04_fifo_intr_cache_error(struct nvkm_fifo * fifo,u32 chid,u32 get)3032fc71a05SBen Skeggs nv04_fifo_intr_cache_error(struct nvkm_fifo *fifo, u32 chid, u32 get)
304c39f472eSBen Skeggs {
3052fc71a05SBen Skeggs struct nvkm_subdev *subdev = &fifo->engine.subdev;
306e5c5e4f5SBen Skeggs struct nvkm_device *device = subdev->device;
307c358f538SBen Skeggs struct nvkm_chan *chan;
3088f0649b5SBen Skeggs unsigned long flags;
30961570911SBen Skeggs u32 pull0 = nvkm_rd32(device, 0x003250);
310c39f472eSBen Skeggs u32 mthd, data;
311c39f472eSBen Skeggs int ptr;
312c39f472eSBen Skeggs
313c39f472eSBen Skeggs /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before wrapping on my
314c39f472eSBen Skeggs * G80 chips, but CACHE1 isn't big enough for this much data.. Tests
315c39f472eSBen Skeggs * show that it wraps around to the start at GET=0x800.. No clue as to
316c39f472eSBen Skeggs * why..
317c39f472eSBen Skeggs */
318c39f472eSBen Skeggs ptr = (get & 0x7ff) >> 2;
319c39f472eSBen Skeggs
320c39f472eSBen Skeggs if (device->card_type < NV_40) {
32187744403SBen Skeggs mthd = nvkm_rd32(device, NV04_PFIFO_CACHE1_METHOD(ptr));
32287744403SBen Skeggs data = nvkm_rd32(device, NV04_PFIFO_CACHE1_DATA(ptr));
323c39f472eSBen Skeggs } else {
32487744403SBen Skeggs mthd = nvkm_rd32(device, NV40_PFIFO_CACHE1_METHOD(ptr));
32587744403SBen Skeggs data = nvkm_rd32(device, NV40_PFIFO_CACHE1_DATA(ptr));
326c39f472eSBen Skeggs }
327c39f472eSBen Skeggs
32861570911SBen Skeggs if (!(pull0 & 0x00000100) ||
32961570911SBen Skeggs !nv04_fifo_swmthd(device, chid, mthd, data)) {
330c358f538SBen Skeggs chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags);
331e5c5e4f5SBen Skeggs nvkm_error(subdev, "CACHE_ERROR - "
332e5c5e4f5SBen Skeggs "ch %d [%s] subc %d mthd %04x data %08x\n",
333c358f538SBen Skeggs chid, chan ? chan->name : "unknown",
3348f0649b5SBen Skeggs (mthd >> 13) & 7, mthd & 0x1ffc, data);
335c358f538SBen Skeggs nvkm_chan_put(&chan, flags);
336c39f472eSBen Skeggs }
337c39f472eSBen Skeggs
33887744403SBen Skeggs nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
33987744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
340c39f472eSBen Skeggs
34187744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0,
34287744403SBen Skeggs nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) & ~1);
34387744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4);
34487744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0,
34587744403SBen Skeggs nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) | 1);
34687744403SBen Skeggs nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0);
347c39f472eSBen Skeggs
34887744403SBen Skeggs nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH,
34987744403SBen Skeggs nvkm_rd32(device, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
35087744403SBen Skeggs nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
351c39f472eSBen Skeggs }
352c39f472eSBen Skeggs
353c39f472eSBen Skeggs static void
nv04_fifo_intr_dma_pusher(struct nvkm_fifo * fifo,u32 chid)3542fc71a05SBen Skeggs nv04_fifo_intr_dma_pusher(struct nvkm_fifo *fifo, u32 chid)
355c39f472eSBen Skeggs {
3562fc71a05SBen Skeggs struct nvkm_subdev *subdev = &fifo->engine.subdev;
357e5c5e4f5SBen Skeggs struct nvkm_device *device = subdev->device;
35887744403SBen Skeggs u32 dma_get = nvkm_rd32(device, 0x003244);
35987744403SBen Skeggs u32 dma_put = nvkm_rd32(device, 0x003240);
36087744403SBen Skeggs u32 push = nvkm_rd32(device, 0x003220);
36187744403SBen Skeggs u32 state = nvkm_rd32(device, 0x003228);
362c358f538SBen Skeggs struct nvkm_chan *chan;
3638f0649b5SBen Skeggs unsigned long flags;
3648f0649b5SBen Skeggs const char *name;
365c39f472eSBen Skeggs
366c358f538SBen Skeggs chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags);
367c358f538SBen Skeggs name = chan ? chan->name : "unknown";
368c39f472eSBen Skeggs if (device->card_type == NV_50) {
36987744403SBen Skeggs u32 ho_get = nvkm_rd32(device, 0x003328);
37087744403SBen Skeggs u32 ho_put = nvkm_rd32(device, 0x003320);
37187744403SBen Skeggs u32 ib_get = nvkm_rd32(device, 0x003334);
37287744403SBen Skeggs u32 ib_put = nvkm_rd32(device, 0x003330);
373c39f472eSBen Skeggs
374e5c5e4f5SBen Skeggs nvkm_error(subdev, "DMA_PUSHER - "
375e5c5e4f5SBen Skeggs "ch %d [%s] get %02x%08x put %02x%08x ib_get %08x "
376e5c5e4f5SBen Skeggs "ib_put %08x state %08x (err: %s) push %08x\n",
3778f0649b5SBen Skeggs chid, name, ho_get, dma_get, ho_put, dma_put,
378e5c5e4f5SBen Skeggs ib_get, ib_put, state, nv_dma_state_err(state),
379e5c5e4f5SBen Skeggs push);
380c39f472eSBen Skeggs
381c39f472eSBen Skeggs /* METHOD_COUNT, in DMA_STATE on earlier chipsets */
38287744403SBen Skeggs nvkm_wr32(device, 0x003364, 0x00000000);
383c39f472eSBen Skeggs if (dma_get != dma_put || ho_get != ho_put) {
38487744403SBen Skeggs nvkm_wr32(device, 0x003244, dma_put);
38587744403SBen Skeggs nvkm_wr32(device, 0x003328, ho_put);
386c39f472eSBen Skeggs } else
387c39f472eSBen Skeggs if (ib_get != ib_put)
38887744403SBen Skeggs nvkm_wr32(device, 0x003334, ib_put);
389c39f472eSBen Skeggs } else {
390e5c5e4f5SBen Skeggs nvkm_error(subdev, "DMA_PUSHER - ch %d [%s] get %08x put %08x "
391e5c5e4f5SBen Skeggs "state %08x (err: %s) push %08x\n",
3928f0649b5SBen Skeggs chid, name, dma_get, dma_put, state,
393c39f472eSBen Skeggs nv_dma_state_err(state), push);
394c39f472eSBen Skeggs
395c39f472eSBen Skeggs if (dma_get != dma_put)
39687744403SBen Skeggs nvkm_wr32(device, 0x003244, dma_put);
397c39f472eSBen Skeggs }
398c358f538SBen Skeggs nvkm_chan_put(&chan, flags);
399c39f472eSBen Skeggs
40087744403SBen Skeggs nvkm_wr32(device, 0x003228, 0x00000000);
40187744403SBen Skeggs nvkm_wr32(device, 0x003220, 0x00000001);
40287744403SBen Skeggs nvkm_wr32(device, 0x002100, NV_PFIFO_INTR_DMA_PUSHER);
403c39f472eSBen Skeggs }
404c39f472eSBen Skeggs
4052fc71a05SBen Skeggs irqreturn_t
nv04_fifo_intr(struct nvkm_inth * inth)4062fc71a05SBen Skeggs nv04_fifo_intr(struct nvkm_inth *inth)
407c39f472eSBen Skeggs {
4082fc71a05SBen Skeggs struct nvkm_fifo *fifo = container_of(inth, typeof(*fifo), engine.subdev.inth);
4092fc71a05SBen Skeggs struct nvkm_subdev *subdev = &fifo->engine.subdev;
410e5c5e4f5SBen Skeggs struct nvkm_device *device = subdev->device;
41187744403SBen Skeggs u32 mask = nvkm_rd32(device, NV03_PFIFO_INTR_EN_0);
41287744403SBen Skeggs u32 stat = nvkm_rd32(device, NV03_PFIFO_INTR_0) & mask;
413adc346b1SBen Skeggs u32 reassign, chid, get, sem;
414c39f472eSBen Skeggs
41587744403SBen Skeggs reassign = nvkm_rd32(device, NV03_PFIFO_CACHES) & 1;
41687744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHES, 0);
417c39f472eSBen Skeggs
4182fc71a05SBen Skeggs chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->chid->mask;
41987744403SBen Skeggs get = nvkm_rd32(device, NV03_PFIFO_CACHE1_GET);
420c39f472eSBen Skeggs
421adc346b1SBen Skeggs if (stat & NV_PFIFO_INTR_CACHE_ERROR) {
4222fc71a05SBen Skeggs nv04_fifo_intr_cache_error(fifo, chid, get);
423adc346b1SBen Skeggs stat &= ~NV_PFIFO_INTR_CACHE_ERROR;
424c39f472eSBen Skeggs }
425c39f472eSBen Skeggs
426adc346b1SBen Skeggs if (stat & NV_PFIFO_INTR_DMA_PUSHER) {
4272fc71a05SBen Skeggs nv04_fifo_intr_dma_pusher(fifo, chid);
428adc346b1SBen Skeggs stat &= ~NV_PFIFO_INTR_DMA_PUSHER;
429c39f472eSBen Skeggs }
430c39f472eSBen Skeggs
431adc346b1SBen Skeggs if (stat & NV_PFIFO_INTR_SEMAPHORE) {
432adc346b1SBen Skeggs stat &= ~NV_PFIFO_INTR_SEMAPHORE;
43387744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE);
434c39f472eSBen Skeggs
43587744403SBen Skeggs sem = nvkm_rd32(device, NV10_PFIFO_CACHE1_SEMAPHORE);
43687744403SBen Skeggs nvkm_wr32(device, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
437c39f472eSBen Skeggs
43887744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4);
43987744403SBen Skeggs nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
440c39f472eSBen Skeggs }
441c39f472eSBen Skeggs
442c39f472eSBen Skeggs if (device->card_type == NV_50) {
443adc346b1SBen Skeggs if (stat & 0x00000010) {
444adc346b1SBen Skeggs stat &= ~0x00000010;
44587744403SBen Skeggs nvkm_wr32(device, 0x002100, 0x00000010);
446c39f472eSBen Skeggs }
447c39f472eSBen Skeggs
448adc346b1SBen Skeggs if (stat & 0x40000000) {
44987744403SBen Skeggs nvkm_wr32(device, 0x002100, 0x40000000);
450d67f3b96SBen Skeggs nvkm_event_ntfy(&fifo->nonstall.event, 0, NVKM_FIFO_NONSTALL_EVENT);
451adc346b1SBen Skeggs stat &= ~0x40000000;
452c39f472eSBen Skeggs }
453c39f472eSBen Skeggs }
454c39f472eSBen Skeggs
455adc346b1SBen Skeggs if (stat) {
456e5c5e4f5SBen Skeggs nvkm_warn(subdev, "intr %08x\n", stat);
45787744403SBen Skeggs nvkm_mask(device, NV03_PFIFO_INTR_EN_0, stat, 0x00000000);
45887744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_INTR_0, stat);
459c39f472eSBen Skeggs }
460c39f472eSBen Skeggs
46187744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHES, reassign);
4622fc71a05SBen Skeggs return IRQ_HANDLED;
463c39f472eSBen Skeggs }
464c39f472eSBen Skeggs
46513de7f46SBen Skeggs void
nv04_fifo_init(struct nvkm_fifo * fifo)466800ac1f8SBen Skeggs nv04_fifo_init(struct nvkm_fifo *fifo)
467c39f472eSBen Skeggs {
468800ac1f8SBen Skeggs struct nvkm_device *device = fifo->engine.subdev.device;
4695b1ab0c2SBen Skeggs struct nvkm_instmem *imem = device->imem;
4705b1ab0c2SBen Skeggs struct nvkm_ramht *ramht = imem->ramht;
4715b1ab0c2SBen Skeggs struct nvkm_memory *ramro = imem->ramro;
4725b1ab0c2SBen Skeggs struct nvkm_memory *ramfc = imem->ramfc;
473c39f472eSBen Skeggs
47487744403SBen Skeggs nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff);
47587744403SBen Skeggs nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
476c39f472eSBen Skeggs
47787744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
4785b1ab0c2SBen Skeggs ((ramht->bits - 9) << 16) |
4791d2a1e53SBen Skeggs (ramht->gpuobj->addr >> 8));
4805b1ab0c2SBen Skeggs nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);
4815b1ab0c2SBen Skeggs nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8);
482c39f472eSBen Skeggs
483800ac1f8SBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask);
484c39f472eSBen Skeggs
48587744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff);
48687744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff);
487c39f472eSBen Skeggs
48887744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
48987744403SBen Skeggs nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
49087744403SBen Skeggs nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
49113de7f46SBen Skeggs }
49213de7f46SBen Skeggs
493800ac1f8SBen Skeggs int
nv04_fifo_runl_ctor(struct nvkm_fifo * fifo)494d94470e9SBen Skeggs nv04_fifo_runl_ctor(struct nvkm_fifo *fifo)
495d94470e9SBen Skeggs {
496d94470e9SBen Skeggs struct nvkm_runl *runl;
497d94470e9SBen Skeggs
498d94470e9SBen Skeggs runl = nvkm_runl_new(fifo, 0, 0, 0);
499d94470e9SBen Skeggs if (IS_ERR(runl))
500d94470e9SBen Skeggs return PTR_ERR(runl);
501d94470e9SBen Skeggs
502d94470e9SBen Skeggs nvkm_runl_add(runl, 0, fifo->func->engn_sw, NVKM_ENGINE_SW, 0);
503d94470e9SBen Skeggs nvkm_runl_add(runl, 0, fifo->func->engn_sw, NVKM_ENGINE_DMAOBJ, 0);
504d94470e9SBen Skeggs nvkm_runl_add(runl, 1, fifo->func->engn , NVKM_ENGINE_GR, 0);
505d94470e9SBen Skeggs nvkm_runl_add(runl, 2, fifo->func->engn , NVKM_ENGINE_MPEG, 0); /* NV31- */
506d94470e9SBen Skeggs return 0;
507d94470e9SBen Skeggs }
508d94470e9SBen Skeggs
509d94470e9SBen Skeggs int
nv04_fifo_chid_ctor(struct nvkm_fifo * fifo,int nr)510800ac1f8SBen Skeggs nv04_fifo_chid_ctor(struct nvkm_fifo *fifo, int nr)
511800ac1f8SBen Skeggs {
512800ac1f8SBen Skeggs /* The last CHID is reserved by HW as a "channel invalid" marker. */
513800ac1f8SBen Skeggs return nvkm_chid_new(&nvkm_chan_event, &fifo->engine.subdev, nr, 0, nr - 1, &fifo->chid);
514800ac1f8SBen Skeggs }
515800ac1f8SBen Skeggs
5168c18138cSBen Skeggs static int
nv04_fifo_chid_nr(struct nvkm_fifo * fifo)5178c18138cSBen Skeggs nv04_fifo_chid_nr(struct nvkm_fifo *fifo)
5188c18138cSBen Skeggs {
5198c18138cSBen Skeggs return 16;
5208c18138cSBen Skeggs }
5218c18138cSBen Skeggs
5228f0649b5SBen Skeggs static const struct nvkm_fifo_func
52313de7f46SBen Skeggs nv04_fifo = {
5248c18138cSBen Skeggs .chid_nr = nv04_fifo_chid_nr,
525800ac1f8SBen Skeggs .chid_ctor = nv04_fifo_chid_ctor,
526d94470e9SBen Skeggs .runl_ctor = nv04_fifo_runl_ctor,
52713de7f46SBen Skeggs .init = nv04_fifo_init,
52813de7f46SBen Skeggs .intr = nv04_fifo_intr,
52913de7f46SBen Skeggs .pause = nv04_fifo_pause,
53013de7f46SBen Skeggs .start = nv04_fifo_start,
531d94470e9SBen Skeggs .runl = &nv04_runl,
532d94470e9SBen Skeggs .engn = &nv04_engn,
533d94470e9SBen Skeggs .engn_sw = &nv04_engn,
534f5e45689SBen Skeggs .cgrp = {{ }, &nv04_cgrp },
535*06db7fdeSBen Skeggs .chan = {{ 0, 0, NV03_CHANNEL_DMA }, &nv04_chan },
5368f0649b5SBen Skeggs };
5378f0649b5SBen Skeggs
53813de7f46SBen Skeggs int
nv04_fifo_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_fifo ** pfifo)539ab0db2bdSBen Skeggs nv04_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
540ab0db2bdSBen Skeggs struct nvkm_fifo **pfifo)
5419a65a38cSBen Skeggs {
542*06db7fdeSBen Skeggs return nvkm_fifo_new_(&nv04_fifo, device, type, inst, pfifo);
5439a65a38cSBen Skeggs }
544