1 /*
2  * Copyright 2016 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "priv.h"
25 #include "runl.h"
26 
27 #include <core/gpuobj.h>
28 #include <subdev/fault.h>
29 
30 #include <nvif/class.h>
31 
32 static void
33 gp100_runl_insert_chan(struct nvkm_chan *chan, struct nvkm_memory *memory, u64 offset)
34 {
35 	nvkm_wo32(memory, offset + 0, chan->id | chan->runq << 14);
36 	nvkm_wo32(memory, offset + 4, chan->inst->addr >> 12);
37 }
38 
39 static const struct nvkm_runl_func
40 gp100_runl = {
41 	.runqs = 2,
42 	.size = 8,
43 	.update = nv50_runl_update,
44 	.insert_cgrp = gk110_runl_insert_cgrp,
45 	.insert_chan = gp100_runl_insert_chan,
46 	.commit = gk104_runl_commit,
47 	.wait = nv50_runl_wait,
48 	.pending = gk104_runl_pending,
49 	.block = gk104_runl_block,
50 	.allow = gk104_runl_allow,
51 	.fault_clear = gk104_runl_fault_clear,
52 	.preempt_pending = gf100_runl_preempt_pending,
53 };
54 
55 static const struct nvkm_enum
56 gp100_fifo_mmu_fault_engine[] = {
57 	{ 0x01, "DISPLAY" },
58 	{ 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
59 	{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
60 	{ 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
61 	{ 0x06, "HOST0" },
62 	{ 0x07, "HOST1" },
63 	{ 0x08, "HOST2" },
64 	{ 0x09, "HOST3" },
65 	{ 0x0a, "HOST4" },
66 	{ 0x0b, "HOST5" },
67 	{ 0x0c, "HOST6" },
68 	{ 0x0d, "HOST7" },
69 	{ 0x0e, "HOST8" },
70 	{ 0x0f, "HOST9" },
71 	{ 0x10, "HOST10" },
72 	{ 0x13, "PERF" },
73 	{ 0x17, "PMU" },
74 	{ 0x18, "PTP" },
75 	{ 0x1f, "PHYSICAL" },
76 	{}
77 };
78 
79 static const struct nvkm_fifo_func_mmu_fault
80 gp100_fifo_mmu_fault = {
81 	.recover = gf100_fifo_mmu_fault_recover,
82 	.access = gf100_fifo_mmu_fault_access,
83 	.engine = gp100_fifo_mmu_fault_engine,
84 	.reason = gk104_fifo_mmu_fault_reason,
85 	.hubclient = gk104_fifo_mmu_fault_hubclient,
86 	.gpcclient = gk104_fifo_mmu_fault_gpcclient,
87 };
88 
89 static void
90 gp100_fifo_intr_mmu_fault_unit(struct nvkm_fifo *fifo, int unit)
91 {
92 	struct nvkm_device *device = fifo->engine.subdev.device;
93 	u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
94 	u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
95 	u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
96 	u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10));
97 	struct nvkm_fault_data info;
98 
99 	info.inst   =  (u64)inst << 12;
100 	info.addr   = ((u64)vahi << 32) | valo;
101 	info.time   = 0;
102 	info.engine = unit;
103 	info.valid  = 1;
104 	info.gpc    = (type & 0x1f000000) >> 24;
105 	info.hub    = (type & 0x00100000) >> 20;
106 	info.access = (type & 0x00070000) >> 16;
107 	info.client = (type & 0x00007f00) >> 8;
108 	info.reason = (type & 0x0000001f);
109 
110 	nvkm_fifo_fault(fifo, &info);
111 }
112 
113 static const struct nvkm_fifo_func
114 gp100_fifo = {
115 	.chid_nr = gm200_fifo_chid_nr,
116 	.chid_ctor = gk110_fifo_chid_ctor,
117 	.runq_nr = gm200_fifo_runq_nr,
118 	.runl_ctor = gk104_fifo_runl_ctor,
119 	.init = gk104_fifo_init,
120 	.init_pbdmas = gk104_fifo_init_pbdmas,
121 	.intr = gk104_fifo_intr,
122 	.intr_mmu_fault_unit = gp100_fifo_intr_mmu_fault_unit,
123 	.intr_ctxsw_timeout = gf100_fifo_intr_ctxsw_timeout,
124 	.mmu_fault = &gp100_fifo_mmu_fault,
125 	.nonstall = &gf100_fifo_nonstall,
126 	.runl = &gp100_runl,
127 	.runq = &gk208_runq,
128 	.engn = &gk104_engn,
129 	.engn_ce = &gk104_engn_ce,
130 	.cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A  }, &gk110_cgrp, .force = true },
131 	.chan = {{ 0, 0, PASCAL_CHANNEL_GPFIFO_A }, &gm107_chan },
132 };
133 
134 int
135 gp100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
136 	       struct nvkm_fifo **pfifo)
137 {
138 	return nvkm_fifo_new_(&gp100_fifo, device, type, inst, pfifo);
139 }
140