1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "gk104.h" 25 #include "cgrp.h" 26 #include "changk104.h" 27 28 #include <core/client.h> 29 #include <core/gpuobj.h> 30 #include <subdev/bar.h> 31 #include <subdev/fault.h> 32 #include <subdev/timer.h> 33 #include <subdev/top.h> 34 #include <engine/sw.h> 35 36 #include <nvif/class.h> 37 #include <nvif/cl0080.h> 38 39 void 40 gk104_fifo_engine_status(struct gk104_fifo *fifo, int engn, 41 struct gk104_fifo_engine_status *status) 42 { 43 struct nvkm_engine *engine = fifo->engine[engn].engine; 44 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 45 struct nvkm_device *device = subdev->device; 46 u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08)); 47 48 status->busy = !!(stat & 0x80000000); 49 status->faulted = !!(stat & 0x40000000); 50 status->next.tsg = !!(stat & 0x10000000); 51 status->next.id = (stat & 0x0fff0000) >> 16; 52 status->chsw = !!(stat & 0x00008000); 53 status->save = !!(stat & 0x00004000); 54 status->load = !!(stat & 0x00002000); 55 status->prev.tsg = !!(stat & 0x00001000); 56 status->prev.id = (stat & 0x00000fff); 57 status->chan = NULL; 58 59 if (status->busy && status->chsw) { 60 if (status->load && status->save) { 61 if (engine && nvkm_engine_chsw_load(engine)) 62 status->chan = &status->next; 63 else 64 status->chan = &status->prev; 65 } else 66 if (status->load) { 67 status->chan = &status->next; 68 } else { 69 status->chan = &status->prev; 70 } 71 } else 72 if (status->load) { 73 status->chan = &status->prev; 74 } 75 76 nvkm_debug(subdev, "engine %02d: busy %d faulted %d chsw %d " 77 "save %d load %d %sid %d%s-> %sid %d%s\n", 78 engn, status->busy, status->faulted, 79 status->chsw, status->save, status->load, 80 status->prev.tsg ? "tsg" : "ch", status->prev.id, 81 status->chan == &status->prev ? "*" : " ", 82 status->next.tsg ? "tsg" : "ch", status->next.id, 83 status->chan == &status->next ? "*" : " "); 84 } 85 86 int 87 gk104_fifo_class_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, 88 void *argv, u32 argc, struct nvkm_object **pobject) 89 { 90 struct gk104_fifo *fifo = gk104_fifo(base); 91 if (oclass->engn == &fifo->func->chan) { 92 const struct gk104_fifo_chan_user *user = oclass->engn; 93 return user->ctor(fifo, oclass, argv, argc, pobject); 94 } else 95 if (oclass->engn == &fifo->func->user) { 96 const struct gk104_fifo_user_user *user = oclass->engn; 97 return user->ctor(oclass, argv, argc, pobject); 98 } 99 WARN_ON(1); 100 return -EINVAL; 101 } 102 103 int 104 gk104_fifo_class_get(struct nvkm_fifo *base, int index, 105 struct nvkm_oclass *oclass) 106 { 107 struct gk104_fifo *fifo = gk104_fifo(base); 108 int c = 0; 109 110 if (fifo->func->user.ctor && c++ == index) { 111 oclass->base = fifo->func->user.user; 112 oclass->engn = &fifo->func->user; 113 return 0; 114 } 115 116 if (fifo->func->chan.ctor && c++ == index) { 117 oclass->base = fifo->func->chan.user; 118 oclass->engn = &fifo->func->chan; 119 return 0; 120 } 121 122 return c; 123 } 124 125 void 126 gk104_fifo_uevent_fini(struct nvkm_fifo *fifo) 127 { 128 struct nvkm_device *device = fifo->engine.subdev.device; 129 nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); 130 } 131 132 void 133 gk104_fifo_uevent_init(struct nvkm_fifo *fifo) 134 { 135 struct nvkm_device *device = fifo->engine.subdev.device; 136 nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); 137 } 138 139 void 140 gk104_fifo_runlist_commit(struct gk104_fifo *fifo, int runl, 141 struct nvkm_memory *mem, int nr) 142 { 143 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 144 struct nvkm_device *device = subdev->device; 145 int target; 146 147 switch (nvkm_memory_target(mem)) { 148 case NVKM_MEM_TARGET_VRAM: target = 0; break; 149 case NVKM_MEM_TARGET_NCOH: target = 3; break; 150 default: 151 WARN_ON(1); 152 return; 153 } 154 155 nvkm_wr32(device, 0x002270, (nvkm_memory_addr(mem) >> 12) | 156 (target << 28)); 157 nvkm_wr32(device, 0x002274, (runl << 20) | nr); 158 159 if (nvkm_msec(device, 2000, 160 if (!(nvkm_rd32(device, 0x002284 + (runl * 0x08)) & 0x00100000)) 161 break; 162 ) < 0) 163 nvkm_error(subdev, "runlist %d update timeout\n", runl); 164 } 165 166 void 167 gk104_fifo_runlist_update(struct gk104_fifo *fifo, int runl) 168 { 169 const struct gk104_fifo_runlist_func *func = fifo->func->runlist; 170 struct gk104_fifo_chan *chan; 171 struct nvkm_memory *mem; 172 struct nvkm_fifo_cgrp *cgrp; 173 int nr = 0; 174 175 mutex_lock(&fifo->base.mutex); 176 mem = fifo->runlist[runl].mem[fifo->runlist[runl].next]; 177 fifo->runlist[runl].next = !fifo->runlist[runl].next; 178 179 nvkm_kmap(mem); 180 list_for_each_entry(chan, &fifo->runlist[runl].chan, head) { 181 func->chan(chan, mem, nr++ * func->size); 182 } 183 184 list_for_each_entry(cgrp, &fifo->runlist[runl].cgrp, head) { 185 func->cgrp(cgrp, mem, nr++ * func->size); 186 list_for_each_entry(chan, &cgrp->chan, head) { 187 func->chan(chan, mem, nr++ * func->size); 188 } 189 } 190 nvkm_done(mem); 191 192 func->commit(fifo, runl, mem, nr); 193 mutex_unlock(&fifo->base.mutex); 194 } 195 196 void 197 gk104_fifo_runlist_remove(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan) 198 { 199 struct nvkm_fifo_cgrp *cgrp = chan->cgrp; 200 mutex_lock(&fifo->base.mutex); 201 if (!list_empty(&chan->head)) { 202 list_del_init(&chan->head); 203 if (cgrp && !--cgrp->chan_nr) 204 list_del_init(&cgrp->head); 205 } 206 mutex_unlock(&fifo->base.mutex); 207 } 208 209 void 210 gk104_fifo_runlist_insert(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan) 211 { 212 struct nvkm_fifo_cgrp *cgrp = chan->cgrp; 213 mutex_lock(&fifo->base.mutex); 214 if (cgrp) { 215 if (!cgrp->chan_nr++) 216 list_add_tail(&cgrp->head, &fifo->runlist[chan->runl].cgrp); 217 list_add_tail(&chan->head, &cgrp->chan); 218 } else { 219 list_add_tail(&chan->head, &fifo->runlist[chan->runl].chan); 220 } 221 mutex_unlock(&fifo->base.mutex); 222 } 223 224 void 225 gk104_fifo_runlist_chan(struct gk104_fifo_chan *chan, 226 struct nvkm_memory *memory, u32 offset) 227 { 228 nvkm_wo32(memory, offset + 0, chan->base.chid); 229 nvkm_wo32(memory, offset + 4, 0x00000000); 230 } 231 232 const struct gk104_fifo_runlist_func 233 gk104_fifo_runlist = { 234 .size = 8, 235 .chan = gk104_fifo_runlist_chan, 236 .commit = gk104_fifo_runlist_commit, 237 }; 238 239 void 240 gk104_fifo_pbdma_init(struct gk104_fifo *fifo) 241 { 242 struct nvkm_device *device = fifo->base.engine.subdev.device; 243 nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1); 244 } 245 246 int 247 gk104_fifo_pbdma_nr(struct gk104_fifo *fifo) 248 { 249 struct nvkm_device *device = fifo->base.engine.subdev.device; 250 /* Determine number of PBDMAs by checking valid enable bits. */ 251 nvkm_wr32(device, 0x000204, 0xffffffff); 252 return hweight32(nvkm_rd32(device, 0x000204)); 253 } 254 255 const struct gk104_fifo_pbdma_func 256 gk104_fifo_pbdma = { 257 .nr = gk104_fifo_pbdma_nr, 258 .init = gk104_fifo_pbdma_init, 259 }; 260 261 struct nvkm_engine * 262 gk104_fifo_id_engine(struct nvkm_fifo *base, int engi) 263 { 264 return gk104_fifo(base)->engine[engi].engine; 265 } 266 267 int 268 gk104_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine) 269 { 270 struct gk104_fifo *fifo = gk104_fifo(base); 271 int engn; 272 273 if (engine->subdev.type == NVKM_ENGINE_SW) 274 return GK104_FIFO_ENGN_SW; 275 276 for (engn = 0; engn < fifo->engine_nr && engine; engn++) { 277 if (fifo->engine[engn].engine == engine) 278 return engn; 279 } 280 281 WARN_ON(1); 282 return -1; 283 } 284 285 static void 286 gk104_fifo_recover_work(struct work_struct *w) 287 { 288 struct gk104_fifo *fifo = container_of(w, typeof(*fifo), recover.work); 289 struct nvkm_device *device = fifo->base.engine.subdev.device; 290 struct nvkm_engine *engine; 291 unsigned long flags; 292 u32 engm, runm, todo; 293 int engn, runl; 294 295 spin_lock_irqsave(&fifo->base.lock, flags); 296 runm = fifo->recover.runm; 297 engm = fifo->recover.engm; 298 fifo->recover.engm = 0; 299 fifo->recover.runm = 0; 300 spin_unlock_irqrestore(&fifo->base.lock, flags); 301 302 nvkm_mask(device, 0x002630, runm, runm); 303 304 for (todo = engm; engn = __ffs(todo), todo; todo &= ~BIT(engn)) { 305 if ((engine = fifo->engine[engn].engine)) { 306 nvkm_subdev_fini(&engine->subdev, false); 307 WARN_ON(nvkm_subdev_init(&engine->subdev)); 308 } 309 } 310 311 for (todo = runm; runl = __ffs(todo), todo; todo &= ~BIT(runl)) 312 gk104_fifo_runlist_update(fifo, runl); 313 314 nvkm_wr32(device, 0x00262c, runm); 315 nvkm_mask(device, 0x002630, runm, 0x00000000); 316 } 317 318 static void gk104_fifo_recover_engn(struct gk104_fifo *fifo, int engn); 319 320 static void 321 gk104_fifo_recover_runl(struct gk104_fifo *fifo, int runl) 322 { 323 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 324 struct nvkm_device *device = subdev->device; 325 const u32 runm = BIT(runl); 326 327 assert_spin_locked(&fifo->base.lock); 328 if (fifo->recover.runm & runm) 329 return; 330 fifo->recover.runm |= runm; 331 332 /* Block runlist to prevent channel assignment(s) from changing. */ 333 nvkm_mask(device, 0x002630, runm, runm); 334 335 /* Schedule recovery. */ 336 nvkm_warn(subdev, "runlist %d: scheduled for recovery\n", runl); 337 schedule_work(&fifo->recover.work); 338 } 339 340 static struct gk104_fifo_chan * 341 gk104_fifo_recover_chid(struct gk104_fifo *fifo, int runl, int chid) 342 { 343 struct gk104_fifo_chan *chan; 344 struct nvkm_fifo_cgrp *cgrp; 345 346 list_for_each_entry(chan, &fifo->runlist[runl].chan, head) { 347 if (chan->base.chid == chid) { 348 list_del_init(&chan->head); 349 return chan; 350 } 351 } 352 353 list_for_each_entry(cgrp, &fifo->runlist[runl].cgrp, head) { 354 if (cgrp->id == chid) { 355 chan = list_first_entry(&cgrp->chan, typeof(*chan), head); 356 list_del_init(&chan->head); 357 if (!--cgrp->chan_nr) 358 list_del_init(&cgrp->head); 359 return chan; 360 } 361 } 362 363 return NULL; 364 } 365 366 static void 367 gk104_fifo_recover_chan(struct nvkm_fifo *base, int chid) 368 { 369 struct gk104_fifo *fifo = gk104_fifo(base); 370 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 371 struct nvkm_device *device = subdev->device; 372 const u32 stat = nvkm_rd32(device, 0x800004 + (chid * 0x08)); 373 const u32 runl = (stat & 0x000f0000) >> 16; 374 const bool used = (stat & 0x00000001); 375 unsigned long engn, engm = fifo->runlist[runl].engm; 376 struct gk104_fifo_chan *chan; 377 378 assert_spin_locked(&fifo->base.lock); 379 if (!used) 380 return; 381 382 /* Lookup SW state for channel, and mark it as dead. */ 383 chan = gk104_fifo_recover_chid(fifo, runl, chid); 384 if (chan) { 385 chan->killed = true; 386 nvkm_fifo_kevent(&fifo->base, chid); 387 } 388 389 /* Disable channel. */ 390 nvkm_wr32(device, 0x800004 + (chid * 0x08), stat | 0x00000800); 391 nvkm_warn(subdev, "channel %d: killed\n", chid); 392 393 /* Block channel assignments from changing during recovery. */ 394 gk104_fifo_recover_runl(fifo, runl); 395 396 /* Schedule recovery for any engines the channel is on. */ 397 for_each_set_bit(engn, &engm, fifo->engine_nr) { 398 struct gk104_fifo_engine_status status; 399 gk104_fifo_engine_status(fifo, engn, &status); 400 if (!status.chan || status.chan->id != chid) 401 continue; 402 gk104_fifo_recover_engn(fifo, engn); 403 } 404 } 405 406 static void 407 gk104_fifo_recover_engn(struct gk104_fifo *fifo, int engn) 408 { 409 struct nvkm_engine *engine = fifo->engine[engn].engine; 410 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 411 struct nvkm_device *device = subdev->device; 412 const u32 runl = fifo->engine[engn].runl; 413 const u32 engm = BIT(engn); 414 struct gk104_fifo_engine_status status; 415 int mmui = -1; 416 417 assert_spin_locked(&fifo->base.lock); 418 if (fifo->recover.engm & engm) 419 return; 420 fifo->recover.engm |= engm; 421 422 /* Block channel assignments from changing during recovery. */ 423 gk104_fifo_recover_runl(fifo, runl); 424 425 /* Determine which channel (if any) is currently on the engine. */ 426 gk104_fifo_engine_status(fifo, engn, &status); 427 if (status.chan) { 428 /* The channel is not longer viable, kill it. */ 429 gk104_fifo_recover_chan(&fifo->base, status.chan->id); 430 } 431 432 /* Determine MMU fault ID for the engine, if we're not being 433 * called from the fault handler already. 434 */ 435 if (!status.faulted && engine) { 436 mmui = nvkm_top_fault_id(device, engine->subdev.type, engine->subdev.inst); 437 if (mmui < 0) { 438 const struct nvkm_enum *en = fifo->func->fault.engine; 439 for (; en && en->name; en++) { 440 if (en->data2 == engine->subdev.type && 441 en->inst == engine->subdev.inst) { 442 mmui = en->value; 443 break; 444 } 445 } 446 } 447 WARN_ON(mmui < 0); 448 } 449 450 /* Trigger a MMU fault for the engine. 451 * 452 * No good idea why this is needed, but nvgpu does something similar, 453 * and it makes recovery from CTXSW_TIMEOUT a lot more reliable. 454 */ 455 if (mmui >= 0) { 456 nvkm_wr32(device, 0x002a30 + (engn * 0x04), 0x00000100 | mmui); 457 458 /* Wait for fault to trigger. */ 459 nvkm_msec(device, 2000, 460 gk104_fifo_engine_status(fifo, engn, &status); 461 if (status.faulted) 462 break; 463 ); 464 465 /* Release MMU fault trigger, and ACK the fault. */ 466 nvkm_wr32(device, 0x002a30 + (engn * 0x04), 0x00000000); 467 nvkm_wr32(device, 0x00259c, BIT(mmui)); 468 nvkm_wr32(device, 0x002100, 0x10000000); 469 } 470 471 /* Schedule recovery. */ 472 nvkm_warn(subdev, "engine %d: scheduled for recovery\n", engn); 473 schedule_work(&fifo->recover.work); 474 } 475 476 static void 477 gk104_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) 478 { 479 struct gk104_fifo *fifo = gk104_fifo(base); 480 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 481 struct nvkm_device *device = subdev->device; 482 const struct nvkm_enum *er, *ee, *ec, *ea; 483 struct nvkm_engine *engine = NULL; 484 struct nvkm_fifo_chan *chan; 485 unsigned long flags; 486 const char *en = ""; 487 char ct[8] = "HUB/"; 488 489 er = nvkm_enum_find(fifo->func->fault.reason, info->reason); 490 ee = nvkm_enum_find(fifo->func->fault.engine, info->engine); 491 if (info->hub) { 492 ec = nvkm_enum_find(fifo->func->fault.hubclient, info->client); 493 } else { 494 ec = nvkm_enum_find(fifo->func->fault.gpcclient, info->client); 495 snprintf(ct, sizeof(ct), "GPC%d/", info->gpc); 496 } 497 ea = nvkm_enum_find(fifo->func->fault.access, info->access); 498 499 if (ee && ee->data2) { 500 switch (ee->data2) { 501 case NVKM_SUBDEV_BAR: 502 nvkm_bar_bar1_reset(device); 503 break; 504 case NVKM_SUBDEV_INSTMEM: 505 nvkm_bar_bar2_reset(device); 506 break; 507 case NVKM_ENGINE_IFB: 508 nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); 509 break; 510 default: 511 engine = nvkm_device_engine(device, ee->data2, 0); 512 break; 513 } 514 } 515 516 if (ee == NULL) { 517 struct nvkm_subdev *subdev = nvkm_top_fault(device, info->engine); 518 if (subdev) { 519 if (subdev->func == &nvkm_engine) 520 engine = container_of(subdev, typeof(*engine), subdev); 521 en = engine->subdev.name; 522 } 523 } else { 524 en = ee->name; 525 } 526 527 spin_lock_irqsave(&fifo->base.lock, flags); 528 chan = nvkm_fifo_chan_inst_locked(&fifo->base, info->inst); 529 530 nvkm_error(subdev, 531 "fault %02x [%s] at %016llx engine %02x [%s] client %02x " 532 "[%s%s] reason %02x [%s] on channel %d [%010llx %s]\n", 533 info->access, ea ? ea->name : "", info->addr, 534 info->engine, ee ? ee->name : en, 535 info->client, ct, ec ? ec->name : "", 536 info->reason, er ? er->name : "", chan ? chan->chid : -1, 537 info->inst, chan ? chan->object.client->name : "unknown"); 538 539 /* Kill the channel that caused the fault. */ 540 if (chan) 541 gk104_fifo_recover_chan(&fifo->base, chan->chid); 542 543 /* Channel recovery will probably have already done this for the 544 * correct engine(s), but just in case we can't find the channel 545 * information... 546 */ 547 if (engine) { 548 int engn = fifo->base.func->engine_id(&fifo->base, engine); 549 if (engn >= 0 && engn != GK104_FIFO_ENGN_SW) 550 gk104_fifo_recover_engn(fifo, engn); 551 } 552 553 spin_unlock_irqrestore(&fifo->base.lock, flags); 554 } 555 556 static const struct nvkm_enum 557 gk104_fifo_bind_reason[] = { 558 { 0x01, "BIND_NOT_UNBOUND" }, 559 { 0x02, "SNOOP_WITHOUT_BAR1" }, 560 { 0x03, "UNBIND_WHILE_RUNNING" }, 561 { 0x05, "INVALID_RUNLIST" }, 562 { 0x06, "INVALID_CTX_TGT" }, 563 { 0x0b, "UNBIND_WHILE_PARKED" }, 564 {} 565 }; 566 567 void 568 gk104_fifo_intr_bind(struct gk104_fifo *fifo) 569 { 570 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 571 struct nvkm_device *device = subdev->device; 572 u32 intr = nvkm_rd32(device, 0x00252c); 573 u32 code = intr & 0x000000ff; 574 const struct nvkm_enum *en = 575 nvkm_enum_find(gk104_fifo_bind_reason, code); 576 577 nvkm_error(subdev, "BIND_ERROR %02x [%s]\n", code, en ? en->name : ""); 578 } 579 580 static const struct nvkm_enum 581 gk104_fifo_sched_reason[] = { 582 { 0x0a, "CTXSW_TIMEOUT" }, 583 {} 584 }; 585 586 static void 587 gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) 588 { 589 struct nvkm_device *device = fifo->base.engine.subdev.device; 590 unsigned long flags, engm = 0; 591 u32 engn; 592 593 /* We need to ACK the SCHED_ERROR here, and prevent it reasserting, 594 * as MMU_FAULT cannot be triggered while it's pending. 595 */ 596 spin_lock_irqsave(&fifo->base.lock, flags); 597 nvkm_mask(device, 0x002140, 0x00000100, 0x00000000); 598 nvkm_wr32(device, 0x002100, 0x00000100); 599 600 for (engn = 0; engn < fifo->engine_nr; engn++) { 601 struct gk104_fifo_engine_status status; 602 603 gk104_fifo_engine_status(fifo, engn, &status); 604 if (!status.busy || !status.chsw) 605 continue; 606 607 engm |= BIT(engn); 608 } 609 610 for_each_set_bit(engn, &engm, fifo->engine_nr) 611 gk104_fifo_recover_engn(fifo, engn); 612 613 nvkm_mask(device, 0x002140, 0x00000100, 0x00000100); 614 spin_unlock_irqrestore(&fifo->base.lock, flags); 615 } 616 617 static void 618 gk104_fifo_intr_sched(struct gk104_fifo *fifo) 619 { 620 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 621 struct nvkm_device *device = subdev->device; 622 u32 intr = nvkm_rd32(device, 0x00254c); 623 u32 code = intr & 0x000000ff; 624 const struct nvkm_enum *en = 625 nvkm_enum_find(gk104_fifo_sched_reason, code); 626 627 nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : ""); 628 629 switch (code) { 630 case 0x0a: 631 gk104_fifo_intr_sched_ctxsw(fifo); 632 break; 633 default: 634 break; 635 } 636 } 637 638 void 639 gk104_fifo_intr_chsw(struct gk104_fifo *fifo) 640 { 641 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 642 struct nvkm_device *device = subdev->device; 643 u32 stat = nvkm_rd32(device, 0x00256c); 644 nvkm_error(subdev, "CHSW_ERROR %08x\n", stat); 645 nvkm_wr32(device, 0x00256c, stat); 646 } 647 648 void 649 gk104_fifo_intr_dropped_fault(struct gk104_fifo *fifo) 650 { 651 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 652 struct nvkm_device *device = subdev->device; 653 u32 stat = nvkm_rd32(device, 0x00259c); 654 nvkm_error(subdev, "DROPPED_MMU_FAULT %08x\n", stat); 655 } 656 657 static const struct nvkm_bitfield gk104_fifo_pbdma_intr_0[] = { 658 { 0x00000001, "MEMREQ" }, 659 { 0x00000002, "MEMACK_TIMEOUT" }, 660 { 0x00000004, "MEMACK_EXTRA" }, 661 { 0x00000008, "MEMDAT_TIMEOUT" }, 662 { 0x00000010, "MEMDAT_EXTRA" }, 663 { 0x00000020, "MEMFLUSH" }, 664 { 0x00000040, "MEMOP" }, 665 { 0x00000080, "LBCONNECT" }, 666 { 0x00000100, "LBREQ" }, 667 { 0x00000200, "LBACK_TIMEOUT" }, 668 { 0x00000400, "LBACK_EXTRA" }, 669 { 0x00000800, "LBDAT_TIMEOUT" }, 670 { 0x00001000, "LBDAT_EXTRA" }, 671 { 0x00002000, "GPFIFO" }, 672 { 0x00004000, "GPPTR" }, 673 { 0x00008000, "GPENTRY" }, 674 { 0x00010000, "GPCRC" }, 675 { 0x00020000, "PBPTR" }, 676 { 0x00040000, "PBENTRY" }, 677 { 0x00080000, "PBCRC" }, 678 { 0x00100000, "XBARCONNECT" }, 679 { 0x00200000, "METHOD" }, 680 { 0x00400000, "METHODCRC" }, 681 { 0x00800000, "DEVICE" }, 682 { 0x02000000, "SEMAPHORE" }, 683 { 0x04000000, "ACQUIRE" }, 684 { 0x08000000, "PRI" }, 685 { 0x20000000, "NO_CTXSW_SEG" }, 686 { 0x40000000, "PBSEG" }, 687 { 0x80000000, "SIGNATURE" }, 688 {} 689 }; 690 691 void 692 gk104_fifo_intr_pbdma_0(struct gk104_fifo *fifo, int unit) 693 { 694 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 695 struct nvkm_device *device = subdev->device; 696 u32 mask = nvkm_rd32(device, 0x04010c + (unit * 0x2000)); 697 u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000)) & mask; 698 u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000)); 699 u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000)); 700 u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0xfff; 701 u32 subc = (addr & 0x00070000) >> 16; 702 u32 mthd = (addr & 0x00003ffc); 703 u32 show = stat; 704 struct nvkm_fifo_chan *chan; 705 unsigned long flags; 706 char msg[128]; 707 708 if (stat & 0x00800000) { 709 if (device->sw) { 710 if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data)) 711 show &= ~0x00800000; 712 } 713 } 714 715 nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008); 716 717 if (show) { 718 nvkm_snprintbf(msg, sizeof(msg), gk104_fifo_pbdma_intr_0, show); 719 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); 720 nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%010llx %s] " 721 "subc %d mthd %04x data %08x\n", 722 unit, show, msg, chid, chan ? chan->inst->addr : 0, 723 chan ? chan->object.client->name : "unknown", 724 subc, mthd, data); 725 nvkm_fifo_chan_put(&fifo->base, flags, &chan); 726 } 727 728 nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat); 729 } 730 731 static const struct nvkm_bitfield gk104_fifo_pbdma_intr_1[] = { 732 { 0x00000001, "HCE_RE_ILLEGAL_OP" }, 733 { 0x00000002, "HCE_RE_ALIGNB" }, 734 { 0x00000004, "HCE_PRIV" }, 735 { 0x00000008, "HCE_ILLEGAL_MTHD" }, 736 { 0x00000010, "HCE_ILLEGAL_CLASS" }, 737 {} 738 }; 739 740 void 741 gk104_fifo_intr_pbdma_1(struct gk104_fifo *fifo, int unit) 742 { 743 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 744 struct nvkm_device *device = subdev->device; 745 u32 mask = nvkm_rd32(device, 0x04014c + (unit * 0x2000)); 746 u32 stat = nvkm_rd32(device, 0x040148 + (unit * 0x2000)) & mask; 747 u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0xfff; 748 char msg[128]; 749 750 if (stat) { 751 nvkm_snprintbf(msg, sizeof(msg), gk104_fifo_pbdma_intr_1, stat); 752 nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d %08x %08x\n", 753 unit, stat, msg, chid, 754 nvkm_rd32(device, 0x040150 + (unit * 0x2000)), 755 nvkm_rd32(device, 0x040154 + (unit * 0x2000))); 756 } 757 758 nvkm_wr32(device, 0x040148 + (unit * 0x2000), stat); 759 } 760 761 void 762 gk104_fifo_intr_runlist(struct gk104_fifo *fifo) 763 { 764 struct nvkm_device *device = fifo->base.engine.subdev.device; 765 u32 mask = nvkm_rd32(device, 0x002a00); 766 while (mask) { 767 int runl = __ffs(mask); 768 wake_up(&fifo->runlist[runl].wait); 769 nvkm_wr32(device, 0x002a00, 1 << runl); 770 mask &= ~(1 << runl); 771 } 772 } 773 774 void 775 gk104_fifo_intr_engine(struct gk104_fifo *fifo) 776 { 777 nvkm_fifo_uevent(&fifo->base); 778 } 779 780 static void 781 gk104_fifo_intr(struct nvkm_fifo *base) 782 { 783 struct gk104_fifo *fifo = gk104_fifo(base); 784 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 785 struct nvkm_device *device = subdev->device; 786 u32 mask = nvkm_rd32(device, 0x002140); 787 u32 stat = nvkm_rd32(device, 0x002100) & mask; 788 789 if (stat & 0x00000001) { 790 gk104_fifo_intr_bind(fifo); 791 nvkm_wr32(device, 0x002100, 0x00000001); 792 stat &= ~0x00000001; 793 } 794 795 if (stat & 0x00000010) { 796 nvkm_error(subdev, "PIO_ERROR\n"); 797 nvkm_wr32(device, 0x002100, 0x00000010); 798 stat &= ~0x00000010; 799 } 800 801 if (stat & 0x00000100) { 802 gk104_fifo_intr_sched(fifo); 803 nvkm_wr32(device, 0x002100, 0x00000100); 804 stat &= ~0x00000100; 805 } 806 807 if (stat & 0x00010000) { 808 gk104_fifo_intr_chsw(fifo); 809 nvkm_wr32(device, 0x002100, 0x00010000); 810 stat &= ~0x00010000; 811 } 812 813 if (stat & 0x00800000) { 814 nvkm_error(subdev, "FB_FLUSH_TIMEOUT\n"); 815 nvkm_wr32(device, 0x002100, 0x00800000); 816 stat &= ~0x00800000; 817 } 818 819 if (stat & 0x01000000) { 820 nvkm_error(subdev, "LB_ERROR\n"); 821 nvkm_wr32(device, 0x002100, 0x01000000); 822 stat &= ~0x01000000; 823 } 824 825 if (stat & 0x08000000) { 826 gk104_fifo_intr_dropped_fault(fifo); 827 nvkm_wr32(device, 0x002100, 0x08000000); 828 stat &= ~0x08000000; 829 } 830 831 if (stat & 0x10000000) { 832 u32 mask = nvkm_rd32(device, 0x00259c); 833 while (mask) { 834 u32 unit = __ffs(mask); 835 fifo->func->intr.fault(&fifo->base, unit); 836 nvkm_wr32(device, 0x00259c, (1 << unit)); 837 mask &= ~(1 << unit); 838 } 839 stat &= ~0x10000000; 840 } 841 842 if (stat & 0x20000000) { 843 u32 mask = nvkm_rd32(device, 0x0025a0); 844 while (mask) { 845 u32 unit = __ffs(mask); 846 gk104_fifo_intr_pbdma_0(fifo, unit); 847 gk104_fifo_intr_pbdma_1(fifo, unit); 848 nvkm_wr32(device, 0x0025a0, (1 << unit)); 849 mask &= ~(1 << unit); 850 } 851 stat &= ~0x20000000; 852 } 853 854 if (stat & 0x40000000) { 855 gk104_fifo_intr_runlist(fifo); 856 stat &= ~0x40000000; 857 } 858 859 if (stat & 0x80000000) { 860 nvkm_wr32(device, 0x002100, 0x80000000); 861 gk104_fifo_intr_engine(fifo); 862 stat &= ~0x80000000; 863 } 864 865 if (stat) { 866 nvkm_error(subdev, "INTR %08x\n", stat); 867 nvkm_mask(device, 0x002140, stat, 0x00000000); 868 nvkm_wr32(device, 0x002100, stat); 869 } 870 } 871 872 void 873 gk104_fifo_fini(struct nvkm_fifo *base) 874 { 875 struct gk104_fifo *fifo = gk104_fifo(base); 876 struct nvkm_device *device = fifo->base.engine.subdev.device; 877 flush_work(&fifo->recover.work); 878 /* allow mmu fault interrupts, even when we're not using fifo */ 879 nvkm_mask(device, 0x002140, 0x10000000, 0x10000000); 880 } 881 882 int 883 gk104_fifo_info(struct nvkm_fifo *base, u64 mthd, u64 *data) 884 { 885 struct gk104_fifo *fifo = gk104_fifo(base); 886 switch (mthd) { 887 case NV_DEVICE_HOST_RUNLISTS: 888 *data = (1ULL << fifo->runlist_nr) - 1; 889 return 0; 890 case NV_DEVICE_HOST_RUNLIST_ENGINES: { 891 if (*data < fifo->runlist_nr) { 892 unsigned long engm = fifo->runlist[*data].engm; 893 struct nvkm_engine *engine; 894 int engn; 895 *data = 0; 896 for_each_set_bit(engn, &engm, fifo->engine_nr) { 897 if ((engine = fifo->engine[engn].engine)) { 898 #define CASE(n) case NVKM_ENGINE_##n: *data |= NV_DEVICE_HOST_RUNLIST_ENGINES_##n; break 899 switch (engine->subdev.type) { 900 CASE(SW ); 901 CASE(GR ); 902 CASE(MPEG ); 903 CASE(ME ); 904 CASE(CIPHER); 905 CASE(BSP ); 906 CASE(VP ); 907 CASE(CE ); 908 CASE(SEC ); 909 CASE(MSVLD ); 910 CASE(MSPDEC); 911 CASE(MSPPP ); 912 CASE(MSENC ); 913 CASE(VIC ); 914 CASE(SEC2 ); 915 CASE(NVDEC ); 916 CASE(NVENC ); 917 default: 918 WARN_ON(1); 919 break; 920 } 921 } 922 } 923 return 0; 924 } 925 } 926 return -EINVAL; 927 default: 928 return -EINVAL; 929 } 930 } 931 932 int 933 gk104_fifo_oneinit(struct nvkm_fifo *base) 934 { 935 struct gk104_fifo *fifo = gk104_fifo(base); 936 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 937 struct nvkm_device *device = subdev->device; 938 struct nvkm_vmm *bar = nvkm_bar_bar1_vmm(device); 939 struct nvkm_top_device *tdev; 940 int pbid, ret, i, j; 941 u32 *map; 942 943 fifo->pbdma_nr = fifo->func->pbdma->nr(fifo); 944 nvkm_debug(subdev, "%d PBDMA(s)\n", fifo->pbdma_nr); 945 946 /* Read PBDMA->runlist(s) mapping from HW. */ 947 if (!(map = kcalloc(fifo->pbdma_nr, sizeof(*map), GFP_KERNEL))) 948 return -ENOMEM; 949 950 for (i = 0; i < fifo->pbdma_nr; i++) 951 map[i] = nvkm_rd32(device, 0x002390 + (i * 0x04)); 952 953 /* Determine runlist configuration from topology device info. */ 954 list_for_each_entry(tdev, &device->top->device, head) { 955 const int engn = tdev->engine; 956 char _en[16], *en; 957 958 if (engn < 0) 959 continue; 960 961 /* Determine which PBDMA handles requests for this engine. */ 962 for (j = 0, pbid = -1; j < fifo->pbdma_nr; j++) { 963 if (map[j] & BIT(tdev->runlist)) { 964 pbid = j; 965 break; 966 } 967 } 968 969 fifo->engine[engn].engine = nvkm_device_engine(device, tdev->type, tdev->inst); 970 if (!fifo->engine[engn].engine) { 971 snprintf(_en, sizeof(_en), "%s, %d", 972 nvkm_subdev_type[tdev->type], tdev->inst); 973 en = _en; 974 } else { 975 en = fifo->engine[engn].engine->subdev.name; 976 } 977 978 nvkm_debug(subdev, "engine %2d: runlist %2d pbdma %2d (%s)\n", 979 tdev->engine, tdev->runlist, pbid, en); 980 981 fifo->engine[engn].runl = tdev->runlist; 982 fifo->engine[engn].pbid = pbid; 983 fifo->engine_nr = max(fifo->engine_nr, engn + 1); 984 fifo->runlist[tdev->runlist].engm |= BIT(engn); 985 fifo->runlist[tdev->runlist].engm_sw |= BIT(engn); 986 if (tdev->type == NVKM_ENGINE_GR) 987 fifo->runlist[tdev->runlist].engm_sw |= BIT(GK104_FIFO_ENGN_SW); 988 fifo->runlist_nr = max(fifo->runlist_nr, tdev->runlist + 1); 989 } 990 991 kfree(map); 992 993 for (i = 0; i < fifo->runlist_nr; i++) { 994 for (j = 0; j < ARRAY_SIZE(fifo->runlist[i].mem); j++) { 995 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 996 fifo->base.nr * 2/* TSG+chan */ * 997 fifo->func->runlist->size, 998 0x1000, false, 999 &fifo->runlist[i].mem[j]); 1000 if (ret) 1001 return ret; 1002 } 1003 1004 init_waitqueue_head(&fifo->runlist[i].wait); 1005 INIT_LIST_HEAD(&fifo->runlist[i].cgrp); 1006 INIT_LIST_HEAD(&fifo->runlist[i].chan); 1007 } 1008 1009 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 1010 fifo->base.nr * 0x200, 0x1000, true, 1011 &fifo->user.mem); 1012 if (ret) 1013 return ret; 1014 1015 ret = nvkm_vmm_get(bar, 12, nvkm_memory_size(fifo->user.mem), 1016 &fifo->user.bar); 1017 if (ret) 1018 return ret; 1019 1020 return nvkm_memory_map(fifo->user.mem, 0, bar, fifo->user.bar, NULL, 0); 1021 } 1022 1023 void 1024 gk104_fifo_init(struct nvkm_fifo *base) 1025 { 1026 struct gk104_fifo *fifo = gk104_fifo(base); 1027 struct nvkm_device *device = fifo->base.engine.subdev.device; 1028 int i; 1029 1030 /* Enable PBDMAs. */ 1031 fifo->func->pbdma->init(fifo); 1032 1033 /* PBDMA[n] */ 1034 for (i = 0; i < fifo->pbdma_nr; i++) { 1035 nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); 1036 nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ 1037 nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ 1038 } 1039 1040 /* PBDMA[n].HCE */ 1041 for (i = 0; i < fifo->pbdma_nr; i++) { 1042 nvkm_wr32(device, 0x040148 + (i * 0x2000), 0xffffffff); /* INTR */ 1043 nvkm_wr32(device, 0x04014c + (i * 0x2000), 0xffffffff); /* INTREN */ 1044 } 1045 1046 nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar->addr >> 12); 1047 1048 if (fifo->func->pbdma->init_timeout) 1049 fifo->func->pbdma->init_timeout(fifo); 1050 1051 nvkm_wr32(device, 0x002100, 0xffffffff); 1052 nvkm_wr32(device, 0x002140, 0x7fffffff); 1053 } 1054 1055 void * 1056 gk104_fifo_dtor(struct nvkm_fifo *base) 1057 { 1058 struct gk104_fifo *fifo = gk104_fifo(base); 1059 struct nvkm_device *device = fifo->base.engine.subdev.device; 1060 int i; 1061 1062 nvkm_vmm_put(nvkm_bar_bar1_vmm(device), &fifo->user.bar); 1063 nvkm_memory_unref(&fifo->user.mem); 1064 1065 for (i = 0; i < fifo->runlist_nr; i++) { 1066 nvkm_memory_unref(&fifo->runlist[i].mem[1]); 1067 nvkm_memory_unref(&fifo->runlist[i].mem[0]); 1068 } 1069 1070 return fifo; 1071 } 1072 1073 static const struct nvkm_fifo_func 1074 gk104_fifo_ = { 1075 .dtor = gk104_fifo_dtor, 1076 .oneinit = gk104_fifo_oneinit, 1077 .info = gk104_fifo_info, 1078 .init = gk104_fifo_init, 1079 .fini = gk104_fifo_fini, 1080 .intr = gk104_fifo_intr, 1081 .fault = gk104_fifo_fault, 1082 .engine_id = gk104_fifo_engine_id, 1083 .id_engine = gk104_fifo_id_engine, 1084 .uevent_init = gk104_fifo_uevent_init, 1085 .uevent_fini = gk104_fifo_uevent_fini, 1086 .recover_chan = gk104_fifo_recover_chan, 1087 .class_get = gk104_fifo_class_get, 1088 .class_new = gk104_fifo_class_new, 1089 }; 1090 1091 int 1092 gk104_fifo_new_(const struct gk104_fifo_func *func, struct nvkm_device *device, 1093 enum nvkm_subdev_type type, int inst, int nr, struct nvkm_fifo **pfifo) 1094 { 1095 struct gk104_fifo *fifo; 1096 1097 if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL))) 1098 return -ENOMEM; 1099 fifo->func = func; 1100 INIT_WORK(&fifo->recover.work, gk104_fifo_recover_work); 1101 *pfifo = &fifo->base; 1102 1103 return nvkm_fifo_ctor(&gk104_fifo_, device, type, inst, nr, &fifo->base); 1104 } 1105 1106 const struct nvkm_enum 1107 gk104_fifo_fault_access[] = { 1108 { 0x0, "READ" }, 1109 { 0x1, "WRITE" }, 1110 {} 1111 }; 1112 1113 const struct nvkm_enum 1114 gk104_fifo_fault_engine[] = { 1115 { 0x00, "GR", NULL, NVKM_ENGINE_GR }, 1116 { 0x01, "DISPLAY" }, 1117 { 0x02, "CAPTURE" }, 1118 { 0x03, "IFB", NULL, NVKM_ENGINE_IFB }, 1119 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, 1120 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM }, 1121 { 0x06, "SCHED" }, 1122 { 0x07, "HOST0", NULL, NVKM_ENGINE_FIFO }, 1123 { 0x08, "HOST1", NULL, NVKM_ENGINE_FIFO }, 1124 { 0x09, "HOST2", NULL, NVKM_ENGINE_FIFO }, 1125 { 0x0a, "HOST3", NULL, NVKM_ENGINE_FIFO }, 1126 { 0x0b, "HOST4", NULL, NVKM_ENGINE_FIFO }, 1127 { 0x0c, "HOST5", NULL, NVKM_ENGINE_FIFO }, 1128 { 0x0d, "HOST6", NULL, NVKM_ENGINE_FIFO }, 1129 { 0x0e, "HOST7", NULL, NVKM_ENGINE_FIFO }, 1130 { 0x0f, "HOSTSR" }, 1131 { 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD }, 1132 { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP }, 1133 { 0x13, "PERF" }, 1134 { 0x14, "MSPDEC", NULL, NVKM_ENGINE_MSPDEC }, 1135 { 0x15, "CE0", NULL, NVKM_ENGINE_CE, 0 }, 1136 { 0x16, "CE1", NULL, NVKM_ENGINE_CE, 1 }, 1137 { 0x17, "PMU" }, 1138 { 0x18, "PTP" }, 1139 { 0x19, "MSENC", NULL, NVKM_ENGINE_MSENC }, 1140 { 0x1b, "CE2", NULL, NVKM_ENGINE_CE, 2 }, 1141 {} 1142 }; 1143 1144 const struct nvkm_enum 1145 gk104_fifo_fault_reason[] = { 1146 { 0x00, "PDE" }, 1147 { 0x01, "PDE_SIZE" }, 1148 { 0x02, "PTE" }, 1149 { 0x03, "VA_LIMIT_VIOLATION" }, 1150 { 0x04, "UNBOUND_INST_BLOCK" }, 1151 { 0x05, "PRIV_VIOLATION" }, 1152 { 0x06, "RO_VIOLATION" }, 1153 { 0x07, "WO_VIOLATION" }, 1154 { 0x08, "PITCH_MASK_VIOLATION" }, 1155 { 0x09, "WORK_CREATION" }, 1156 { 0x0a, "UNSUPPORTED_APERTURE" }, 1157 { 0x0b, "COMPRESSION_FAILURE" }, 1158 { 0x0c, "UNSUPPORTED_KIND" }, 1159 { 0x0d, "REGION_VIOLATION" }, 1160 { 0x0e, "BOTH_PTES_VALID" }, 1161 { 0x0f, "INFO_TYPE_POISONED" }, 1162 {} 1163 }; 1164 1165 const struct nvkm_enum 1166 gk104_fifo_fault_hubclient[] = { 1167 { 0x00, "VIP" }, 1168 { 0x01, "CE0" }, 1169 { 0x02, "CE1" }, 1170 { 0x03, "DNISO" }, 1171 { 0x04, "FE" }, 1172 { 0x05, "FECS" }, 1173 { 0x06, "HOST" }, 1174 { 0x07, "HOST_CPU" }, 1175 { 0x08, "HOST_CPU_NB" }, 1176 { 0x09, "ISO" }, 1177 { 0x0a, "MMU" }, 1178 { 0x0b, "MSPDEC" }, 1179 { 0x0c, "MSPPP" }, 1180 { 0x0d, "MSVLD" }, 1181 { 0x0e, "NISO" }, 1182 { 0x0f, "P2P" }, 1183 { 0x10, "PD" }, 1184 { 0x11, "PERF" }, 1185 { 0x12, "PMU" }, 1186 { 0x13, "RASTERTWOD" }, 1187 { 0x14, "SCC" }, 1188 { 0x15, "SCC_NB" }, 1189 { 0x16, "SEC" }, 1190 { 0x17, "SSYNC" }, 1191 { 0x18, "GR_CE" }, 1192 { 0x19, "CE2" }, 1193 { 0x1a, "XV" }, 1194 { 0x1b, "MMU_NB" }, 1195 { 0x1c, "MSENC" }, 1196 { 0x1d, "DFALCON" }, 1197 { 0x1e, "SKED" }, 1198 { 0x1f, "AFALCON" }, 1199 {} 1200 }; 1201 1202 const struct nvkm_enum 1203 gk104_fifo_fault_gpcclient[] = { 1204 { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" }, 1205 { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" }, 1206 { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" }, 1207 { 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" }, 1208 { 0x0c, "RAST" }, 1209 { 0x0d, "GCC" }, 1210 { 0x0e, "GPCCS" }, 1211 { 0x0f, "PROP_0" }, 1212 { 0x10, "PROP_1" }, 1213 { 0x11, "PROP_2" }, 1214 { 0x12, "PROP_3" }, 1215 { 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" }, 1216 { 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" }, 1217 { 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" }, 1218 { 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" }, 1219 { 0x1f, "GPM" }, 1220 { 0x20, "LTP_UTLB_0" }, 1221 { 0x21, "LTP_UTLB_1" }, 1222 { 0x22, "LTP_UTLB_2" }, 1223 { 0x23, "LTP_UTLB_3" }, 1224 { 0x24, "GPC_RGG_UTLB" }, 1225 {} 1226 }; 1227 1228 static const struct gk104_fifo_func 1229 gk104_fifo = { 1230 .intr.fault = gf100_fifo_intr_fault, 1231 .pbdma = &gk104_fifo_pbdma, 1232 .fault.access = gk104_fifo_fault_access, 1233 .fault.engine = gk104_fifo_fault_engine, 1234 .fault.reason = gk104_fifo_fault_reason, 1235 .fault.hubclient = gk104_fifo_fault_hubclient, 1236 .fault.gpcclient = gk104_fifo_fault_gpcclient, 1237 .runlist = &gk104_fifo_runlist, 1238 .chan = {{0,0,KEPLER_CHANNEL_GPFIFO_A}, gk104_fifo_gpfifo_new }, 1239 }; 1240 1241 int 1242 gk104_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 1243 struct nvkm_fifo **pfifo) 1244 { 1245 return gk104_fifo_new_(&gk104_fifo, device, type, inst, 4096, pfifo); 1246 } 1247