1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "gk104.h" 25 #include "cgrp.h" 26 #include "changk104.h" 27 28 #include <core/client.h> 29 #include <core/gpuobj.h> 30 #include <subdev/bar.h> 31 #include <subdev/fault.h> 32 #include <subdev/timer.h> 33 #include <subdev/top.h> 34 #include <engine/sw.h> 35 36 #include <nvif/class.h> 37 #include <nvif/cl0080.h> 38 39 void 40 gk104_fifo_engine_status(struct gk104_fifo *fifo, int engn, 41 struct gk104_fifo_engine_status *status) 42 { 43 struct nvkm_engine *engine = fifo->engine[engn].engine; 44 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 45 struct nvkm_device *device = subdev->device; 46 u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08)); 47 48 status->busy = !!(stat & 0x80000000); 49 status->faulted = !!(stat & 0x40000000); 50 status->next.tsg = !!(stat & 0x10000000); 51 status->next.id = (stat & 0x0fff0000) >> 16; 52 status->chsw = !!(stat & 0x00008000); 53 status->save = !!(stat & 0x00004000); 54 status->load = !!(stat & 0x00002000); 55 status->prev.tsg = !!(stat & 0x00001000); 56 status->prev.id = (stat & 0x00000fff); 57 status->chan = NULL; 58 59 if (status->busy && status->chsw) { 60 if (status->load && status->save) { 61 if (engine && nvkm_engine_chsw_load(engine)) 62 status->chan = &status->next; 63 else 64 status->chan = &status->prev; 65 } else 66 if (status->load) { 67 status->chan = &status->next; 68 } else { 69 status->chan = &status->prev; 70 } 71 } else 72 if (status->load) { 73 status->chan = &status->prev; 74 } 75 76 nvkm_debug(subdev, "engine %02d: busy %d faulted %d chsw %d " 77 "save %d load %d %sid %d%s-> %sid %d%s\n", 78 engn, status->busy, status->faulted, 79 status->chsw, status->save, status->load, 80 status->prev.tsg ? "tsg" : "ch", status->prev.id, 81 status->chan == &status->prev ? "*" : " ", 82 status->next.tsg ? "tsg" : "ch", status->next.id, 83 status->chan == &status->next ? "*" : " "); 84 } 85 86 int 87 gk104_fifo_class_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, 88 void *argv, u32 argc, struct nvkm_object **pobject) 89 { 90 struct gk104_fifo *fifo = gk104_fifo(base); 91 if (oclass->engn == &fifo->func->chan) { 92 const struct gk104_fifo_chan_user *user = oclass->engn; 93 return user->ctor(fifo, oclass, argv, argc, pobject); 94 } else 95 if (oclass->engn == &fifo->func->user) { 96 const struct gk104_fifo_user_user *user = oclass->engn; 97 return user->ctor(oclass, argv, argc, pobject); 98 } 99 WARN_ON(1); 100 return -EINVAL; 101 } 102 103 int 104 gk104_fifo_class_get(struct nvkm_fifo *base, int index, 105 struct nvkm_oclass *oclass) 106 { 107 struct gk104_fifo *fifo = gk104_fifo(base); 108 int c = 0; 109 110 if (fifo->func->user.ctor && c++ == index) { 111 oclass->base = fifo->func->user.user; 112 oclass->engn = &fifo->func->user; 113 return 0; 114 } 115 116 if (fifo->func->chan.ctor && c++ == index) { 117 oclass->base = fifo->func->chan.user; 118 oclass->engn = &fifo->func->chan; 119 return 0; 120 } 121 122 return c; 123 } 124 125 void 126 gk104_fifo_uevent_fini(struct nvkm_fifo *fifo) 127 { 128 struct nvkm_device *device = fifo->engine.subdev.device; 129 nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); 130 } 131 132 void 133 gk104_fifo_uevent_init(struct nvkm_fifo *fifo) 134 { 135 struct nvkm_device *device = fifo->engine.subdev.device; 136 nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); 137 } 138 139 void 140 gk104_fifo_runlist_commit(struct gk104_fifo *fifo, int runl, 141 struct nvkm_memory *mem, int nr) 142 { 143 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 144 struct nvkm_device *device = subdev->device; 145 int target; 146 147 switch (nvkm_memory_target(mem)) { 148 case NVKM_MEM_TARGET_VRAM: target = 0; break; 149 case NVKM_MEM_TARGET_NCOH: target = 3; break; 150 default: 151 WARN_ON(1); 152 return; 153 } 154 155 nvkm_wr32(device, 0x002270, (nvkm_memory_addr(mem) >> 12) | 156 (target << 28)); 157 nvkm_wr32(device, 0x002274, (runl << 20) | nr); 158 159 if (nvkm_msec(device, 2000, 160 if (!(nvkm_rd32(device, 0x002284 + (runl * 0x08)) & 0x00100000)) 161 break; 162 ) < 0) 163 nvkm_error(subdev, "runlist %d update timeout\n", runl); 164 } 165 166 void 167 gk104_fifo_runlist_update(struct gk104_fifo *fifo, int runl) 168 { 169 const struct gk104_fifo_runlist_func *func = fifo->func->runlist; 170 struct gk104_fifo_chan *chan; 171 struct nvkm_memory *mem; 172 struct nvkm_fifo_cgrp *cgrp; 173 int nr = 0; 174 175 mutex_lock(&fifo->base.mutex); 176 mem = fifo->runlist[runl].mem[fifo->runlist[runl].next]; 177 fifo->runlist[runl].next = !fifo->runlist[runl].next; 178 179 nvkm_kmap(mem); 180 list_for_each_entry(chan, &fifo->runlist[runl].chan, head) { 181 func->chan(chan, mem, nr++ * func->size); 182 } 183 184 list_for_each_entry(cgrp, &fifo->runlist[runl].cgrp, head) { 185 func->cgrp(cgrp, mem, nr++ * func->size); 186 list_for_each_entry(chan, &cgrp->chan, head) { 187 func->chan(chan, mem, nr++ * func->size); 188 } 189 } 190 nvkm_done(mem); 191 192 func->commit(fifo, runl, mem, nr); 193 mutex_unlock(&fifo->base.mutex); 194 } 195 196 void 197 gk104_fifo_runlist_remove(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan) 198 { 199 struct nvkm_fifo_cgrp *cgrp = chan->cgrp; 200 mutex_lock(&fifo->base.mutex); 201 if (!list_empty(&chan->head)) { 202 list_del_init(&chan->head); 203 if (cgrp && !--cgrp->chan_nr) 204 list_del_init(&cgrp->head); 205 } 206 mutex_unlock(&fifo->base.mutex); 207 } 208 209 void 210 gk104_fifo_runlist_insert(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan) 211 { 212 struct nvkm_fifo_cgrp *cgrp = chan->cgrp; 213 mutex_lock(&fifo->base.mutex); 214 if (cgrp) { 215 if (!cgrp->chan_nr++) 216 list_add_tail(&cgrp->head, &fifo->runlist[chan->runl].cgrp); 217 list_add_tail(&chan->head, &cgrp->chan); 218 } else { 219 list_add_tail(&chan->head, &fifo->runlist[chan->runl].chan); 220 } 221 mutex_unlock(&fifo->base.mutex); 222 } 223 224 void 225 gk104_fifo_runlist_chan(struct gk104_fifo_chan *chan, 226 struct nvkm_memory *memory, u32 offset) 227 { 228 nvkm_wo32(memory, offset + 0, chan->base.chid); 229 nvkm_wo32(memory, offset + 4, 0x00000000); 230 } 231 232 const struct gk104_fifo_runlist_func 233 gk104_fifo_runlist = { 234 .size = 8, 235 .chan = gk104_fifo_runlist_chan, 236 .commit = gk104_fifo_runlist_commit, 237 }; 238 239 void 240 gk104_fifo_pbdma_init(struct gk104_fifo *fifo) 241 { 242 struct nvkm_device *device = fifo->base.engine.subdev.device; 243 nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1); 244 } 245 246 int 247 gk104_fifo_pbdma_nr(struct gk104_fifo *fifo) 248 { 249 struct nvkm_device *device = fifo->base.engine.subdev.device; 250 /* Determine number of PBDMAs by checking valid enable bits. */ 251 nvkm_wr32(device, 0x000204, 0xffffffff); 252 return hweight32(nvkm_rd32(device, 0x000204)); 253 } 254 255 const struct gk104_fifo_pbdma_func 256 gk104_fifo_pbdma = { 257 .nr = gk104_fifo_pbdma_nr, 258 .init = gk104_fifo_pbdma_init, 259 }; 260 261 static void 262 gk104_fifo_recover_work(struct work_struct *w) 263 { 264 struct gk104_fifo *fifo = container_of(w, typeof(*fifo), recover.work); 265 struct nvkm_device *device = fifo->base.engine.subdev.device; 266 struct nvkm_engine *engine; 267 unsigned long flags; 268 u32 engm, runm, todo; 269 int engn, runl; 270 271 spin_lock_irqsave(&fifo->base.lock, flags); 272 runm = fifo->recover.runm; 273 engm = fifo->recover.engm; 274 fifo->recover.engm = 0; 275 fifo->recover.runm = 0; 276 spin_unlock_irqrestore(&fifo->base.lock, flags); 277 278 nvkm_mask(device, 0x002630, runm, runm); 279 280 for (todo = engm; engn = __ffs(todo), todo; todo &= ~BIT(engn)) { 281 if ((engine = fifo->engine[engn].engine)) { 282 nvkm_subdev_fini(&engine->subdev, false); 283 WARN_ON(nvkm_subdev_init(&engine->subdev)); 284 } 285 } 286 287 for (todo = runm; runl = __ffs(todo), todo; todo &= ~BIT(runl)) 288 gk104_fifo_runlist_update(fifo, runl); 289 290 nvkm_wr32(device, 0x00262c, runm); 291 nvkm_mask(device, 0x002630, runm, 0x00000000); 292 } 293 294 static void gk104_fifo_recover_engn(struct gk104_fifo *fifo, int engn); 295 296 static void 297 gk104_fifo_recover_runl(struct gk104_fifo *fifo, int runl) 298 { 299 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 300 struct nvkm_device *device = subdev->device; 301 const u32 runm = BIT(runl); 302 303 assert_spin_locked(&fifo->base.lock); 304 if (fifo->recover.runm & runm) 305 return; 306 fifo->recover.runm |= runm; 307 308 /* Block runlist to prevent channel assignment(s) from changing. */ 309 nvkm_mask(device, 0x002630, runm, runm); 310 311 /* Schedule recovery. */ 312 nvkm_warn(subdev, "runlist %d: scheduled for recovery\n", runl); 313 schedule_work(&fifo->recover.work); 314 } 315 316 static struct gk104_fifo_chan * 317 gk104_fifo_recover_chid(struct gk104_fifo *fifo, int runl, int chid) 318 { 319 struct gk104_fifo_chan *chan; 320 struct nvkm_fifo_cgrp *cgrp; 321 322 list_for_each_entry(chan, &fifo->runlist[runl].chan, head) { 323 if (chan->base.chid == chid) { 324 list_del_init(&chan->head); 325 return chan; 326 } 327 } 328 329 list_for_each_entry(cgrp, &fifo->runlist[runl].cgrp, head) { 330 if (cgrp->id == chid) { 331 chan = list_first_entry(&cgrp->chan, typeof(*chan), head); 332 list_del_init(&chan->head); 333 if (!--cgrp->chan_nr) 334 list_del_init(&cgrp->head); 335 return chan; 336 } 337 } 338 339 return NULL; 340 } 341 342 static void 343 gk104_fifo_recover_chan(struct nvkm_fifo *base, int chid) 344 { 345 struct gk104_fifo *fifo = gk104_fifo(base); 346 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 347 struct nvkm_device *device = subdev->device; 348 const u32 stat = nvkm_rd32(device, 0x800004 + (chid * 0x08)); 349 const u32 runl = (stat & 0x000f0000) >> 16; 350 const bool used = (stat & 0x00000001); 351 unsigned long engn, engm = fifo->runlist[runl].engm; 352 struct gk104_fifo_chan *chan; 353 354 assert_spin_locked(&fifo->base.lock); 355 if (!used) 356 return; 357 358 /* Lookup SW state for channel, and mark it as dead. */ 359 chan = gk104_fifo_recover_chid(fifo, runl, chid); 360 if (chan) { 361 chan->killed = true; 362 nvkm_fifo_kevent(&fifo->base, chid); 363 } 364 365 /* Disable channel. */ 366 nvkm_wr32(device, 0x800004 + (chid * 0x08), stat | 0x00000800); 367 nvkm_warn(subdev, "channel %d: killed\n", chid); 368 369 /* Block channel assignments from changing during recovery. */ 370 gk104_fifo_recover_runl(fifo, runl); 371 372 /* Schedule recovery for any engines the channel is on. */ 373 for_each_set_bit(engn, &engm, fifo->engine_nr) { 374 struct gk104_fifo_engine_status status; 375 gk104_fifo_engine_status(fifo, engn, &status); 376 if (!status.chan || status.chan->id != chid) 377 continue; 378 gk104_fifo_recover_engn(fifo, engn); 379 } 380 } 381 382 static void 383 gk104_fifo_recover_engn(struct gk104_fifo *fifo, int engn) 384 { 385 struct nvkm_engine *engine = fifo->engine[engn].engine; 386 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 387 struct nvkm_device *device = subdev->device; 388 const u32 runl = fifo->engine[engn].runl; 389 const u32 engm = BIT(engn); 390 struct gk104_fifo_engine_status status; 391 int mmui = -1; 392 393 assert_spin_locked(&fifo->base.lock); 394 if (fifo->recover.engm & engm) 395 return; 396 fifo->recover.engm |= engm; 397 398 /* Block channel assignments from changing during recovery. */ 399 gk104_fifo_recover_runl(fifo, runl); 400 401 /* Determine which channel (if any) is currently on the engine. */ 402 gk104_fifo_engine_status(fifo, engn, &status); 403 if (status.chan) { 404 /* The channel is not longer viable, kill it. */ 405 gk104_fifo_recover_chan(&fifo->base, status.chan->id); 406 } 407 408 /* Determine MMU fault ID for the engine, if we're not being 409 * called from the fault handler already. 410 */ 411 if (!status.faulted && engine) { 412 mmui = nvkm_top_fault_id(device, engine->subdev.index); 413 if (mmui < 0) { 414 const struct nvkm_enum *en = fifo->func->fault.engine; 415 for (; en && en->name; en++) { 416 if (en->data2 == engine->subdev.index) { 417 mmui = en->value; 418 break; 419 } 420 } 421 } 422 WARN_ON(mmui < 0); 423 } 424 425 /* Trigger a MMU fault for the engine. 426 * 427 * No good idea why this is needed, but nvgpu does something similar, 428 * and it makes recovery from CTXSW_TIMEOUT a lot more reliable. 429 */ 430 if (mmui >= 0) { 431 nvkm_wr32(device, 0x002a30 + (engn * 0x04), 0x00000100 | mmui); 432 433 /* Wait for fault to trigger. */ 434 nvkm_msec(device, 2000, 435 gk104_fifo_engine_status(fifo, engn, &status); 436 if (status.faulted) 437 break; 438 ); 439 440 /* Release MMU fault trigger, and ACK the fault. */ 441 nvkm_wr32(device, 0x002a30 + (engn * 0x04), 0x00000000); 442 nvkm_wr32(device, 0x00259c, BIT(mmui)); 443 nvkm_wr32(device, 0x002100, 0x10000000); 444 } 445 446 /* Schedule recovery. */ 447 nvkm_warn(subdev, "engine %d: scheduled for recovery\n", engn); 448 schedule_work(&fifo->recover.work); 449 } 450 451 static void 452 gk104_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) 453 { 454 struct gk104_fifo *fifo = gk104_fifo(base); 455 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 456 struct nvkm_device *device = subdev->device; 457 const struct nvkm_enum *er, *ee, *ec, *ea; 458 struct nvkm_engine *engine = NULL; 459 struct nvkm_fifo_chan *chan; 460 unsigned long flags; 461 char ct[8] = "HUB/", en[16] = ""; 462 int engn; 463 464 er = nvkm_enum_find(fifo->func->fault.reason, info->reason); 465 ee = nvkm_enum_find(fifo->func->fault.engine, info->engine); 466 if (info->hub) { 467 ec = nvkm_enum_find(fifo->func->fault.hubclient, info->client); 468 } else { 469 ec = nvkm_enum_find(fifo->func->fault.gpcclient, info->client); 470 snprintf(ct, sizeof(ct), "GPC%d/", info->gpc); 471 } 472 ea = nvkm_enum_find(fifo->func->fault.access, info->access); 473 474 if (ee && ee->data2) { 475 switch (ee->data2) { 476 case NVKM_SUBDEV_BAR: 477 nvkm_bar_bar1_reset(device); 478 break; 479 case NVKM_SUBDEV_INSTMEM: 480 nvkm_bar_bar2_reset(device); 481 break; 482 case NVKM_ENGINE_IFB: 483 nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); 484 break; 485 default: 486 engine = nvkm_device_engine(device, ee->data2, 0); 487 break; 488 } 489 } 490 491 if (ee == NULL) { 492 enum nvkm_devidx engidx = nvkm_top_fault(device, info->engine); 493 if (engidx < NVKM_SUBDEV_NR) { 494 const char *src = nvkm_subdev_type[engidx]; 495 char *dst = en; 496 do { 497 *dst++ = toupper(*src++); 498 } while(*src); 499 engine = nvkm_device_engine(device, engidx, 0); 500 } 501 } else { 502 snprintf(en, sizeof(en), "%s", ee->name); 503 } 504 505 spin_lock_irqsave(&fifo->base.lock, flags); 506 chan = nvkm_fifo_chan_inst_locked(&fifo->base, info->inst); 507 508 nvkm_error(subdev, 509 "fault %02x [%s] at %016llx engine %02x [%s] client %02x " 510 "[%s%s] reason %02x [%s] on channel %d [%010llx %s]\n", 511 info->access, ea ? ea->name : "", info->addr, 512 info->engine, ee ? ee->name : en, 513 info->client, ct, ec ? ec->name : "", 514 info->reason, er ? er->name : "", chan ? chan->chid : -1, 515 info->inst, chan ? chan->object.client->name : "unknown"); 516 517 /* Kill the channel that caused the fault. */ 518 if (chan) 519 gk104_fifo_recover_chan(&fifo->base, chan->chid); 520 521 /* Channel recovery will probably have already done this for the 522 * correct engine(s), but just in case we can't find the channel 523 * information... 524 */ 525 for (engn = 0; engn < fifo->engine_nr && engine; engn++) { 526 if (fifo->engine[engn].engine == engine) { 527 gk104_fifo_recover_engn(fifo, engn); 528 break; 529 } 530 } 531 532 spin_unlock_irqrestore(&fifo->base.lock, flags); 533 } 534 535 static const struct nvkm_enum 536 gk104_fifo_bind_reason[] = { 537 { 0x01, "BIND_NOT_UNBOUND" }, 538 { 0x02, "SNOOP_WITHOUT_BAR1" }, 539 { 0x03, "UNBIND_WHILE_RUNNING" }, 540 { 0x05, "INVALID_RUNLIST" }, 541 { 0x06, "INVALID_CTX_TGT" }, 542 { 0x0b, "UNBIND_WHILE_PARKED" }, 543 {} 544 }; 545 546 void 547 gk104_fifo_intr_bind(struct gk104_fifo *fifo) 548 { 549 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 550 struct nvkm_device *device = subdev->device; 551 u32 intr = nvkm_rd32(device, 0x00252c); 552 u32 code = intr & 0x000000ff; 553 const struct nvkm_enum *en = 554 nvkm_enum_find(gk104_fifo_bind_reason, code); 555 556 nvkm_error(subdev, "BIND_ERROR %02x [%s]\n", code, en ? en->name : ""); 557 } 558 559 static const struct nvkm_enum 560 gk104_fifo_sched_reason[] = { 561 { 0x0a, "CTXSW_TIMEOUT" }, 562 {} 563 }; 564 565 static void 566 gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) 567 { 568 struct nvkm_device *device = fifo->base.engine.subdev.device; 569 unsigned long flags, engm = 0; 570 u32 engn; 571 572 /* We need to ACK the SCHED_ERROR here, and prevent it reasserting, 573 * as MMU_FAULT cannot be triggered while it's pending. 574 */ 575 spin_lock_irqsave(&fifo->base.lock, flags); 576 nvkm_mask(device, 0x002140, 0x00000100, 0x00000000); 577 nvkm_wr32(device, 0x002100, 0x00000100); 578 579 for (engn = 0; engn < fifo->engine_nr; engn++) { 580 struct gk104_fifo_engine_status status; 581 582 gk104_fifo_engine_status(fifo, engn, &status); 583 if (!status.busy || !status.chsw) 584 continue; 585 586 engm |= BIT(engn); 587 } 588 589 for_each_set_bit(engn, &engm, fifo->engine_nr) 590 gk104_fifo_recover_engn(fifo, engn); 591 592 nvkm_mask(device, 0x002140, 0x00000100, 0x00000100); 593 spin_unlock_irqrestore(&fifo->base.lock, flags); 594 } 595 596 static void 597 gk104_fifo_intr_sched(struct gk104_fifo *fifo) 598 { 599 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 600 struct nvkm_device *device = subdev->device; 601 u32 intr = nvkm_rd32(device, 0x00254c); 602 u32 code = intr & 0x000000ff; 603 const struct nvkm_enum *en = 604 nvkm_enum_find(gk104_fifo_sched_reason, code); 605 606 nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : ""); 607 608 switch (code) { 609 case 0x0a: 610 gk104_fifo_intr_sched_ctxsw(fifo); 611 break; 612 default: 613 break; 614 } 615 } 616 617 void 618 gk104_fifo_intr_chsw(struct gk104_fifo *fifo) 619 { 620 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 621 struct nvkm_device *device = subdev->device; 622 u32 stat = nvkm_rd32(device, 0x00256c); 623 nvkm_error(subdev, "CHSW_ERROR %08x\n", stat); 624 nvkm_wr32(device, 0x00256c, stat); 625 } 626 627 void 628 gk104_fifo_intr_dropped_fault(struct gk104_fifo *fifo) 629 { 630 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 631 struct nvkm_device *device = subdev->device; 632 u32 stat = nvkm_rd32(device, 0x00259c); 633 nvkm_error(subdev, "DROPPED_MMU_FAULT %08x\n", stat); 634 } 635 636 static const struct nvkm_bitfield gk104_fifo_pbdma_intr_0[] = { 637 { 0x00000001, "MEMREQ" }, 638 { 0x00000002, "MEMACK_TIMEOUT" }, 639 { 0x00000004, "MEMACK_EXTRA" }, 640 { 0x00000008, "MEMDAT_TIMEOUT" }, 641 { 0x00000010, "MEMDAT_EXTRA" }, 642 { 0x00000020, "MEMFLUSH" }, 643 { 0x00000040, "MEMOP" }, 644 { 0x00000080, "LBCONNECT" }, 645 { 0x00000100, "LBREQ" }, 646 { 0x00000200, "LBACK_TIMEOUT" }, 647 { 0x00000400, "LBACK_EXTRA" }, 648 { 0x00000800, "LBDAT_TIMEOUT" }, 649 { 0x00001000, "LBDAT_EXTRA" }, 650 { 0x00002000, "GPFIFO" }, 651 { 0x00004000, "GPPTR" }, 652 { 0x00008000, "GPENTRY" }, 653 { 0x00010000, "GPCRC" }, 654 { 0x00020000, "PBPTR" }, 655 { 0x00040000, "PBENTRY" }, 656 { 0x00080000, "PBCRC" }, 657 { 0x00100000, "XBARCONNECT" }, 658 { 0x00200000, "METHOD" }, 659 { 0x00400000, "METHODCRC" }, 660 { 0x00800000, "DEVICE" }, 661 { 0x02000000, "SEMAPHORE" }, 662 { 0x04000000, "ACQUIRE" }, 663 { 0x08000000, "PRI" }, 664 { 0x20000000, "NO_CTXSW_SEG" }, 665 { 0x40000000, "PBSEG" }, 666 { 0x80000000, "SIGNATURE" }, 667 {} 668 }; 669 670 void 671 gk104_fifo_intr_pbdma_0(struct gk104_fifo *fifo, int unit) 672 { 673 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 674 struct nvkm_device *device = subdev->device; 675 u32 mask = nvkm_rd32(device, 0x04010c + (unit * 0x2000)); 676 u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000)) & mask; 677 u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000)); 678 u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000)); 679 u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0xfff; 680 u32 subc = (addr & 0x00070000) >> 16; 681 u32 mthd = (addr & 0x00003ffc); 682 u32 show = stat; 683 struct nvkm_fifo_chan *chan; 684 unsigned long flags; 685 char msg[128]; 686 687 if (stat & 0x00800000) { 688 if (device->sw) { 689 if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data)) 690 show &= ~0x00800000; 691 } 692 } 693 694 nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008); 695 696 if (show) { 697 nvkm_snprintbf(msg, sizeof(msg), gk104_fifo_pbdma_intr_0, show); 698 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); 699 nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%010llx %s] " 700 "subc %d mthd %04x data %08x\n", 701 unit, show, msg, chid, chan ? chan->inst->addr : 0, 702 chan ? chan->object.client->name : "unknown", 703 subc, mthd, data); 704 nvkm_fifo_chan_put(&fifo->base, flags, &chan); 705 } 706 707 nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat); 708 } 709 710 static const struct nvkm_bitfield gk104_fifo_pbdma_intr_1[] = { 711 { 0x00000001, "HCE_RE_ILLEGAL_OP" }, 712 { 0x00000002, "HCE_RE_ALIGNB" }, 713 { 0x00000004, "HCE_PRIV" }, 714 { 0x00000008, "HCE_ILLEGAL_MTHD" }, 715 { 0x00000010, "HCE_ILLEGAL_CLASS" }, 716 {} 717 }; 718 719 void 720 gk104_fifo_intr_pbdma_1(struct gk104_fifo *fifo, int unit) 721 { 722 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 723 struct nvkm_device *device = subdev->device; 724 u32 mask = nvkm_rd32(device, 0x04014c + (unit * 0x2000)); 725 u32 stat = nvkm_rd32(device, 0x040148 + (unit * 0x2000)) & mask; 726 u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0xfff; 727 char msg[128]; 728 729 if (stat) { 730 nvkm_snprintbf(msg, sizeof(msg), gk104_fifo_pbdma_intr_1, stat); 731 nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d %08x %08x\n", 732 unit, stat, msg, chid, 733 nvkm_rd32(device, 0x040150 + (unit * 0x2000)), 734 nvkm_rd32(device, 0x040154 + (unit * 0x2000))); 735 } 736 737 nvkm_wr32(device, 0x040148 + (unit * 0x2000), stat); 738 } 739 740 void 741 gk104_fifo_intr_runlist(struct gk104_fifo *fifo) 742 { 743 struct nvkm_device *device = fifo->base.engine.subdev.device; 744 u32 mask = nvkm_rd32(device, 0x002a00); 745 while (mask) { 746 int runl = __ffs(mask); 747 wake_up(&fifo->runlist[runl].wait); 748 nvkm_wr32(device, 0x002a00, 1 << runl); 749 mask &= ~(1 << runl); 750 } 751 } 752 753 void 754 gk104_fifo_intr_engine(struct gk104_fifo *fifo) 755 { 756 nvkm_fifo_uevent(&fifo->base); 757 } 758 759 static void 760 gk104_fifo_intr(struct nvkm_fifo *base) 761 { 762 struct gk104_fifo *fifo = gk104_fifo(base); 763 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 764 struct nvkm_device *device = subdev->device; 765 u32 mask = nvkm_rd32(device, 0x002140); 766 u32 stat = nvkm_rd32(device, 0x002100) & mask; 767 768 if (stat & 0x00000001) { 769 gk104_fifo_intr_bind(fifo); 770 nvkm_wr32(device, 0x002100, 0x00000001); 771 stat &= ~0x00000001; 772 } 773 774 if (stat & 0x00000010) { 775 nvkm_error(subdev, "PIO_ERROR\n"); 776 nvkm_wr32(device, 0x002100, 0x00000010); 777 stat &= ~0x00000010; 778 } 779 780 if (stat & 0x00000100) { 781 gk104_fifo_intr_sched(fifo); 782 nvkm_wr32(device, 0x002100, 0x00000100); 783 stat &= ~0x00000100; 784 } 785 786 if (stat & 0x00010000) { 787 gk104_fifo_intr_chsw(fifo); 788 nvkm_wr32(device, 0x002100, 0x00010000); 789 stat &= ~0x00010000; 790 } 791 792 if (stat & 0x00800000) { 793 nvkm_error(subdev, "FB_FLUSH_TIMEOUT\n"); 794 nvkm_wr32(device, 0x002100, 0x00800000); 795 stat &= ~0x00800000; 796 } 797 798 if (stat & 0x01000000) { 799 nvkm_error(subdev, "LB_ERROR\n"); 800 nvkm_wr32(device, 0x002100, 0x01000000); 801 stat &= ~0x01000000; 802 } 803 804 if (stat & 0x08000000) { 805 gk104_fifo_intr_dropped_fault(fifo); 806 nvkm_wr32(device, 0x002100, 0x08000000); 807 stat &= ~0x08000000; 808 } 809 810 if (stat & 0x10000000) { 811 u32 mask = nvkm_rd32(device, 0x00259c); 812 while (mask) { 813 u32 unit = __ffs(mask); 814 fifo->func->intr.fault(&fifo->base, unit); 815 nvkm_wr32(device, 0x00259c, (1 << unit)); 816 mask &= ~(1 << unit); 817 } 818 stat &= ~0x10000000; 819 } 820 821 if (stat & 0x20000000) { 822 u32 mask = nvkm_rd32(device, 0x0025a0); 823 while (mask) { 824 u32 unit = __ffs(mask); 825 gk104_fifo_intr_pbdma_0(fifo, unit); 826 gk104_fifo_intr_pbdma_1(fifo, unit); 827 nvkm_wr32(device, 0x0025a0, (1 << unit)); 828 mask &= ~(1 << unit); 829 } 830 stat &= ~0x20000000; 831 } 832 833 if (stat & 0x40000000) { 834 gk104_fifo_intr_runlist(fifo); 835 stat &= ~0x40000000; 836 } 837 838 if (stat & 0x80000000) { 839 nvkm_wr32(device, 0x002100, 0x80000000); 840 gk104_fifo_intr_engine(fifo); 841 stat &= ~0x80000000; 842 } 843 844 if (stat) { 845 nvkm_error(subdev, "INTR %08x\n", stat); 846 nvkm_mask(device, 0x002140, stat, 0x00000000); 847 nvkm_wr32(device, 0x002100, stat); 848 } 849 } 850 851 void 852 gk104_fifo_fini(struct nvkm_fifo *base) 853 { 854 struct gk104_fifo *fifo = gk104_fifo(base); 855 struct nvkm_device *device = fifo->base.engine.subdev.device; 856 flush_work(&fifo->recover.work); 857 /* allow mmu fault interrupts, even when we're not using fifo */ 858 nvkm_mask(device, 0x002140, 0x10000000, 0x10000000); 859 } 860 861 int 862 gk104_fifo_info(struct nvkm_fifo *base, u64 mthd, u64 *data) 863 { 864 struct gk104_fifo *fifo = gk104_fifo(base); 865 switch (mthd) { 866 case NV_DEVICE_FIFO_RUNLISTS: 867 *data = (1ULL << fifo->runlist_nr) - 1; 868 return 0; 869 case NV_DEVICE_FIFO_RUNLIST_ENGINES(0)... 870 NV_DEVICE_FIFO_RUNLIST_ENGINES(63): { 871 int runl = mthd - NV_DEVICE_FIFO_RUNLIST_ENGINES(0), engn; 872 if (runl < fifo->runlist_nr) { 873 unsigned long engm = fifo->runlist[runl].engm; 874 struct nvkm_engine *engine; 875 *data = 0; 876 for_each_set_bit(engn, &engm, fifo->engine_nr) { 877 if ((engine = fifo->engine[engn].engine)) 878 *data |= BIT_ULL(engine->subdev.index); 879 } 880 return 0; 881 } 882 } 883 return -EINVAL; 884 default: 885 return -EINVAL; 886 } 887 } 888 889 int 890 gk104_fifo_oneinit(struct nvkm_fifo *base) 891 { 892 struct gk104_fifo *fifo = gk104_fifo(base); 893 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 894 struct nvkm_device *device = subdev->device; 895 struct nvkm_vmm *bar = nvkm_bar_bar1_vmm(device); 896 int engn, runl, pbid, ret, i, j; 897 enum nvkm_devidx engidx; 898 u32 *map; 899 900 fifo->pbdma_nr = fifo->func->pbdma->nr(fifo); 901 nvkm_debug(subdev, "%d PBDMA(s)\n", fifo->pbdma_nr); 902 903 /* Read PBDMA->runlist(s) mapping from HW. */ 904 if (!(map = kcalloc(fifo->pbdma_nr, sizeof(*map), GFP_KERNEL))) 905 return -ENOMEM; 906 907 for (i = 0; i < fifo->pbdma_nr; i++) 908 map[i] = nvkm_rd32(device, 0x002390 + (i * 0x04)); 909 910 /* Determine runlist configuration from topology device info. */ 911 i = 0; 912 while ((int)(engidx = nvkm_top_engine(device, i++, &runl, &engn)) >= 0) { 913 /* Determine which PBDMA handles requests for this engine. */ 914 for (j = 0, pbid = -1; j < fifo->pbdma_nr; j++) { 915 if (map[j] & (1 << runl)) { 916 pbid = j; 917 break; 918 } 919 } 920 921 nvkm_debug(subdev, "engine %2d: runlist %2d pbdma %2d (%s)\n", 922 engn, runl, pbid, nvkm_subdev_type[engidx]); 923 924 fifo->engine[engn].engine = nvkm_device_engine(device, engidx, 0); 925 fifo->engine[engn].runl = runl; 926 fifo->engine[engn].pbid = pbid; 927 fifo->engine_nr = max(fifo->engine_nr, engn + 1); 928 fifo->runlist[runl].engm |= 1 << engn; 929 fifo->runlist_nr = max(fifo->runlist_nr, runl + 1); 930 } 931 932 kfree(map); 933 934 for (i = 0; i < fifo->runlist_nr; i++) { 935 for (j = 0; j < ARRAY_SIZE(fifo->runlist[i].mem); j++) { 936 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 937 fifo->base.nr * 2/* TSG+chan */ * 938 fifo->func->runlist->size, 939 0x1000, false, 940 &fifo->runlist[i].mem[j]); 941 if (ret) 942 return ret; 943 } 944 945 init_waitqueue_head(&fifo->runlist[i].wait); 946 INIT_LIST_HEAD(&fifo->runlist[i].cgrp); 947 INIT_LIST_HEAD(&fifo->runlist[i].chan); 948 } 949 950 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 951 fifo->base.nr * 0x200, 0x1000, true, 952 &fifo->user.mem); 953 if (ret) 954 return ret; 955 956 ret = nvkm_vmm_get(bar, 12, nvkm_memory_size(fifo->user.mem), 957 &fifo->user.bar); 958 if (ret) 959 return ret; 960 961 return nvkm_memory_map(fifo->user.mem, 0, bar, fifo->user.bar, NULL, 0); 962 } 963 964 void 965 gk104_fifo_init(struct nvkm_fifo *base) 966 { 967 struct gk104_fifo *fifo = gk104_fifo(base); 968 struct nvkm_device *device = fifo->base.engine.subdev.device; 969 int i; 970 971 /* Enable PBDMAs. */ 972 fifo->func->pbdma->init(fifo); 973 974 /* PBDMA[n] */ 975 for (i = 0; i < fifo->pbdma_nr; i++) { 976 nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); 977 nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ 978 nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ 979 } 980 981 /* PBDMA[n].HCE */ 982 for (i = 0; i < fifo->pbdma_nr; i++) { 983 nvkm_wr32(device, 0x040148 + (i * 0x2000), 0xffffffff); /* INTR */ 984 nvkm_wr32(device, 0x04014c + (i * 0x2000), 0xffffffff); /* INTREN */ 985 } 986 987 nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar->addr >> 12); 988 989 if (fifo->func->pbdma->init_timeout) 990 fifo->func->pbdma->init_timeout(fifo); 991 992 nvkm_wr32(device, 0x002100, 0xffffffff); 993 nvkm_wr32(device, 0x002140, 0x7fffffff); 994 } 995 996 void * 997 gk104_fifo_dtor(struct nvkm_fifo *base) 998 { 999 struct gk104_fifo *fifo = gk104_fifo(base); 1000 struct nvkm_device *device = fifo->base.engine.subdev.device; 1001 int i; 1002 1003 nvkm_vmm_put(nvkm_bar_bar1_vmm(device), &fifo->user.bar); 1004 nvkm_memory_unref(&fifo->user.mem); 1005 1006 for (i = 0; i < fifo->runlist_nr; i++) { 1007 nvkm_memory_unref(&fifo->runlist[i].mem[1]); 1008 nvkm_memory_unref(&fifo->runlist[i].mem[0]); 1009 } 1010 1011 return fifo; 1012 } 1013 1014 static const struct nvkm_fifo_func 1015 gk104_fifo_ = { 1016 .dtor = gk104_fifo_dtor, 1017 .oneinit = gk104_fifo_oneinit, 1018 .info = gk104_fifo_info, 1019 .init = gk104_fifo_init, 1020 .fini = gk104_fifo_fini, 1021 .intr = gk104_fifo_intr, 1022 .fault = gk104_fifo_fault, 1023 .uevent_init = gk104_fifo_uevent_init, 1024 .uevent_fini = gk104_fifo_uevent_fini, 1025 .recover_chan = gk104_fifo_recover_chan, 1026 .class_get = gk104_fifo_class_get, 1027 .class_new = gk104_fifo_class_new, 1028 }; 1029 1030 int 1031 gk104_fifo_new_(const struct gk104_fifo_func *func, struct nvkm_device *device, 1032 int index, int nr, struct nvkm_fifo **pfifo) 1033 { 1034 struct gk104_fifo *fifo; 1035 1036 if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL))) 1037 return -ENOMEM; 1038 fifo->func = func; 1039 INIT_WORK(&fifo->recover.work, gk104_fifo_recover_work); 1040 *pfifo = &fifo->base; 1041 1042 return nvkm_fifo_ctor(&gk104_fifo_, device, index, nr, &fifo->base); 1043 } 1044 1045 const struct nvkm_enum 1046 gk104_fifo_fault_access[] = { 1047 { 0x0, "READ" }, 1048 { 0x1, "WRITE" }, 1049 {} 1050 }; 1051 1052 const struct nvkm_enum 1053 gk104_fifo_fault_engine[] = { 1054 { 0x00, "GR", NULL, NVKM_ENGINE_GR }, 1055 { 0x01, "DISPLAY" }, 1056 { 0x02, "CAPTURE" }, 1057 { 0x03, "IFB", NULL, NVKM_ENGINE_IFB }, 1058 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, 1059 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM }, 1060 { 0x06, "SCHED" }, 1061 { 0x07, "HOST0", NULL, NVKM_ENGINE_FIFO }, 1062 { 0x08, "HOST1", NULL, NVKM_ENGINE_FIFO }, 1063 { 0x09, "HOST2", NULL, NVKM_ENGINE_FIFO }, 1064 { 0x0a, "HOST3", NULL, NVKM_ENGINE_FIFO }, 1065 { 0x0b, "HOST4", NULL, NVKM_ENGINE_FIFO }, 1066 { 0x0c, "HOST5", NULL, NVKM_ENGINE_FIFO }, 1067 { 0x0d, "HOST6", NULL, NVKM_ENGINE_FIFO }, 1068 { 0x0e, "HOST7", NULL, NVKM_ENGINE_FIFO }, 1069 { 0x0f, "HOSTSR" }, 1070 { 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD }, 1071 { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP }, 1072 { 0x13, "PERF" }, 1073 { 0x14, "MSPDEC", NULL, NVKM_ENGINE_MSPDEC }, 1074 { 0x15, "CE0", NULL, NVKM_ENGINE_CE0 }, 1075 { 0x16, "CE1", NULL, NVKM_ENGINE_CE1 }, 1076 { 0x17, "PMU" }, 1077 { 0x18, "PTP" }, 1078 { 0x19, "MSENC", NULL, NVKM_ENGINE_MSENC }, 1079 { 0x1b, "CE2", NULL, NVKM_ENGINE_CE2 }, 1080 {} 1081 }; 1082 1083 const struct nvkm_enum 1084 gk104_fifo_fault_reason[] = { 1085 { 0x00, "PDE" }, 1086 { 0x01, "PDE_SIZE" }, 1087 { 0x02, "PTE" }, 1088 { 0x03, "VA_LIMIT_VIOLATION" }, 1089 { 0x04, "UNBOUND_INST_BLOCK" }, 1090 { 0x05, "PRIV_VIOLATION" }, 1091 { 0x06, "RO_VIOLATION" }, 1092 { 0x07, "WO_VIOLATION" }, 1093 { 0x08, "PITCH_MASK_VIOLATION" }, 1094 { 0x09, "WORK_CREATION" }, 1095 { 0x0a, "UNSUPPORTED_APERTURE" }, 1096 { 0x0b, "COMPRESSION_FAILURE" }, 1097 { 0x0c, "UNSUPPORTED_KIND" }, 1098 { 0x0d, "REGION_VIOLATION" }, 1099 { 0x0e, "BOTH_PTES_VALID" }, 1100 { 0x0f, "INFO_TYPE_POISONED" }, 1101 {} 1102 }; 1103 1104 const struct nvkm_enum 1105 gk104_fifo_fault_hubclient[] = { 1106 { 0x00, "VIP" }, 1107 { 0x01, "CE0" }, 1108 { 0x02, "CE1" }, 1109 { 0x03, "DNISO" }, 1110 { 0x04, "FE" }, 1111 { 0x05, "FECS" }, 1112 { 0x06, "HOST" }, 1113 { 0x07, "HOST_CPU" }, 1114 { 0x08, "HOST_CPU_NB" }, 1115 { 0x09, "ISO" }, 1116 { 0x0a, "MMU" }, 1117 { 0x0b, "MSPDEC" }, 1118 { 0x0c, "MSPPP" }, 1119 { 0x0d, "MSVLD" }, 1120 { 0x0e, "NISO" }, 1121 { 0x0f, "P2P" }, 1122 { 0x10, "PD" }, 1123 { 0x11, "PERF" }, 1124 { 0x12, "PMU" }, 1125 { 0x13, "RASTERTWOD" }, 1126 { 0x14, "SCC" }, 1127 { 0x15, "SCC_NB" }, 1128 { 0x16, "SEC" }, 1129 { 0x17, "SSYNC" }, 1130 { 0x18, "GR_CE" }, 1131 { 0x19, "CE2" }, 1132 { 0x1a, "XV" }, 1133 { 0x1b, "MMU_NB" }, 1134 { 0x1c, "MSENC" }, 1135 { 0x1d, "DFALCON" }, 1136 { 0x1e, "SKED" }, 1137 { 0x1f, "AFALCON" }, 1138 {} 1139 }; 1140 1141 const struct nvkm_enum 1142 gk104_fifo_fault_gpcclient[] = { 1143 { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" }, 1144 { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" }, 1145 { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" }, 1146 { 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" }, 1147 { 0x0c, "RAST" }, 1148 { 0x0d, "GCC" }, 1149 { 0x0e, "GPCCS" }, 1150 { 0x0f, "PROP_0" }, 1151 { 0x10, "PROP_1" }, 1152 { 0x11, "PROP_2" }, 1153 { 0x12, "PROP_3" }, 1154 { 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" }, 1155 { 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" }, 1156 { 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" }, 1157 { 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" }, 1158 { 0x1f, "GPM" }, 1159 { 0x20, "LTP_UTLB_0" }, 1160 { 0x21, "LTP_UTLB_1" }, 1161 { 0x22, "LTP_UTLB_2" }, 1162 { 0x23, "LTP_UTLB_3" }, 1163 { 0x24, "GPC_RGG_UTLB" }, 1164 {} 1165 }; 1166 1167 static const struct gk104_fifo_func 1168 gk104_fifo = { 1169 .intr.fault = gf100_fifo_intr_fault, 1170 .pbdma = &gk104_fifo_pbdma, 1171 .fault.access = gk104_fifo_fault_access, 1172 .fault.engine = gk104_fifo_fault_engine, 1173 .fault.reason = gk104_fifo_fault_reason, 1174 .fault.hubclient = gk104_fifo_fault_hubclient, 1175 .fault.gpcclient = gk104_fifo_fault_gpcclient, 1176 .runlist = &gk104_fifo_runlist, 1177 .chan = {{0,0,KEPLER_CHANNEL_GPFIFO_A}, gk104_fifo_gpfifo_new }, 1178 }; 1179 1180 int 1181 gk104_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) 1182 { 1183 return gk104_fifo_new_(&gk104_fifo, device, index, 4096, pfifo); 1184 } 1185