1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "gf100.h" 25 #include "changf100.h" 26 27 #include <core/client.h> 28 #include <core/enum.h> 29 #include <core/gpuobj.h> 30 #include <subdev/bar.h> 31 #include <engine/sw.h> 32 33 #include <nvif/class.h> 34 35 static void 36 gf100_fifo_uevent_init(struct nvkm_fifo *fifo) 37 { 38 struct nvkm_device *device = fifo->engine.subdev.device; 39 nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); 40 } 41 42 static void 43 gf100_fifo_uevent_fini(struct nvkm_fifo *fifo) 44 { 45 struct nvkm_device *device = fifo->engine.subdev.device; 46 nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); 47 } 48 49 void 50 gf100_fifo_runlist_commit(struct gf100_fifo *fifo) 51 { 52 struct gf100_fifo_chan *chan; 53 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 54 struct nvkm_device *device = subdev->device; 55 struct nvkm_memory *cur; 56 int nr = 0; 57 int target; 58 59 mutex_lock(&subdev->mutex); 60 cur = fifo->runlist.mem[fifo->runlist.active]; 61 fifo->runlist.active = !fifo->runlist.active; 62 63 nvkm_kmap(cur); 64 list_for_each_entry(chan, &fifo->chan, head) { 65 nvkm_wo32(cur, (nr * 8) + 0, chan->base.chid); 66 nvkm_wo32(cur, (nr * 8) + 4, 0x00000004); 67 nr++; 68 } 69 nvkm_done(cur); 70 71 target = (nvkm_memory_target(cur) == NVKM_MEM_TARGET_HOST) ? 0x3 : 0x0; 72 73 nvkm_wr32(device, 0x002270, (nvkm_memory_addr(cur) >> 12) | 74 (target << 28)); 75 nvkm_wr32(device, 0x002274, 0x01f00000 | nr); 76 77 if (wait_event_timeout(fifo->runlist.wait, 78 !(nvkm_rd32(device, 0x00227c) & 0x00100000), 79 msecs_to_jiffies(2000)) == 0) 80 nvkm_error(subdev, "runlist update timeout\n"); 81 mutex_unlock(&subdev->mutex); 82 } 83 84 void 85 gf100_fifo_runlist_remove(struct gf100_fifo *fifo, struct gf100_fifo_chan *chan) 86 { 87 mutex_lock(&fifo->base.engine.subdev.mutex); 88 list_del_init(&chan->head); 89 mutex_unlock(&fifo->base.engine.subdev.mutex); 90 } 91 92 void 93 gf100_fifo_runlist_insert(struct gf100_fifo *fifo, struct gf100_fifo_chan *chan) 94 { 95 mutex_lock(&fifo->base.engine.subdev.mutex); 96 list_add_tail(&chan->head, &fifo->chan); 97 mutex_unlock(&fifo->base.engine.subdev.mutex); 98 } 99 100 static inline int 101 gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn) 102 { 103 switch (engn) { 104 case NVKM_ENGINE_GR : engn = 0; break; 105 case NVKM_ENGINE_MSVLD : engn = 1; break; 106 case NVKM_ENGINE_MSPPP : engn = 2; break; 107 case NVKM_ENGINE_MSPDEC: engn = 3; break; 108 case NVKM_ENGINE_CE0 : engn = 4; break; 109 case NVKM_ENGINE_CE1 : engn = 5; break; 110 default: 111 return -1; 112 } 113 114 return engn; 115 } 116 117 static inline struct nvkm_engine * 118 gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn) 119 { 120 struct nvkm_device *device = fifo->base.engine.subdev.device; 121 122 switch (engn) { 123 case 0: engn = NVKM_ENGINE_GR; break; 124 case 1: engn = NVKM_ENGINE_MSVLD; break; 125 case 2: engn = NVKM_ENGINE_MSPPP; break; 126 case 3: engn = NVKM_ENGINE_MSPDEC; break; 127 case 4: engn = NVKM_ENGINE_CE0; break; 128 case 5: engn = NVKM_ENGINE_CE1; break; 129 default: 130 return NULL; 131 } 132 133 return nvkm_device_engine(device, engn); 134 } 135 136 static void 137 gf100_fifo_recover_work(struct work_struct *w) 138 { 139 struct gf100_fifo *fifo = container_of(w, typeof(*fifo), recover.work); 140 struct nvkm_device *device = fifo->base.engine.subdev.device; 141 struct nvkm_engine *engine; 142 unsigned long flags; 143 u32 engn, engm = 0; 144 u64 mask, todo; 145 146 spin_lock_irqsave(&fifo->base.lock, flags); 147 mask = fifo->recover.mask; 148 fifo->recover.mask = 0ULL; 149 spin_unlock_irqrestore(&fifo->base.lock, flags); 150 151 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~BIT_ULL(engn)) 152 engm |= 1 << gf100_fifo_engidx(fifo, engn); 153 nvkm_mask(device, 0x002630, engm, engm); 154 155 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~BIT_ULL(engn)) { 156 if ((engine = nvkm_device_engine(device, engn))) { 157 nvkm_subdev_fini(&engine->subdev, false); 158 WARN_ON(nvkm_subdev_init(&engine->subdev)); 159 } 160 } 161 162 gf100_fifo_runlist_commit(fifo); 163 nvkm_wr32(device, 0x00262c, engm); 164 nvkm_mask(device, 0x002630, engm, 0x00000000); 165 } 166 167 static void 168 gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine, 169 struct gf100_fifo_chan *chan) 170 { 171 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 172 struct nvkm_device *device = subdev->device; 173 u32 chid = chan->base.chid; 174 175 nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n", 176 nvkm_subdev_name[engine->subdev.index], chid); 177 assert_spin_locked(&fifo->base.lock); 178 179 nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000); 180 list_del_init(&chan->head); 181 chan->killed = true; 182 183 if (engine != &fifo->base.engine) 184 fifo->recover.mask |= 1ULL << engine->subdev.index; 185 schedule_work(&fifo->recover.work); 186 } 187 188 static const struct nvkm_enum 189 gf100_fifo_sched_reason[] = { 190 { 0x0a, "CTXSW_TIMEOUT" }, 191 {} 192 }; 193 194 static void 195 gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo) 196 { 197 struct nvkm_device *device = fifo->base.engine.subdev.device; 198 struct nvkm_engine *engine; 199 struct gf100_fifo_chan *chan; 200 unsigned long flags; 201 u32 engn; 202 203 spin_lock_irqsave(&fifo->base.lock, flags); 204 for (engn = 0; engn < 6; engn++) { 205 u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); 206 u32 busy = (stat & 0x80000000); 207 u32 save = (stat & 0x00100000); /* maybe? */ 208 u32 unk0 = (stat & 0x00040000); 209 u32 unk1 = (stat & 0x00001000); 210 u32 chid = (stat & 0x0000007f); 211 (void)save; 212 213 if (busy && unk0 && unk1) { 214 list_for_each_entry(chan, &fifo->chan, head) { 215 if (chan->base.chid == chid) { 216 engine = gf100_fifo_engine(fifo, engn); 217 if (!engine) 218 break; 219 gf100_fifo_recover(fifo, engine, chan); 220 break; 221 } 222 } 223 } 224 } 225 spin_unlock_irqrestore(&fifo->base.lock, flags); 226 } 227 228 static void 229 gf100_fifo_intr_sched(struct gf100_fifo *fifo) 230 { 231 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 232 struct nvkm_device *device = subdev->device; 233 u32 intr = nvkm_rd32(device, 0x00254c); 234 u32 code = intr & 0x000000ff; 235 const struct nvkm_enum *en; 236 237 en = nvkm_enum_find(gf100_fifo_sched_reason, code); 238 239 nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : ""); 240 241 switch (code) { 242 case 0x0a: 243 gf100_fifo_intr_sched_ctxsw(fifo); 244 break; 245 default: 246 break; 247 } 248 } 249 250 static const struct nvkm_enum 251 gf100_fifo_fault_engine[] = { 252 { 0x00, "PGRAPH", NULL, NVKM_ENGINE_GR }, 253 { 0x03, "PEEPHOLE", NULL, NVKM_ENGINE_IFB }, 254 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, 255 { 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM }, 256 { 0x07, "PFIFO", NULL, NVKM_ENGINE_FIFO }, 257 { 0x10, "PMSVLD", NULL, NVKM_ENGINE_MSVLD }, 258 { 0x11, "PMSPPP", NULL, NVKM_ENGINE_MSPPP }, 259 { 0x13, "PCOUNTER" }, 260 { 0x14, "PMSPDEC", NULL, NVKM_ENGINE_MSPDEC }, 261 { 0x15, "PCE0", NULL, NVKM_ENGINE_CE0 }, 262 { 0x16, "PCE1", NULL, NVKM_ENGINE_CE1 }, 263 { 0x17, "PMU" }, 264 {} 265 }; 266 267 static const struct nvkm_enum 268 gf100_fifo_fault_reason[] = { 269 { 0x00, "PT_NOT_PRESENT" }, 270 { 0x01, "PT_TOO_SHORT" }, 271 { 0x02, "PAGE_NOT_PRESENT" }, 272 { 0x03, "VM_LIMIT_EXCEEDED" }, 273 { 0x04, "NO_CHANNEL" }, 274 { 0x05, "PAGE_SYSTEM_ONLY" }, 275 { 0x06, "PAGE_READ_ONLY" }, 276 { 0x0a, "COMPRESSED_SYSRAM" }, 277 { 0x0c, "INVALID_STORAGE_TYPE" }, 278 {} 279 }; 280 281 static const struct nvkm_enum 282 gf100_fifo_fault_hubclient[] = { 283 { 0x01, "PCOPY0" }, 284 { 0x02, "PCOPY1" }, 285 { 0x04, "DISPATCH" }, 286 { 0x05, "CTXCTL" }, 287 { 0x06, "PFIFO" }, 288 { 0x07, "BAR_READ" }, 289 { 0x08, "BAR_WRITE" }, 290 { 0x0b, "PVP" }, 291 { 0x0c, "PMSPPP" }, 292 { 0x0d, "PMSVLD" }, 293 { 0x11, "PCOUNTER" }, 294 { 0x12, "PMU" }, 295 { 0x14, "CCACHE" }, 296 { 0x15, "CCACHE_POST" }, 297 {} 298 }; 299 300 static const struct nvkm_enum 301 gf100_fifo_fault_gpcclient[] = { 302 { 0x01, "TEX" }, 303 { 0x0c, "ESETUP" }, 304 { 0x0e, "CTXCTL" }, 305 { 0x0f, "PROP" }, 306 {} 307 }; 308 309 static void 310 gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit) 311 { 312 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 313 struct nvkm_device *device = subdev->device; 314 u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); 315 u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); 316 u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); 317 u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10)); 318 u32 gpc = (stat & 0x1f000000) >> 24; 319 u32 client = (stat & 0x00001f00) >> 8; 320 u32 write = (stat & 0x00000080); 321 u32 hub = (stat & 0x00000040); 322 u32 reason = (stat & 0x0000000f); 323 const struct nvkm_enum *er, *eu, *ec; 324 struct nvkm_engine *engine = NULL; 325 struct nvkm_fifo_chan *chan; 326 unsigned long flags; 327 char gpcid[8] = ""; 328 329 er = nvkm_enum_find(gf100_fifo_fault_reason, reason); 330 eu = nvkm_enum_find(gf100_fifo_fault_engine, unit); 331 if (hub) { 332 ec = nvkm_enum_find(gf100_fifo_fault_hubclient, client); 333 } else { 334 ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, client); 335 snprintf(gpcid, sizeof(gpcid), "GPC%d/", gpc); 336 } 337 338 if (eu && eu->data2) { 339 switch (eu->data2) { 340 case NVKM_SUBDEV_BAR: 341 nvkm_mask(device, 0x001704, 0x00000000, 0x00000000); 342 break; 343 case NVKM_SUBDEV_INSTMEM: 344 nvkm_mask(device, 0x001714, 0x00000000, 0x00000000); 345 break; 346 case NVKM_ENGINE_IFB: 347 nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); 348 break; 349 default: 350 engine = nvkm_device_engine(device, eu->data2); 351 break; 352 } 353 } 354 355 chan = nvkm_fifo_chan_inst(&fifo->base, (u64)inst << 12, &flags); 356 357 nvkm_error(subdev, 358 "%s fault at %010llx engine %02x [%s] client %02x [%s%s] " 359 "reason %02x [%s] on channel %d [%010llx %s]\n", 360 write ? "write" : "read", (u64)vahi << 32 | valo, 361 unit, eu ? eu->name : "", client, gpcid, ec ? ec->name : "", 362 reason, er ? er->name : "", chan ? chan->chid : -1, 363 (u64)inst << 12, 364 chan ? chan->object.client->name : "unknown"); 365 366 if (engine && chan) 367 gf100_fifo_recover(fifo, engine, (void *)chan); 368 nvkm_fifo_chan_put(&fifo->base, flags, &chan); 369 } 370 371 static const struct nvkm_bitfield 372 gf100_fifo_pbdma_intr[] = { 373 /* { 0x00008000, "" } seen with null ib push */ 374 { 0x00200000, "ILLEGAL_MTHD" }, 375 { 0x00800000, "EMPTY_SUBC" }, 376 {} 377 }; 378 379 static void 380 gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit) 381 { 382 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 383 struct nvkm_device *device = subdev->device; 384 u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000)); 385 u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000)); 386 u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000)); 387 u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0x7f; 388 u32 subc = (addr & 0x00070000) >> 16; 389 u32 mthd = (addr & 0x00003ffc); 390 struct nvkm_fifo_chan *chan; 391 unsigned long flags; 392 u32 show= stat; 393 char msg[128]; 394 395 if (stat & 0x00800000) { 396 if (device->sw) { 397 if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data)) 398 show &= ~0x00800000; 399 } 400 } 401 402 if (show) { 403 nvkm_snprintbf(msg, sizeof(msg), gf100_fifo_pbdma_intr, show); 404 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); 405 nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%010llx %s] " 406 "subc %d mthd %04x data %08x\n", 407 unit, show, msg, chid, chan ? chan->inst->addr : 0, 408 chan ? chan->object.client->name : "unknown", 409 subc, mthd, data); 410 nvkm_fifo_chan_put(&fifo->base, flags, &chan); 411 } 412 413 nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008); 414 nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat); 415 } 416 417 static void 418 gf100_fifo_intr_runlist(struct gf100_fifo *fifo) 419 { 420 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 421 struct nvkm_device *device = subdev->device; 422 u32 intr = nvkm_rd32(device, 0x002a00); 423 424 if (intr & 0x10000000) { 425 wake_up(&fifo->runlist.wait); 426 nvkm_wr32(device, 0x002a00, 0x10000000); 427 intr &= ~0x10000000; 428 } 429 430 if (intr) { 431 nvkm_error(subdev, "RUNLIST %08x\n", intr); 432 nvkm_wr32(device, 0x002a00, intr); 433 } 434 } 435 436 static void 437 gf100_fifo_intr_engine_unit(struct gf100_fifo *fifo, int engn) 438 { 439 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 440 struct nvkm_device *device = subdev->device; 441 u32 intr = nvkm_rd32(device, 0x0025a8 + (engn * 0x04)); 442 u32 inte = nvkm_rd32(device, 0x002628); 443 u32 unkn; 444 445 nvkm_wr32(device, 0x0025a8 + (engn * 0x04), intr); 446 447 for (unkn = 0; unkn < 8; unkn++) { 448 u32 ints = (intr >> (unkn * 0x04)) & inte; 449 if (ints & 0x1) { 450 nvkm_fifo_uevent(&fifo->base); 451 ints &= ~1; 452 } 453 if (ints) { 454 nvkm_error(subdev, "ENGINE %d %d %01x", 455 engn, unkn, ints); 456 nvkm_mask(device, 0x002628, ints, 0); 457 } 458 } 459 } 460 461 void 462 gf100_fifo_intr_engine(struct gf100_fifo *fifo) 463 { 464 struct nvkm_device *device = fifo->base.engine.subdev.device; 465 u32 mask = nvkm_rd32(device, 0x0025a4); 466 while (mask) { 467 u32 unit = __ffs(mask); 468 gf100_fifo_intr_engine_unit(fifo, unit); 469 mask &= ~(1 << unit); 470 } 471 } 472 473 static void 474 gf100_fifo_intr(struct nvkm_fifo *base) 475 { 476 struct gf100_fifo *fifo = gf100_fifo(base); 477 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 478 struct nvkm_device *device = subdev->device; 479 u32 mask = nvkm_rd32(device, 0x002140); 480 u32 stat = nvkm_rd32(device, 0x002100) & mask; 481 482 if (stat & 0x00000001) { 483 u32 intr = nvkm_rd32(device, 0x00252c); 484 nvkm_warn(subdev, "INTR 00000001: %08x\n", intr); 485 nvkm_wr32(device, 0x002100, 0x00000001); 486 stat &= ~0x00000001; 487 } 488 489 if (stat & 0x00000100) { 490 gf100_fifo_intr_sched(fifo); 491 nvkm_wr32(device, 0x002100, 0x00000100); 492 stat &= ~0x00000100; 493 } 494 495 if (stat & 0x00010000) { 496 u32 intr = nvkm_rd32(device, 0x00256c); 497 nvkm_warn(subdev, "INTR 00010000: %08x\n", intr); 498 nvkm_wr32(device, 0x002100, 0x00010000); 499 stat &= ~0x00010000; 500 } 501 502 if (stat & 0x01000000) { 503 u32 intr = nvkm_rd32(device, 0x00258c); 504 nvkm_warn(subdev, "INTR 01000000: %08x\n", intr); 505 nvkm_wr32(device, 0x002100, 0x01000000); 506 stat &= ~0x01000000; 507 } 508 509 if (stat & 0x10000000) { 510 u32 mask = nvkm_rd32(device, 0x00259c); 511 while (mask) { 512 u32 unit = __ffs(mask); 513 gf100_fifo_intr_fault(fifo, unit); 514 nvkm_wr32(device, 0x00259c, (1 << unit)); 515 mask &= ~(1 << unit); 516 } 517 stat &= ~0x10000000; 518 } 519 520 if (stat & 0x20000000) { 521 u32 mask = nvkm_rd32(device, 0x0025a0); 522 while (mask) { 523 u32 unit = __ffs(mask); 524 gf100_fifo_intr_pbdma(fifo, unit); 525 nvkm_wr32(device, 0x0025a0, (1 << unit)); 526 mask &= ~(1 << unit); 527 } 528 stat &= ~0x20000000; 529 } 530 531 if (stat & 0x40000000) { 532 gf100_fifo_intr_runlist(fifo); 533 stat &= ~0x40000000; 534 } 535 536 if (stat & 0x80000000) { 537 gf100_fifo_intr_engine(fifo); 538 stat &= ~0x80000000; 539 } 540 541 if (stat) { 542 nvkm_error(subdev, "INTR %08x\n", stat); 543 nvkm_mask(device, 0x002140, stat, 0x00000000); 544 nvkm_wr32(device, 0x002100, stat); 545 } 546 } 547 548 static int 549 gf100_fifo_oneinit(struct nvkm_fifo *base) 550 { 551 struct gf100_fifo *fifo = gf100_fifo(base); 552 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 553 struct nvkm_device *device = subdev->device; 554 int ret; 555 556 /* Determine number of PBDMAs by checking valid enable bits. */ 557 nvkm_wr32(device, 0x002204, 0xffffffff); 558 fifo->pbdma_nr = hweight32(nvkm_rd32(device, 0x002204)); 559 nvkm_debug(subdev, "%d PBDMA(s)\n", fifo->pbdma_nr); 560 561 562 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, 563 false, &fifo->runlist.mem[0]); 564 if (ret) 565 return ret; 566 567 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, 568 false, &fifo->runlist.mem[1]); 569 if (ret) 570 return ret; 571 572 init_waitqueue_head(&fifo->runlist.wait); 573 574 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 0x1000, 575 0x1000, false, &fifo->user.mem); 576 if (ret) 577 return ret; 578 579 ret = nvkm_bar_umap(device->bar, 128 * 0x1000, 12, &fifo->user.bar); 580 if (ret) 581 return ret; 582 583 nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0); 584 return 0; 585 } 586 587 static void 588 gf100_fifo_fini(struct nvkm_fifo *base) 589 { 590 struct gf100_fifo *fifo = gf100_fifo(base); 591 flush_work(&fifo->recover.work); 592 } 593 594 static void 595 gf100_fifo_init(struct nvkm_fifo *base) 596 { 597 struct gf100_fifo *fifo = gf100_fifo(base); 598 struct nvkm_device *device = fifo->base.engine.subdev.device; 599 int i; 600 601 /* Enable PBDMAs. */ 602 nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1); 603 nvkm_wr32(device, 0x002204, (1 << fifo->pbdma_nr) - 1); 604 605 /* Assign engines to PBDMAs. */ 606 if (fifo->pbdma_nr >= 3) { 607 nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */ 608 nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */ 609 nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */ 610 nvkm_wr32(device, 0x002214, ~(1 << 1)); /* PMSVLD */ 611 nvkm_wr32(device, 0x002218, ~(1 << 2)); /* PCE0 */ 612 nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */ 613 } 614 615 /* PBDMA[n] */ 616 for (i = 0; i < fifo->pbdma_nr; i++) { 617 nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); 618 nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ 619 nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ 620 } 621 622 nvkm_mask(device, 0x002200, 0x00000001, 0x00000001); 623 nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12); 624 625 nvkm_wr32(device, 0x002100, 0xffffffff); 626 nvkm_wr32(device, 0x002140, 0x7fffffff); 627 nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */ 628 } 629 630 static void * 631 gf100_fifo_dtor(struct nvkm_fifo *base) 632 { 633 struct gf100_fifo *fifo = gf100_fifo(base); 634 nvkm_vm_put(&fifo->user.bar); 635 nvkm_memory_del(&fifo->user.mem); 636 nvkm_memory_del(&fifo->runlist.mem[0]); 637 nvkm_memory_del(&fifo->runlist.mem[1]); 638 return fifo; 639 } 640 641 static const struct nvkm_fifo_func 642 gf100_fifo = { 643 .dtor = gf100_fifo_dtor, 644 .oneinit = gf100_fifo_oneinit, 645 .init = gf100_fifo_init, 646 .fini = gf100_fifo_fini, 647 .intr = gf100_fifo_intr, 648 .uevent_init = gf100_fifo_uevent_init, 649 .uevent_fini = gf100_fifo_uevent_fini, 650 .chan = { 651 &gf100_fifo_gpfifo_oclass, 652 NULL 653 }, 654 }; 655 656 int 657 gf100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) 658 { 659 struct gf100_fifo *fifo; 660 661 if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL))) 662 return -ENOMEM; 663 INIT_LIST_HEAD(&fifo->chan); 664 INIT_WORK(&fifo->recover.work, gf100_fifo_recover_work); 665 *pfifo = &fifo->base; 666 667 return nvkm_fifo_ctor(&gf100_fifo, device, index, 128, &fifo->base); 668 } 669