1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "gf100.h" 25 #include "changf100.h" 26 27 #include <core/client.h> 28 #include <core/enum.h> 29 #include <core/handle.h> 30 #include <subdev/bar.h> 31 #include <engine/sw.h> 32 33 #include <nvif/class.h> 34 35 static void 36 gf100_fifo_uevent_init(struct nvkm_event *event, int type, int index) 37 { 38 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); 39 struct nvkm_device *device = fifo->engine.subdev.device; 40 nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); 41 } 42 43 static void 44 gf100_fifo_uevent_fini(struct nvkm_event *event, int type, int index) 45 { 46 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); 47 struct nvkm_device *device = fifo->engine.subdev.device; 48 nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); 49 } 50 51 static const struct nvkm_event_func 52 gf100_fifo_uevent_func = { 53 .ctor = nvkm_fifo_uevent_ctor, 54 .init = gf100_fifo_uevent_init, 55 .fini = gf100_fifo_uevent_fini, 56 }; 57 58 void 59 gf100_fifo_runlist_update(struct gf100_fifo *fifo) 60 { 61 struct gf100_fifo_chan *chan; 62 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 63 struct nvkm_device *device = subdev->device; 64 struct nvkm_memory *cur; 65 int nr = 0; 66 67 mutex_lock(&nv_subdev(fifo)->mutex); 68 cur = fifo->runlist.mem[fifo->runlist.active]; 69 fifo->runlist.active = !fifo->runlist.active; 70 71 nvkm_kmap(cur); 72 list_for_each_entry(chan, &fifo->chan, head) { 73 nvkm_wo32(cur, (nr * 8) + 0, chan->base.chid); 74 nvkm_wo32(cur, (nr * 8) + 4, 0x00000004); 75 nr++; 76 } 77 nvkm_done(cur); 78 79 nvkm_wr32(device, 0x002270, nvkm_memory_addr(cur) >> 12); 80 nvkm_wr32(device, 0x002274, 0x01f00000 | nr); 81 82 if (wait_event_timeout(fifo->runlist.wait, 83 !(nvkm_rd32(device, 0x00227c) & 0x00100000), 84 msecs_to_jiffies(2000)) == 0) 85 nvkm_error(subdev, "runlist update timeout\n"); 86 mutex_unlock(&nv_subdev(fifo)->mutex); 87 } 88 89 static inline int 90 gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn) 91 { 92 switch (engn) { 93 case NVDEV_ENGINE_GR : engn = 0; break; 94 case NVDEV_ENGINE_MSVLD : engn = 1; break; 95 case NVDEV_ENGINE_MSPPP : engn = 2; break; 96 case NVDEV_ENGINE_MSPDEC: engn = 3; break; 97 case NVDEV_ENGINE_CE0 : engn = 4; break; 98 case NVDEV_ENGINE_CE1 : engn = 5; break; 99 default: 100 return -1; 101 } 102 103 return engn; 104 } 105 106 static inline struct nvkm_engine * 107 gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn) 108 { 109 switch (engn) { 110 case 0: engn = NVDEV_ENGINE_GR; break; 111 case 1: engn = NVDEV_ENGINE_MSVLD; break; 112 case 2: engn = NVDEV_ENGINE_MSPPP; break; 113 case 3: engn = NVDEV_ENGINE_MSPDEC; break; 114 case 4: engn = NVDEV_ENGINE_CE0; break; 115 case 5: engn = NVDEV_ENGINE_CE1; break; 116 default: 117 return NULL; 118 } 119 120 return nvkm_engine(fifo, engn); 121 } 122 123 static void 124 gf100_fifo_recover_work(struct work_struct *work) 125 { 126 struct gf100_fifo *fifo = container_of(work, typeof(*fifo), fault); 127 struct nvkm_device *device = fifo->base.engine.subdev.device; 128 struct nvkm_engine *engine; 129 unsigned long flags; 130 u32 engn, engm = 0; 131 u64 mask, todo; 132 133 spin_lock_irqsave(&fifo->base.lock, flags); 134 mask = fifo->mask; 135 fifo->mask = 0ULL; 136 spin_unlock_irqrestore(&fifo->base.lock, flags); 137 138 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) 139 engm |= 1 << gf100_fifo_engidx(fifo, engn); 140 nvkm_mask(device, 0x002630, engm, engm); 141 142 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { 143 if ((engine = nvkm_device_engine(device, engn))) { 144 nvkm_subdev_fini(&engine->subdev, false); 145 WARN_ON(nvkm_subdev_init(&engine->subdev)); 146 } 147 } 148 149 gf100_fifo_runlist_update(fifo); 150 nvkm_wr32(device, 0x00262c, engm); 151 nvkm_mask(device, 0x002630, engm, 0x00000000); 152 } 153 154 static void 155 gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine, 156 struct gf100_fifo_chan *chan) 157 { 158 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 159 struct nvkm_device *device = subdev->device; 160 u32 chid = chan->base.chid; 161 162 nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n", 163 nvkm_subdev_name[engine->subdev.index], chid); 164 assert_spin_locked(&fifo->base.lock); 165 166 nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000); 167 list_del_init(&chan->head); 168 chan->killed = true; 169 170 fifo->mask |= 1ULL << nv_engidx(engine); 171 schedule_work(&fifo->fault); 172 } 173 174 static const struct nvkm_enum 175 gf100_fifo_sched_reason[] = { 176 { 0x0a, "CTXSW_TIMEOUT" }, 177 {} 178 }; 179 180 static void 181 gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo) 182 { 183 struct nvkm_device *device = fifo->base.engine.subdev.device; 184 struct nvkm_engine *engine; 185 struct gf100_fifo_chan *chan; 186 unsigned long flags; 187 u32 engn; 188 189 spin_lock_irqsave(&fifo->base.lock, flags); 190 for (engn = 0; engn < 6; engn++) { 191 u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); 192 u32 busy = (stat & 0x80000000); 193 u32 save = (stat & 0x00100000); /* maybe? */ 194 u32 unk0 = (stat & 0x00040000); 195 u32 unk1 = (stat & 0x00001000); 196 u32 chid = (stat & 0x0000007f); 197 (void)save; 198 199 if (busy && unk0 && unk1) { 200 list_for_each_entry(chan, &fifo->chan, head) { 201 if (chan->base.chid == chid) { 202 engine = gf100_fifo_engine(fifo, engn); 203 if (!engine) 204 break; 205 gf100_fifo_recover(fifo, engine, chan); 206 break; 207 } 208 } 209 } 210 } 211 spin_unlock_irqrestore(&fifo->base.lock, flags); 212 } 213 214 static void 215 gf100_fifo_intr_sched(struct gf100_fifo *fifo) 216 { 217 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 218 struct nvkm_device *device = subdev->device; 219 u32 intr = nvkm_rd32(device, 0x00254c); 220 u32 code = intr & 0x000000ff; 221 const struct nvkm_enum *en; 222 223 en = nvkm_enum_find(gf100_fifo_sched_reason, code); 224 225 nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : ""); 226 227 switch (code) { 228 case 0x0a: 229 gf100_fifo_intr_sched_ctxsw(fifo); 230 break; 231 default: 232 break; 233 } 234 } 235 236 static const struct nvkm_enum 237 gf100_fifo_fault_engine[] = { 238 { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR }, 239 { 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB }, 240 { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, 241 { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM }, 242 { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO }, 243 { 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD }, 244 { 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP }, 245 { 0x13, "PCOUNTER" }, 246 { 0x14, "PMSPDEC", NULL, NVDEV_ENGINE_MSPDEC }, 247 { 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 }, 248 { 0x16, "PCE1", NULL, NVDEV_ENGINE_CE1 }, 249 { 0x17, "PDAEMON" }, 250 {} 251 }; 252 253 static const struct nvkm_enum 254 gf100_fifo_fault_reason[] = { 255 { 0x00, "PT_NOT_PRESENT" }, 256 { 0x01, "PT_TOO_SHORT" }, 257 { 0x02, "PAGE_NOT_PRESENT" }, 258 { 0x03, "VM_LIMIT_EXCEEDED" }, 259 { 0x04, "NO_CHANNEL" }, 260 { 0x05, "PAGE_SYSTEM_ONLY" }, 261 { 0x06, "PAGE_READ_ONLY" }, 262 { 0x0a, "COMPRESSED_SYSRAM" }, 263 { 0x0c, "INVALID_STORAGE_TYPE" }, 264 {} 265 }; 266 267 static const struct nvkm_enum 268 gf100_fifo_fault_hubclient[] = { 269 { 0x01, "PCOPY0" }, 270 { 0x02, "PCOPY1" }, 271 { 0x04, "DISPATCH" }, 272 { 0x05, "CTXCTL" }, 273 { 0x06, "PFIFO" }, 274 { 0x07, "BAR_READ" }, 275 { 0x08, "BAR_WRITE" }, 276 { 0x0b, "PVP" }, 277 { 0x0c, "PMSPPP" }, 278 { 0x0d, "PMSVLD" }, 279 { 0x11, "PCOUNTER" }, 280 { 0x12, "PDAEMON" }, 281 { 0x14, "CCACHE" }, 282 { 0x15, "CCACHE_POST" }, 283 {} 284 }; 285 286 static const struct nvkm_enum 287 gf100_fifo_fault_gpcclient[] = { 288 { 0x01, "TEX" }, 289 { 0x0c, "ESETUP" }, 290 { 0x0e, "CTXCTL" }, 291 { 0x0f, "PROP" }, 292 {} 293 }; 294 295 static void 296 gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit) 297 { 298 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 299 struct nvkm_device *device = subdev->device; 300 u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); 301 u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); 302 u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); 303 u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10)); 304 u32 gpc = (stat & 0x1f000000) >> 24; 305 u32 client = (stat & 0x00001f00) >> 8; 306 u32 write = (stat & 0x00000080); 307 u32 hub = (stat & 0x00000040); 308 u32 reason = (stat & 0x0000000f); 309 const struct nvkm_enum *er, *eu, *ec; 310 struct nvkm_engine *engine = NULL; 311 struct nvkm_fifo_chan *chan; 312 unsigned long flags; 313 char gpcid[8] = ""; 314 315 er = nvkm_enum_find(gf100_fifo_fault_reason, reason); 316 eu = nvkm_enum_find(gf100_fifo_fault_engine, unit); 317 if (hub) { 318 ec = nvkm_enum_find(gf100_fifo_fault_hubclient, client); 319 } else { 320 ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, client); 321 snprintf(gpcid, sizeof(gpcid), "GPC%d/", gpc); 322 } 323 324 if (eu) { 325 switch (eu->data2) { 326 case NVDEV_SUBDEV_BAR: 327 nvkm_mask(device, 0x001704, 0x00000000, 0x00000000); 328 break; 329 case NVDEV_SUBDEV_INSTMEM: 330 nvkm_mask(device, 0x001714, 0x00000000, 0x00000000); 331 break; 332 case NVDEV_ENGINE_IFB: 333 nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); 334 break; 335 default: 336 engine = nvkm_engine(fifo, eu->data2); 337 break; 338 } 339 } 340 341 chan = nvkm_fifo_chan_inst(&fifo->base, (u64)inst << 12, &flags); 342 343 nvkm_error(subdev, 344 "%s fault at %010llx engine %02x [%s] client %02x [%s%s] " 345 "reason %02x [%s] on channel %d [%010llx %s]\n", 346 write ? "write" : "read", (u64)vahi << 32 | valo, 347 unit, eu ? eu->name : "", client, gpcid, ec ? ec->name : "", 348 reason, er ? er->name : "", chan ? chan->chid : -1, 349 (u64)inst << 12, 350 chan ? chan->object.client->name : "unknown"); 351 352 if (engine && chan) 353 gf100_fifo_recover(fifo, engine, (void *)chan); 354 nvkm_fifo_chan_put(&fifo->base, flags, &chan); 355 } 356 357 static const struct nvkm_bitfield 358 gf100_fifo_pbdma_intr[] = { 359 /* { 0x00008000, "" } seen with null ib push */ 360 { 0x00200000, "ILLEGAL_MTHD" }, 361 { 0x00800000, "EMPTY_SUBC" }, 362 {} 363 }; 364 365 static void 366 gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit) 367 { 368 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 369 struct nvkm_device *device = subdev->device; 370 u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000)); 371 u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000)); 372 u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000)); 373 u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0x7f; 374 u32 subc = (addr & 0x00070000) >> 16; 375 u32 mthd = (addr & 0x00003ffc); 376 struct nvkm_fifo_chan *chan; 377 unsigned long flags; 378 u32 show= stat; 379 char msg[128]; 380 381 if (stat & 0x00800000) { 382 if (device->sw) { 383 if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data)) 384 show &= ~0x00800000; 385 } 386 } 387 388 if (show) { 389 nvkm_snprintbf(msg, sizeof(msg), gf100_fifo_pbdma_intr, show); 390 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); 391 nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%010llx %s] " 392 "subc %d mthd %04x data %08x\n", 393 unit, show, msg, chid, chan ? chan->inst->addr : 0, 394 chan ? chan->object.client->name : "unknown", 395 subc, mthd, data); 396 nvkm_fifo_chan_put(&fifo->base, flags, &chan); 397 } 398 399 nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008); 400 nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat); 401 } 402 403 static void 404 gf100_fifo_intr_runlist(struct gf100_fifo *fifo) 405 { 406 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 407 struct nvkm_device *device = subdev->device; 408 u32 intr = nvkm_rd32(device, 0x002a00); 409 410 if (intr & 0x10000000) { 411 wake_up(&fifo->runlist.wait); 412 nvkm_wr32(device, 0x002a00, 0x10000000); 413 intr &= ~0x10000000; 414 } 415 416 if (intr) { 417 nvkm_error(subdev, "RUNLIST %08x\n", intr); 418 nvkm_wr32(device, 0x002a00, intr); 419 } 420 } 421 422 static void 423 gf100_fifo_intr_engine_unit(struct gf100_fifo *fifo, int engn) 424 { 425 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 426 struct nvkm_device *device = subdev->device; 427 u32 intr = nvkm_rd32(device, 0x0025a8 + (engn * 0x04)); 428 u32 inte = nvkm_rd32(device, 0x002628); 429 u32 unkn; 430 431 nvkm_wr32(device, 0x0025a8 + (engn * 0x04), intr); 432 433 for (unkn = 0; unkn < 8; unkn++) { 434 u32 ints = (intr >> (unkn * 0x04)) & inte; 435 if (ints & 0x1) { 436 nvkm_fifo_uevent(&fifo->base); 437 ints &= ~1; 438 } 439 if (ints) { 440 nvkm_error(subdev, "ENGINE %d %d %01x", 441 engn, unkn, ints); 442 nvkm_mask(device, 0x002628, ints, 0); 443 } 444 } 445 } 446 447 void 448 gf100_fifo_intr_engine(struct gf100_fifo *fifo) 449 { 450 struct nvkm_device *device = fifo->base.engine.subdev.device; 451 u32 mask = nvkm_rd32(device, 0x0025a4); 452 while (mask) { 453 u32 unit = __ffs(mask); 454 gf100_fifo_intr_engine_unit(fifo, unit); 455 mask &= ~(1 << unit); 456 } 457 } 458 459 static void 460 gf100_fifo_intr(struct nvkm_subdev *subdev) 461 { 462 struct gf100_fifo *fifo = (void *)subdev; 463 struct nvkm_device *device = fifo->base.engine.subdev.device; 464 u32 mask = nvkm_rd32(device, 0x002140); 465 u32 stat = nvkm_rd32(device, 0x002100) & mask; 466 467 if (stat & 0x00000001) { 468 u32 intr = nvkm_rd32(device, 0x00252c); 469 nvkm_warn(subdev, "INTR 00000001: %08x\n", intr); 470 nvkm_wr32(device, 0x002100, 0x00000001); 471 stat &= ~0x00000001; 472 } 473 474 if (stat & 0x00000100) { 475 gf100_fifo_intr_sched(fifo); 476 nvkm_wr32(device, 0x002100, 0x00000100); 477 stat &= ~0x00000100; 478 } 479 480 if (stat & 0x00010000) { 481 u32 intr = nvkm_rd32(device, 0x00256c); 482 nvkm_warn(subdev, "INTR 00010000: %08x\n", intr); 483 nvkm_wr32(device, 0x002100, 0x00010000); 484 stat &= ~0x00010000; 485 } 486 487 if (stat & 0x01000000) { 488 u32 intr = nvkm_rd32(device, 0x00258c); 489 nvkm_warn(subdev, "INTR 01000000: %08x\n", intr); 490 nvkm_wr32(device, 0x002100, 0x01000000); 491 stat &= ~0x01000000; 492 } 493 494 if (stat & 0x10000000) { 495 u32 mask = nvkm_rd32(device, 0x00259c); 496 while (mask) { 497 u32 unit = __ffs(mask); 498 gf100_fifo_intr_fault(fifo, unit); 499 nvkm_wr32(device, 0x00259c, (1 << unit)); 500 mask &= ~(1 << unit); 501 } 502 stat &= ~0x10000000; 503 } 504 505 if (stat & 0x20000000) { 506 u32 mask = nvkm_rd32(device, 0x0025a0); 507 while (mask) { 508 u32 unit = __ffs(mask); 509 gf100_fifo_intr_pbdma(fifo, unit); 510 nvkm_wr32(device, 0x0025a0, (1 << unit)); 511 mask &= ~(1 << unit); 512 } 513 stat &= ~0x20000000; 514 } 515 516 if (stat & 0x40000000) { 517 gf100_fifo_intr_runlist(fifo); 518 stat &= ~0x40000000; 519 } 520 521 if (stat & 0x80000000) { 522 gf100_fifo_intr_engine(fifo); 523 stat &= ~0x80000000; 524 } 525 526 if (stat) { 527 nvkm_error(subdev, "INTR %08x\n", stat); 528 nvkm_mask(device, 0x002140, stat, 0x00000000); 529 nvkm_wr32(device, 0x002100, stat); 530 } 531 } 532 533 static int 534 gf100_fifo_init(struct nvkm_object *object) 535 { 536 struct gf100_fifo *fifo = (void *)object; 537 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 538 struct nvkm_device *device = subdev->device; 539 int ret, i; 540 541 ret = nvkm_fifo_init(&fifo->base); 542 if (ret) 543 return ret; 544 545 nvkm_wr32(device, 0x000204, 0xffffffff); 546 nvkm_wr32(device, 0x002204, 0xffffffff); 547 548 fifo->spoon_nr = hweight32(nvkm_rd32(device, 0x002204)); 549 nvkm_debug(subdev, "%d PBDMA unit(s)\n", fifo->spoon_nr); 550 551 /* assign engines to PBDMAs */ 552 if (fifo->spoon_nr >= 3) { 553 nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */ 554 nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */ 555 nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */ 556 nvkm_wr32(device, 0x002214, ~(1 << 1)); /* PMSVLD */ 557 nvkm_wr32(device, 0x002218, ~(1 << 2)); /* PCE0 */ 558 nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */ 559 } 560 561 /* PBDMA[n] */ 562 for (i = 0; i < fifo->spoon_nr; i++) { 563 nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); 564 nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ 565 nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ 566 } 567 568 nvkm_mask(device, 0x002200, 0x00000001, 0x00000001); 569 nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12); 570 571 nvkm_wr32(device, 0x002100, 0xffffffff); 572 nvkm_wr32(device, 0x002140, 0x7fffffff); 573 nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */ 574 return 0; 575 } 576 577 static void 578 gf100_fifo_dtor(struct nvkm_object *object) 579 { 580 struct gf100_fifo *fifo = (void *)object; 581 582 nvkm_vm_put(&fifo->user.bar); 583 nvkm_memory_del(&fifo->user.mem); 584 nvkm_memory_del(&fifo->runlist.mem[0]); 585 nvkm_memory_del(&fifo->runlist.mem[1]); 586 587 nvkm_fifo_destroy(&fifo->base); 588 } 589 590 static const struct nvkm_fifo_func 591 gf100_fifo_func = { 592 .chan = { 593 &gf100_fifo_gpfifo_oclass, 594 NULL 595 }, 596 }; 597 598 static int 599 gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 600 struct nvkm_oclass *oclass, void *data, u32 size, 601 struct nvkm_object **pobject) 602 { 603 struct nvkm_device *device = (void *)parent; 604 struct nvkm_bar *bar = device->bar; 605 struct gf100_fifo *fifo; 606 int ret; 607 608 ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &fifo); 609 *pobject = nv_object(fifo); 610 if (ret) 611 return ret; 612 613 fifo->base.func = &gf100_fifo_func; 614 615 INIT_LIST_HEAD(&fifo->chan); 616 INIT_WORK(&fifo->fault, gf100_fifo_recover_work); 617 618 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, 619 false, &fifo->runlist.mem[0]); 620 if (ret) 621 return ret; 622 623 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, 624 false, &fifo->runlist.mem[1]); 625 if (ret) 626 return ret; 627 628 init_waitqueue_head(&fifo->runlist.wait); 629 630 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 0x1000, 631 0x1000, false, &fifo->user.mem); 632 if (ret) 633 return ret; 634 635 ret = nvkm_bar_umap(bar, 128 * 0x1000, 12, &fifo->user.bar); 636 if (ret) 637 return ret; 638 639 nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0); 640 641 ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &fifo->base.uevent); 642 if (ret) 643 return ret; 644 645 nv_subdev(fifo)->unit = 0x00000100; 646 nv_subdev(fifo)->intr = gf100_fifo_intr; 647 return 0; 648 } 649 650 651 struct nvkm_oclass * 652 gf100_fifo_oclass = &(struct nvkm_oclass) { 653 .handle = NV_ENGINE(FIFO, 0xc0), 654 .ofuncs = &(struct nvkm_ofuncs) { 655 .ctor = gf100_fifo_ctor, 656 .dtor = gf100_fifo_dtor, 657 .init = gf100_fifo_init, 658 .fini = _nvkm_fifo_fini, 659 }, 660 }; 661