1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 #include "nv04.h" 26 27 #include <core/client.h> 28 #include <core/engctx.h> 29 #include <core/ramht.h> 30 #include <subdev/bar.h> 31 #include <subdev/mmu.h> 32 #include <subdev/timer.h> 33 34 #include <nvif/class.h> 35 #include <nvif/unpack.h> 36 37 /******************************************************************************* 38 * FIFO channel objects 39 ******************************************************************************/ 40 41 static int 42 g84_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) 43 { 44 struct nvkm_bar *bar = nvkm_bar(parent); 45 struct nv50_fifo_base *base = (void *)parent->parent; 46 struct nvkm_gpuobj *ectx = (void *)object; 47 u64 limit = ectx->addr + ectx->size - 1; 48 u64 start = ectx->addr; 49 u32 addr; 50 51 switch (nv_engidx(object->engine)) { 52 case NVDEV_ENGINE_SW : return 0; 53 case NVDEV_ENGINE_GR : addr = 0x0020; break; 54 case NVDEV_ENGINE_VP : 55 case NVDEV_ENGINE_MSPDEC: addr = 0x0040; break; 56 case NVDEV_ENGINE_MSPPP : 57 case NVDEV_ENGINE_MPEG : addr = 0x0060; break; 58 case NVDEV_ENGINE_BSP : 59 case NVDEV_ENGINE_MSVLD : addr = 0x0080; break; 60 case NVDEV_ENGINE_CIPHER: 61 case NVDEV_ENGINE_SEC : addr = 0x00a0; break; 62 case NVDEV_ENGINE_CE0 : addr = 0x00c0; break; 63 default: 64 return -EINVAL; 65 } 66 67 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; 68 nvkm_kmap(base->eng); 69 nvkm_wo32(base->eng, addr + 0x00, 0x00190000); 70 nvkm_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); 71 nvkm_wo32(base->eng, addr + 0x08, lower_32_bits(start)); 72 nvkm_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 | 73 upper_32_bits(start)); 74 nvkm_wo32(base->eng, addr + 0x10, 0x00000000); 75 nvkm_wo32(base->eng, addr + 0x14, 0x00000000); 76 bar->flush(bar); 77 nvkm_done(base->eng); 78 return 0; 79 } 80 81 static int 82 g84_fifo_context_detach(struct nvkm_object *parent, bool suspend, 83 struct nvkm_object *object) 84 { 85 struct nv50_fifo *fifo = (void *)parent->engine; 86 struct nv50_fifo_base *base = (void *)parent->parent; 87 struct nv50_fifo_chan *chan = (void *)parent; 88 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 89 struct nvkm_device *device = subdev->device; 90 struct nvkm_bar *bar = device->bar; 91 u32 addr, save, engn; 92 bool done; 93 94 switch (nv_engidx(object->engine)) { 95 case NVDEV_ENGINE_SW : return 0; 96 case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break; 97 case NVDEV_ENGINE_VP : 98 case NVDEV_ENGINE_MSPDEC: engn = 3; addr = 0x0040; break; 99 case NVDEV_ENGINE_MSPPP : 100 case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break; 101 case NVDEV_ENGINE_BSP : 102 case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break; 103 case NVDEV_ENGINE_CIPHER: 104 case NVDEV_ENGINE_SEC : engn = 4; addr = 0x00a0; break; 105 case NVDEV_ENGINE_CE0 : engn = 2; addr = 0x00c0; break; 106 default: 107 return -EINVAL; 108 } 109 110 save = nvkm_mask(device, 0x002520, 0x0000003f, 1 << engn); 111 nvkm_wr32(device, 0x0032fc, nv_gpuobj(base)->addr >> 12); 112 done = nvkm_msec(device, 2000, 113 if (nvkm_rd32(device, 0x0032fc) != 0xffffffff) 114 break; 115 ) >= 0; 116 nvkm_wr32(device, 0x002520, save); 117 if (!done) { 118 nvkm_error(subdev, "channel %d [%s] unload timeout\n", 119 chan->base.chid, nvkm_client_name(chan)); 120 if (suspend) 121 return -EBUSY; 122 } 123 124 nvkm_kmap(base->eng); 125 nvkm_wo32(base->eng, addr + 0x00, 0x00000000); 126 nvkm_wo32(base->eng, addr + 0x04, 0x00000000); 127 nvkm_wo32(base->eng, addr + 0x08, 0x00000000); 128 nvkm_wo32(base->eng, addr + 0x0c, 0x00000000); 129 nvkm_wo32(base->eng, addr + 0x10, 0x00000000); 130 nvkm_wo32(base->eng, addr + 0x14, 0x00000000); 131 bar->flush(bar); 132 nvkm_done(base->eng); 133 return 0; 134 } 135 136 static int 137 g84_fifo_object_attach(struct nvkm_object *parent, 138 struct nvkm_object *object, u32 handle) 139 { 140 struct nv50_fifo_chan *chan = (void *)parent; 141 u32 context; 142 143 if (nv_iclass(object, NV_GPUOBJ_CLASS)) 144 context = nv_gpuobj(object)->node->offset >> 4; 145 else 146 context = 0x00000004; /* just non-zero */ 147 148 switch (nv_engidx(object->engine)) { 149 case NVDEV_ENGINE_DMAOBJ: 150 case NVDEV_ENGINE_SW : context |= 0x00000000; break; 151 case NVDEV_ENGINE_GR : context |= 0x00100000; break; 152 case NVDEV_ENGINE_MPEG : 153 case NVDEV_ENGINE_MSPPP : context |= 0x00200000; break; 154 case NVDEV_ENGINE_ME : 155 case NVDEV_ENGINE_CE0 : context |= 0x00300000; break; 156 case NVDEV_ENGINE_VP : 157 case NVDEV_ENGINE_MSPDEC: context |= 0x00400000; break; 158 case NVDEV_ENGINE_CIPHER: 159 case NVDEV_ENGINE_SEC : 160 case NVDEV_ENGINE_VIC : context |= 0x00500000; break; 161 case NVDEV_ENGINE_BSP : 162 case NVDEV_ENGINE_MSVLD : context |= 0x00600000; break; 163 default: 164 return -EINVAL; 165 } 166 167 return nvkm_ramht_insert(chan->ramht, 0, handle, context); 168 } 169 170 static int 171 g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, 172 struct nvkm_oclass *oclass, void *data, u32 size, 173 struct nvkm_object **pobject) 174 { 175 union { 176 struct nv50_channel_dma_v0 v0; 177 } *args = data; 178 struct nvkm_bar *bar = nvkm_bar(parent); 179 struct nv50_fifo_base *base = (void *)parent; 180 struct nv50_fifo_chan *chan; 181 int ret; 182 183 nvif_ioctl(parent, "create channel dma size %d\n", size); 184 if (nvif_unpack(args->v0, 0, 0, false)) { 185 nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " 186 "offset %016llx\n", args->v0.version, 187 args->v0.pushbuf, args->v0.offset); 188 if (args->v0.vm) 189 return -ENOENT; 190 } else 191 return ret; 192 193 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, 194 0x2000, args->v0.pushbuf, 195 (1ULL << NVDEV_ENGINE_DMAOBJ) | 196 (1ULL << NVDEV_ENGINE_SW) | 197 (1ULL << NVDEV_ENGINE_GR) | 198 (1ULL << NVDEV_ENGINE_MPEG) | 199 (1ULL << NVDEV_ENGINE_ME) | 200 (1ULL << NVDEV_ENGINE_VP) | 201 (1ULL << NVDEV_ENGINE_CIPHER) | 202 (1ULL << NVDEV_ENGINE_SEC) | 203 (1ULL << NVDEV_ENGINE_BSP) | 204 (1ULL << NVDEV_ENGINE_MSVLD) | 205 (1ULL << NVDEV_ENGINE_MSPDEC) | 206 (1ULL << NVDEV_ENGINE_MSPPP) | 207 (1ULL << NVDEV_ENGINE_CE0) | 208 (1ULL << NVDEV_ENGINE_VIC), &chan); 209 *pobject = nv_object(chan); 210 if (ret) 211 return ret; 212 213 args->v0.chid = chan->base.chid; 214 215 ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, 216 &chan->ramht); 217 if (ret) 218 return ret; 219 220 nv_parent(chan)->context_attach = g84_fifo_context_attach; 221 nv_parent(chan)->context_detach = g84_fifo_context_detach; 222 nv_parent(chan)->object_attach = g84_fifo_object_attach; 223 nv_parent(chan)->object_detach = nv50_fifo_object_detach; 224 225 nvkm_kmap(base->ramfc); 226 nvkm_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); 227 nvkm_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset)); 228 nvkm_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset)); 229 nvkm_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset)); 230 nvkm_wo32(base->ramfc, 0x3c, 0x003f6078); 231 nvkm_wo32(base->ramfc, 0x44, 0x01003fff); 232 nvkm_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); 233 nvkm_wo32(base->ramfc, 0x4c, 0xffffffff); 234 nvkm_wo32(base->ramfc, 0x60, 0x7fffffff); 235 nvkm_wo32(base->ramfc, 0x78, 0x00000000); 236 nvkm_wo32(base->ramfc, 0x7c, 0x30000001); 237 nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | 238 (4 << 24) /* SEARCH_FULL */ | 239 (chan->ramht->gpuobj.node->offset >> 4)); 240 nvkm_wo32(base->ramfc, 0x88, base->cache->addr >> 10); 241 nvkm_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12); 242 bar->flush(bar); 243 nvkm_done(base->ramfc); 244 return 0; 245 } 246 247 static int 248 g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, 249 struct nvkm_oclass *oclass, void *data, u32 size, 250 struct nvkm_object **pobject) 251 { 252 union { 253 struct nv50_channel_gpfifo_v0 v0; 254 } *args = data; 255 struct nvkm_bar *bar = nvkm_bar(parent); 256 struct nv50_fifo_base *base = (void *)parent; 257 struct nv50_fifo_chan *chan; 258 u64 ioffset, ilength; 259 int ret; 260 261 nvif_ioctl(parent, "create channel gpfifo size %d\n", size); 262 if (nvif_unpack(args->v0, 0, 0, false)) { 263 nvif_ioctl(parent, "create channel gpfifo vers %d pushbuf %llx " 264 "ioffset %016llx ilength %08x\n", 265 args->v0.version, args->v0.pushbuf, args->v0.ioffset, 266 args->v0.ilength); 267 if (args->v0.vm) 268 return -ENOENT; 269 } else 270 return ret; 271 272 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, 273 0x2000, args->v0.pushbuf, 274 (1ULL << NVDEV_ENGINE_DMAOBJ) | 275 (1ULL << NVDEV_ENGINE_SW) | 276 (1ULL << NVDEV_ENGINE_GR) | 277 (1ULL << NVDEV_ENGINE_MPEG) | 278 (1ULL << NVDEV_ENGINE_ME) | 279 (1ULL << NVDEV_ENGINE_VP) | 280 (1ULL << NVDEV_ENGINE_CIPHER) | 281 (1ULL << NVDEV_ENGINE_SEC) | 282 (1ULL << NVDEV_ENGINE_BSP) | 283 (1ULL << NVDEV_ENGINE_MSVLD) | 284 (1ULL << NVDEV_ENGINE_MSPDEC) | 285 (1ULL << NVDEV_ENGINE_MSPPP) | 286 (1ULL << NVDEV_ENGINE_CE0) | 287 (1ULL << NVDEV_ENGINE_VIC), &chan); 288 *pobject = nv_object(chan); 289 if (ret) 290 return ret; 291 292 args->v0.chid = chan->base.chid; 293 294 ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, 295 &chan->ramht); 296 if (ret) 297 return ret; 298 299 nv_parent(chan)->context_attach = g84_fifo_context_attach; 300 nv_parent(chan)->context_detach = g84_fifo_context_detach; 301 nv_parent(chan)->object_attach = g84_fifo_object_attach; 302 nv_parent(chan)->object_detach = nv50_fifo_object_detach; 303 304 ioffset = args->v0.ioffset; 305 ilength = order_base_2(args->v0.ilength / 8); 306 307 nvkm_kmap(base->ramfc); 308 nvkm_wo32(base->ramfc, 0x3c, 0x403f6078); 309 nvkm_wo32(base->ramfc, 0x44, 0x01003fff); 310 nvkm_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); 311 nvkm_wo32(base->ramfc, 0x50, lower_32_bits(ioffset)); 312 nvkm_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); 313 nvkm_wo32(base->ramfc, 0x60, 0x7fffffff); 314 nvkm_wo32(base->ramfc, 0x78, 0x00000000); 315 nvkm_wo32(base->ramfc, 0x7c, 0x30000001); 316 nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | 317 (4 << 24) /* SEARCH_FULL */ | 318 (chan->ramht->gpuobj.node->offset >> 4)); 319 nvkm_wo32(base->ramfc, 0x88, base->cache->addr >> 10); 320 nvkm_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12); 321 bar->flush(bar); 322 nvkm_done(base->ramfc); 323 return 0; 324 } 325 326 static int 327 g84_fifo_chan_init(struct nvkm_object *object) 328 { 329 struct nv50_fifo *fifo = (void *)object->engine; 330 struct nv50_fifo_base *base = (void *)object->parent; 331 struct nv50_fifo_chan *chan = (void *)object; 332 struct nvkm_gpuobj *ramfc = base->ramfc; 333 struct nvkm_device *device = fifo->base.engine.subdev.device; 334 u32 chid = chan->base.chid; 335 int ret; 336 337 ret = nvkm_fifo_channel_init(&chan->base); 338 if (ret) 339 return ret; 340 341 nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8); 342 nv50_fifo_playlist_update(fifo); 343 return 0; 344 } 345 346 static struct nvkm_ofuncs 347 g84_fifo_ofuncs_dma = { 348 .ctor = g84_fifo_chan_ctor_dma, 349 .dtor = nv50_fifo_chan_dtor, 350 .init = g84_fifo_chan_init, 351 .fini = nv50_fifo_chan_fini, 352 .map = _nvkm_fifo_channel_map, 353 .rd32 = _nvkm_fifo_channel_rd32, 354 .wr32 = _nvkm_fifo_channel_wr32, 355 .ntfy = _nvkm_fifo_channel_ntfy 356 }; 357 358 static struct nvkm_ofuncs 359 g84_fifo_ofuncs_ind = { 360 .ctor = g84_fifo_chan_ctor_ind, 361 .dtor = nv50_fifo_chan_dtor, 362 .init = g84_fifo_chan_init, 363 .fini = nv50_fifo_chan_fini, 364 .map = _nvkm_fifo_channel_map, 365 .rd32 = _nvkm_fifo_channel_rd32, 366 .wr32 = _nvkm_fifo_channel_wr32, 367 .ntfy = _nvkm_fifo_channel_ntfy 368 }; 369 370 static struct nvkm_oclass 371 g84_fifo_sclass[] = { 372 { G82_CHANNEL_DMA, &g84_fifo_ofuncs_dma }, 373 { G82_CHANNEL_GPFIFO, &g84_fifo_ofuncs_ind }, 374 {} 375 }; 376 377 /******************************************************************************* 378 * FIFO context - basically just the instmem reserved for the channel 379 ******************************************************************************/ 380 381 static int 382 g84_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 383 struct nvkm_oclass *oclass, void *data, u32 size, 384 struct nvkm_object **pobject) 385 { 386 struct nv50_fifo_base *base; 387 int ret; 388 389 ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000, 390 0x1000, NVOBJ_FLAG_HEAP, &base); 391 *pobject = nv_object(base); 392 if (ret) 393 return ret; 394 395 ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0, 396 NVOBJ_FLAG_ZERO_ALLOC, &base->eng); 397 if (ret) 398 return ret; 399 400 ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, 401 0, &base->pgd); 402 if (ret) 403 return ret; 404 405 ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); 406 if (ret) 407 return ret; 408 409 ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x1000, 410 0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache); 411 if (ret) 412 return ret; 413 414 ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0100, 415 0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc); 416 if (ret) 417 return ret; 418 419 return 0; 420 } 421 422 static struct nvkm_oclass 423 g84_fifo_cclass = { 424 .handle = NV_ENGCTX(FIFO, 0x84), 425 .ofuncs = &(struct nvkm_ofuncs) { 426 .ctor = g84_fifo_context_ctor, 427 .dtor = nv50_fifo_context_dtor, 428 .init = _nvkm_fifo_context_init, 429 .fini = _nvkm_fifo_context_fini, 430 .rd32 = _nvkm_fifo_context_rd32, 431 .wr32 = _nvkm_fifo_context_wr32, 432 }, 433 }; 434 435 /******************************************************************************* 436 * PFIFO engine 437 ******************************************************************************/ 438 439 static void 440 g84_fifo_uevent_init(struct nvkm_event *event, int type, int index) 441 { 442 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); 443 struct nvkm_device *device = fifo->engine.subdev.device; 444 nvkm_mask(device, 0x002140, 0x40000000, 0x40000000); 445 } 446 447 static void 448 g84_fifo_uevent_fini(struct nvkm_event *event, int type, int index) 449 { 450 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); 451 struct nvkm_device *device = fifo->engine.subdev.device; 452 nvkm_mask(device, 0x002140, 0x40000000, 0x00000000); 453 } 454 455 static const struct nvkm_event_func 456 g84_fifo_uevent_func = { 457 .ctor = nvkm_fifo_uevent_ctor, 458 .init = g84_fifo_uevent_init, 459 .fini = g84_fifo_uevent_fini, 460 }; 461 462 static int 463 g84_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 464 struct nvkm_oclass *oclass, void *data, u32 size, 465 struct nvkm_object **pobject) 466 { 467 struct nv50_fifo *fifo; 468 int ret; 469 470 ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &fifo); 471 *pobject = nv_object(fifo); 472 if (ret) 473 return ret; 474 475 ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 128 * 4, 0x1000, 0, 476 &fifo->playlist[0]); 477 if (ret) 478 return ret; 479 480 ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 128 * 4, 0x1000, 0, 481 &fifo->playlist[1]); 482 if (ret) 483 return ret; 484 485 ret = nvkm_event_init(&g84_fifo_uevent_func, 1, 1, &fifo->base.uevent); 486 if (ret) 487 return ret; 488 489 nv_subdev(fifo)->unit = 0x00000100; 490 nv_subdev(fifo)->intr = nv04_fifo_intr; 491 nv_engine(fifo)->cclass = &g84_fifo_cclass; 492 nv_engine(fifo)->sclass = g84_fifo_sclass; 493 fifo->base.pause = nv04_fifo_pause; 494 fifo->base.start = nv04_fifo_start; 495 return 0; 496 } 497 498 struct nvkm_oclass * 499 g84_fifo_oclass = &(struct nvkm_oclass) { 500 .handle = NV_ENGINE(FIFO, 0x84), 501 .ofuncs = &(struct nvkm_ofuncs) { 502 .ctor = g84_fifo_ctor, 503 .dtor = nv50_fifo_dtor, 504 .init = nv50_fifo_init, 505 .fini = _nvkm_fifo_fini, 506 }, 507 }; 508