1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 #include "nv04.h" 26 27 #include <core/client.h> 28 #include <core/engctx.h> 29 #include <core/ramht.h> 30 #include <subdev/mmu.h> 31 #include <subdev/timer.h> 32 33 #include <nvif/class.h> 34 #include <nvif/unpack.h> 35 36 /******************************************************************************* 37 * FIFO channel objects 38 ******************************************************************************/ 39 40 static int 41 g84_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) 42 { 43 struct nv50_fifo_base *base = (void *)parent->parent; 44 struct nvkm_gpuobj *ectx = (void *)object; 45 u64 limit = ectx->addr + ectx->size - 1; 46 u64 start = ectx->addr; 47 u32 addr; 48 49 switch (nv_engidx(object->engine)) { 50 case NVDEV_ENGINE_SW : return 0; 51 case NVDEV_ENGINE_GR : addr = 0x0020; break; 52 case NVDEV_ENGINE_VP : 53 case NVDEV_ENGINE_MSPDEC: addr = 0x0040; break; 54 case NVDEV_ENGINE_MSPPP : 55 case NVDEV_ENGINE_MPEG : addr = 0x0060; break; 56 case NVDEV_ENGINE_BSP : 57 case NVDEV_ENGINE_MSVLD : addr = 0x0080; break; 58 case NVDEV_ENGINE_CIPHER: 59 case NVDEV_ENGINE_SEC : addr = 0x00a0; break; 60 case NVDEV_ENGINE_CE0 : addr = 0x00c0; break; 61 default: 62 return -EINVAL; 63 } 64 65 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; 66 nvkm_kmap(base->eng); 67 nvkm_wo32(base->eng, addr + 0x00, 0x00190000); 68 nvkm_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); 69 nvkm_wo32(base->eng, addr + 0x08, lower_32_bits(start)); 70 nvkm_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 | 71 upper_32_bits(start)); 72 nvkm_wo32(base->eng, addr + 0x10, 0x00000000); 73 nvkm_wo32(base->eng, addr + 0x14, 0x00000000); 74 nvkm_done(base->eng); 75 return 0; 76 } 77 78 static int 79 g84_fifo_context_detach(struct nvkm_object *parent, bool suspend, 80 struct nvkm_object *object) 81 { 82 struct nv50_fifo *fifo = (void *)parent->engine; 83 struct nv50_fifo_base *base = (void *)parent->parent; 84 struct nv50_fifo_chan *chan = (void *)parent; 85 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 86 struct nvkm_device *device = subdev->device; 87 u32 addr, save, engn; 88 bool done; 89 90 switch (nv_engidx(object->engine)) { 91 case NVDEV_ENGINE_SW : return 0; 92 case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break; 93 case NVDEV_ENGINE_VP : 94 case NVDEV_ENGINE_MSPDEC: engn = 3; addr = 0x0040; break; 95 case NVDEV_ENGINE_MSPPP : 96 case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break; 97 case NVDEV_ENGINE_BSP : 98 case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break; 99 case NVDEV_ENGINE_CIPHER: 100 case NVDEV_ENGINE_SEC : engn = 4; addr = 0x00a0; break; 101 case NVDEV_ENGINE_CE0 : engn = 2; addr = 0x00c0; break; 102 default: 103 return -EINVAL; 104 } 105 106 save = nvkm_mask(device, 0x002520, 0x0000003f, 1 << engn); 107 nvkm_wr32(device, 0x0032fc, nv_gpuobj(base)->addr >> 12); 108 done = nvkm_msec(device, 2000, 109 if (nvkm_rd32(device, 0x0032fc) != 0xffffffff) 110 break; 111 ) >= 0; 112 nvkm_wr32(device, 0x002520, save); 113 if (!done) { 114 nvkm_error(subdev, "channel %d [%s] unload timeout\n", 115 chan->base.chid, nvkm_client_name(chan)); 116 if (suspend) 117 return -EBUSY; 118 } 119 120 nvkm_kmap(base->eng); 121 nvkm_wo32(base->eng, addr + 0x00, 0x00000000); 122 nvkm_wo32(base->eng, addr + 0x04, 0x00000000); 123 nvkm_wo32(base->eng, addr + 0x08, 0x00000000); 124 nvkm_wo32(base->eng, addr + 0x0c, 0x00000000); 125 nvkm_wo32(base->eng, addr + 0x10, 0x00000000); 126 nvkm_wo32(base->eng, addr + 0x14, 0x00000000); 127 nvkm_done(base->eng); 128 return 0; 129 } 130 131 static int 132 g84_fifo_object_attach(struct nvkm_object *parent, 133 struct nvkm_object *object, u32 handle) 134 { 135 struct nv50_fifo_chan *chan = (void *)parent; 136 u32 context; 137 138 if (nv_iclass(object, NV_GPUOBJ_CLASS)) 139 context = nv_gpuobj(object)->node->offset >> 4; 140 else 141 context = 0x00000004; /* just non-zero */ 142 143 if (object->engine) { 144 switch (nv_engidx(object->engine)) { 145 case NVDEV_ENGINE_DMAOBJ: 146 case NVDEV_ENGINE_SW : context |= 0x00000000; break; 147 case NVDEV_ENGINE_GR : context |= 0x00100000; break; 148 case NVDEV_ENGINE_MPEG : 149 case NVDEV_ENGINE_MSPPP : context |= 0x00200000; break; 150 case NVDEV_ENGINE_ME : 151 case NVDEV_ENGINE_CE0 : context |= 0x00300000; break; 152 case NVDEV_ENGINE_VP : 153 case NVDEV_ENGINE_MSPDEC: context |= 0x00400000; break; 154 case NVDEV_ENGINE_CIPHER: 155 case NVDEV_ENGINE_SEC : 156 case NVDEV_ENGINE_VIC : context |= 0x00500000; break; 157 case NVDEV_ENGINE_BSP : 158 case NVDEV_ENGINE_MSVLD : context |= 0x00600000; break; 159 default: 160 return -EINVAL; 161 } 162 } 163 164 return nvkm_ramht_insert(chan->ramht, NULL, 0, 0, handle, context); 165 } 166 167 static int 168 g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, 169 struct nvkm_oclass *oclass, void *data, u32 size, 170 struct nvkm_object **pobject) 171 { 172 union { 173 struct nv50_channel_dma_v0 v0; 174 } *args = data; 175 struct nvkm_device *device = parent->engine->subdev.device; 176 struct nv50_fifo_base *base = (void *)parent; 177 struct nv50_fifo_chan *chan; 178 int ret; 179 180 nvif_ioctl(parent, "create channel dma size %d\n", size); 181 if (nvif_unpack(args->v0, 0, 0, false)) { 182 nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " 183 "offset %016llx\n", args->v0.version, 184 args->v0.pushbuf, args->v0.offset); 185 if (args->v0.vm) 186 return -ENOENT; 187 } else 188 return ret; 189 190 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, 191 0x2000, args->v0.pushbuf, 192 (1ULL << NVDEV_ENGINE_DMAOBJ) | 193 (1ULL << NVDEV_ENGINE_SW) | 194 (1ULL << NVDEV_ENGINE_GR) | 195 (1ULL << NVDEV_ENGINE_MPEG) | 196 (1ULL << NVDEV_ENGINE_ME) | 197 (1ULL << NVDEV_ENGINE_VP) | 198 (1ULL << NVDEV_ENGINE_CIPHER) | 199 (1ULL << NVDEV_ENGINE_SEC) | 200 (1ULL << NVDEV_ENGINE_BSP) | 201 (1ULL << NVDEV_ENGINE_MSVLD) | 202 (1ULL << NVDEV_ENGINE_MSPDEC) | 203 (1ULL << NVDEV_ENGINE_MSPPP) | 204 (1ULL << NVDEV_ENGINE_CE0) | 205 (1ULL << NVDEV_ENGINE_VIC), &chan); 206 *pobject = nv_object(chan); 207 if (ret) 208 return ret; 209 210 chan->base.inst = base->base.gpuobj.addr; 211 args->v0.chid = chan->base.chid; 212 213 ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj, 214 &chan->ramht); 215 if (ret) 216 return ret; 217 218 nv_parent(chan)->context_attach = g84_fifo_context_attach; 219 nv_parent(chan)->context_detach = g84_fifo_context_detach; 220 nv_parent(chan)->object_attach = g84_fifo_object_attach; 221 nv_parent(chan)->object_detach = nv50_fifo_object_detach; 222 223 nvkm_kmap(base->ramfc); 224 nvkm_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); 225 nvkm_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset)); 226 nvkm_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset)); 227 nvkm_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset)); 228 nvkm_wo32(base->ramfc, 0x3c, 0x003f6078); 229 nvkm_wo32(base->ramfc, 0x44, 0x01003fff); 230 nvkm_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); 231 nvkm_wo32(base->ramfc, 0x4c, 0xffffffff); 232 nvkm_wo32(base->ramfc, 0x60, 0x7fffffff); 233 nvkm_wo32(base->ramfc, 0x78, 0x00000000); 234 nvkm_wo32(base->ramfc, 0x7c, 0x30000001); 235 nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | 236 (4 << 24) /* SEARCH_FULL */ | 237 (chan->ramht->gpuobj->node->offset >> 4)); 238 nvkm_wo32(base->ramfc, 0x88, base->cache->addr >> 10); 239 nvkm_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12); 240 nvkm_done(base->ramfc); 241 return 0; 242 } 243 244 static int 245 g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, 246 struct nvkm_oclass *oclass, void *data, u32 size, 247 struct nvkm_object **pobject) 248 { 249 union { 250 struct nv50_channel_gpfifo_v0 v0; 251 } *args = data; 252 struct nvkm_device *device = parent->engine->subdev.device; 253 struct nv50_fifo_base *base = (void *)parent; 254 struct nv50_fifo_chan *chan; 255 u64 ioffset, ilength; 256 int ret; 257 258 nvif_ioctl(parent, "create channel gpfifo size %d\n", size); 259 if (nvif_unpack(args->v0, 0, 0, false)) { 260 nvif_ioctl(parent, "create channel gpfifo vers %d pushbuf %llx " 261 "ioffset %016llx ilength %08x\n", 262 args->v0.version, args->v0.pushbuf, args->v0.ioffset, 263 args->v0.ilength); 264 if (args->v0.vm) 265 return -ENOENT; 266 } else 267 return ret; 268 269 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, 270 0x2000, args->v0.pushbuf, 271 (1ULL << NVDEV_ENGINE_DMAOBJ) | 272 (1ULL << NVDEV_ENGINE_SW) | 273 (1ULL << NVDEV_ENGINE_GR) | 274 (1ULL << NVDEV_ENGINE_MPEG) | 275 (1ULL << NVDEV_ENGINE_ME) | 276 (1ULL << NVDEV_ENGINE_VP) | 277 (1ULL << NVDEV_ENGINE_CIPHER) | 278 (1ULL << NVDEV_ENGINE_SEC) | 279 (1ULL << NVDEV_ENGINE_BSP) | 280 (1ULL << NVDEV_ENGINE_MSVLD) | 281 (1ULL << NVDEV_ENGINE_MSPDEC) | 282 (1ULL << NVDEV_ENGINE_MSPPP) | 283 (1ULL << NVDEV_ENGINE_CE0) | 284 (1ULL << NVDEV_ENGINE_VIC), &chan); 285 *pobject = nv_object(chan); 286 if (ret) 287 return ret; 288 289 chan->base.inst = base->base.gpuobj.addr; 290 args->v0.chid = chan->base.chid; 291 292 ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj, 293 &chan->ramht); 294 if (ret) 295 return ret; 296 297 nv_parent(chan)->context_attach = g84_fifo_context_attach; 298 nv_parent(chan)->context_detach = g84_fifo_context_detach; 299 nv_parent(chan)->object_attach = g84_fifo_object_attach; 300 nv_parent(chan)->object_detach = nv50_fifo_object_detach; 301 302 ioffset = args->v0.ioffset; 303 ilength = order_base_2(args->v0.ilength / 8); 304 305 nvkm_kmap(base->ramfc); 306 nvkm_wo32(base->ramfc, 0x3c, 0x403f6078); 307 nvkm_wo32(base->ramfc, 0x44, 0x01003fff); 308 nvkm_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); 309 nvkm_wo32(base->ramfc, 0x50, lower_32_bits(ioffset)); 310 nvkm_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); 311 nvkm_wo32(base->ramfc, 0x60, 0x7fffffff); 312 nvkm_wo32(base->ramfc, 0x78, 0x00000000); 313 nvkm_wo32(base->ramfc, 0x7c, 0x30000001); 314 nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | 315 (4 << 24) /* SEARCH_FULL */ | 316 (chan->ramht->gpuobj->node->offset >> 4)); 317 nvkm_wo32(base->ramfc, 0x88, base->cache->addr >> 10); 318 nvkm_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12); 319 nvkm_done(base->ramfc); 320 return 0; 321 } 322 323 static int 324 g84_fifo_chan_init(struct nvkm_object *object) 325 { 326 struct nv50_fifo *fifo = (void *)object->engine; 327 struct nv50_fifo_base *base = (void *)object->parent; 328 struct nv50_fifo_chan *chan = (void *)object; 329 struct nvkm_gpuobj *ramfc = base->ramfc; 330 struct nvkm_device *device = fifo->base.engine.subdev.device; 331 u32 chid = chan->base.chid; 332 int ret; 333 334 ret = nvkm_fifo_channel_init(&chan->base); 335 if (ret) 336 return ret; 337 338 nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8); 339 nv50_fifo_playlist_update(fifo); 340 return 0; 341 } 342 343 static struct nvkm_ofuncs 344 g84_fifo_ofuncs_dma = { 345 .ctor = g84_fifo_chan_ctor_dma, 346 .dtor = nv50_fifo_chan_dtor, 347 .init = g84_fifo_chan_init, 348 .fini = nv50_fifo_chan_fini, 349 .map = _nvkm_fifo_channel_map, 350 .rd32 = _nvkm_fifo_channel_rd32, 351 .wr32 = _nvkm_fifo_channel_wr32, 352 .ntfy = _nvkm_fifo_channel_ntfy 353 }; 354 355 static struct nvkm_ofuncs 356 g84_fifo_ofuncs_ind = { 357 .ctor = g84_fifo_chan_ctor_ind, 358 .dtor = nv50_fifo_chan_dtor, 359 .init = g84_fifo_chan_init, 360 .fini = nv50_fifo_chan_fini, 361 .map = _nvkm_fifo_channel_map, 362 .rd32 = _nvkm_fifo_channel_rd32, 363 .wr32 = _nvkm_fifo_channel_wr32, 364 .ntfy = _nvkm_fifo_channel_ntfy 365 }; 366 367 static struct nvkm_oclass 368 g84_fifo_sclass[] = { 369 { G82_CHANNEL_DMA, &g84_fifo_ofuncs_dma }, 370 { G82_CHANNEL_GPFIFO, &g84_fifo_ofuncs_ind }, 371 {} 372 }; 373 374 /******************************************************************************* 375 * FIFO context - basically just the instmem reserved for the channel 376 ******************************************************************************/ 377 378 static int 379 g84_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 380 struct nvkm_oclass *oclass, void *data, u32 size, 381 struct nvkm_object **pobject) 382 { 383 struct nvkm_device *device = nv_engine(engine)->subdev.device; 384 struct nv50_fifo_base *base; 385 int ret; 386 387 ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000, 388 0x1000, NVOBJ_FLAG_HEAP, &base); 389 *pobject = nv_object(base); 390 if (ret) 391 return ret; 392 393 ret = nvkm_gpuobj_new(device, 0x0200, 0, true, &base->base.gpuobj, 394 &base->eng); 395 if (ret) 396 return ret; 397 398 ret = nvkm_gpuobj_new(device, 0x4000, 0, false, &base->base.gpuobj, 399 &base->pgd); 400 if (ret) 401 return ret; 402 403 ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); 404 if (ret) 405 return ret; 406 407 ret = nvkm_gpuobj_new(device, 0x1000, 0x400, true, &base->base.gpuobj, 408 &base->cache); 409 if (ret) 410 return ret; 411 412 ret = nvkm_gpuobj_new(device, 0x100, 0x100, true, &base->base.gpuobj, 413 &base->ramfc); 414 if (ret) 415 return ret; 416 417 return 0; 418 } 419 420 static struct nvkm_oclass 421 g84_fifo_cclass = { 422 .handle = NV_ENGCTX(FIFO, 0x84), 423 .ofuncs = &(struct nvkm_ofuncs) { 424 .ctor = g84_fifo_context_ctor, 425 .dtor = nv50_fifo_context_dtor, 426 .init = _nvkm_fifo_context_init, 427 .fini = _nvkm_fifo_context_fini, 428 .rd32 = _nvkm_fifo_context_rd32, 429 .wr32 = _nvkm_fifo_context_wr32, 430 }, 431 }; 432 433 /******************************************************************************* 434 * PFIFO engine 435 ******************************************************************************/ 436 437 static void 438 g84_fifo_uevent_init(struct nvkm_event *event, int type, int index) 439 { 440 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); 441 struct nvkm_device *device = fifo->engine.subdev.device; 442 nvkm_mask(device, 0x002140, 0x40000000, 0x40000000); 443 } 444 445 static void 446 g84_fifo_uevent_fini(struct nvkm_event *event, int type, int index) 447 { 448 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); 449 struct nvkm_device *device = fifo->engine.subdev.device; 450 nvkm_mask(device, 0x002140, 0x40000000, 0x00000000); 451 } 452 453 static const struct nvkm_event_func 454 g84_fifo_uevent_func = { 455 .ctor = nvkm_fifo_uevent_ctor, 456 .init = g84_fifo_uevent_init, 457 .fini = g84_fifo_uevent_fini, 458 }; 459 460 static int 461 g84_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 462 struct nvkm_oclass *oclass, void *data, u32 size, 463 struct nvkm_object **pobject) 464 { 465 struct nvkm_device *device = (void *)parent; 466 struct nv50_fifo *fifo; 467 int ret; 468 469 ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &fifo); 470 *pobject = nv_object(fifo); 471 if (ret) 472 return ret; 473 474 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000, 475 false, &fifo->playlist[0]); 476 if (ret) 477 return ret; 478 479 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000, 480 false, &fifo->playlist[1]); 481 if (ret) 482 return ret; 483 484 ret = nvkm_event_init(&g84_fifo_uevent_func, 1, 1, &fifo->base.uevent); 485 if (ret) 486 return ret; 487 488 nv_subdev(fifo)->unit = 0x00000100; 489 nv_subdev(fifo)->intr = nv04_fifo_intr; 490 nv_engine(fifo)->cclass = &g84_fifo_cclass; 491 nv_engine(fifo)->sclass = g84_fifo_sclass; 492 fifo->base.pause = nv04_fifo_pause; 493 fifo->base.start = nv04_fifo_start; 494 return 0; 495 } 496 497 struct nvkm_oclass * 498 g84_fifo_oclass = &(struct nvkm_oclass) { 499 .handle = NV_ENGINE(FIFO, 0x84), 500 .ofuncs = &(struct nvkm_ofuncs) { 501 .ctor = g84_fifo_ctor, 502 .dtor = nv50_fifo_dtor, 503 .init = nv50_fifo_init, 504 .fini = _nvkm_fifo_fini, 505 }, 506 }; 507