1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include <engine/falcon.h> 23 #include <engine/fifo.h> 24 25 #include <subdev/timer.h> 26 27 static void 28 nvkm_falcon_intr(struct nvkm_subdev *subdev) 29 { 30 struct nvkm_falcon *falcon = (void *)subdev; 31 struct nvkm_device *device = falcon->engine.subdev.device; 32 const u32 base = falcon->addr; 33 u32 dest = nvkm_rd32(device, base + 0x01c); 34 u32 intr = nvkm_rd32(device, base + 0x008) & dest & ~(dest >> 16); 35 u32 inst = nvkm_rd32(device, base + 0x050) & 0x3fffffff; 36 struct nvkm_fifo_chan *chan; 37 unsigned long flags; 38 39 chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags); 40 41 if (intr & 0x00000040) { 42 if (falcon->func->intr) { 43 falcon->func->intr(falcon, chan); 44 nvkm_wr32(device, base + 0x004, 0x00000040); 45 intr &= ~0x00000040; 46 } 47 } 48 49 if (intr & 0x00000010) { 50 nvkm_debug(subdev, "ucode halted\n"); 51 nvkm_wr32(device, base + 0x004, 0x00000010); 52 intr &= ~0x00000010; 53 } 54 55 if (intr) { 56 nvkm_error(subdev, "intr %08x\n", intr); 57 nvkm_wr32(device, base + 0x004, intr); 58 } 59 60 nvkm_fifo_chan_put(device->fifo, flags, &chan); 61 } 62 63 static void * 64 vmemdup(const void *src, size_t len) 65 { 66 void *p = vmalloc(len); 67 68 if (p) 69 memcpy(p, src, len); 70 return p; 71 } 72 73 int 74 _nvkm_falcon_init(struct nvkm_object *object) 75 { 76 struct nvkm_falcon *falcon = (void *)object; 77 struct nvkm_subdev *subdev = &falcon->engine.subdev; 78 struct nvkm_device *device = subdev->device; 79 const struct firmware *fw; 80 char name[32] = "internal"; 81 const u32 base = falcon->addr; 82 int ret, i; 83 u32 caps; 84 85 /* enable engine, and determine its capabilities */ 86 ret = nvkm_engine_init_old(&falcon->engine); 87 if (ret) 88 return ret; 89 90 if (device->chipset < 0xa3 || 91 device->chipset == 0xaa || device->chipset == 0xac) { 92 falcon->version = 0; 93 falcon->secret = (falcon->addr == 0x087000) ? 1 : 0; 94 } else { 95 caps = nvkm_rd32(device, base + 0x12c); 96 falcon->version = (caps & 0x0000000f); 97 falcon->secret = (caps & 0x00000030) >> 4; 98 } 99 100 caps = nvkm_rd32(device, base + 0x108); 101 falcon->code.limit = (caps & 0x000001ff) << 8; 102 falcon->data.limit = (caps & 0x0003fe00) >> 1; 103 104 nvkm_debug(subdev, "falcon version: %d\n", falcon->version); 105 nvkm_debug(subdev, "secret level: %d\n", falcon->secret); 106 nvkm_debug(subdev, "code limit: %d\n", falcon->code.limit); 107 nvkm_debug(subdev, "data limit: %d\n", falcon->data.limit); 108 109 /* wait for 'uc halted' to be signalled before continuing */ 110 if (falcon->secret && falcon->version < 4) { 111 if (!falcon->version) { 112 nvkm_msec(device, 2000, 113 if (nvkm_rd32(device, base + 0x008) & 0x00000010) 114 break; 115 ); 116 } else { 117 nvkm_msec(device, 2000, 118 if (!(nvkm_rd32(device, base + 0x180) & 0x80000000)) 119 break; 120 ); 121 } 122 nvkm_wr32(device, base + 0x004, 0x00000010); 123 } 124 125 /* disable all interrupts */ 126 nvkm_wr32(device, base + 0x014, 0xffffffff); 127 128 /* no default ucode provided by the engine implementation, try and 129 * locate a "self-bootstrapping" firmware image for the engine 130 */ 131 if (!falcon->code.data) { 132 snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03x", 133 device->chipset, falcon->addr >> 12); 134 135 ret = request_firmware(&fw, name, nv_device_base(device)); 136 if (ret == 0) { 137 falcon->code.data = vmemdup(fw->data, fw->size); 138 falcon->code.size = fw->size; 139 falcon->data.data = NULL; 140 falcon->data.size = 0; 141 release_firmware(fw); 142 } 143 144 falcon->external = true; 145 } 146 147 /* next step is to try and load "static code/data segment" firmware 148 * images for the engine 149 */ 150 if (!falcon->code.data) { 151 snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xd", 152 device->chipset, falcon->addr >> 12); 153 154 ret = request_firmware(&fw, name, nv_device_base(device)); 155 if (ret) { 156 nvkm_error(subdev, "unable to load firmware data\n"); 157 return -ENODEV; 158 } 159 160 falcon->data.data = vmemdup(fw->data, fw->size); 161 falcon->data.size = fw->size; 162 release_firmware(fw); 163 if (!falcon->data.data) 164 return -ENOMEM; 165 166 snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xc", 167 device->chipset, falcon->addr >> 12); 168 169 ret = request_firmware(&fw, name, nv_device_base(device)); 170 if (ret) { 171 nvkm_error(subdev, "unable to load firmware code\n"); 172 return -ENODEV; 173 } 174 175 falcon->code.data = vmemdup(fw->data, fw->size); 176 falcon->code.size = fw->size; 177 release_firmware(fw); 178 if (!falcon->code.data) 179 return -ENOMEM; 180 } 181 182 nvkm_debug(subdev, "firmware: %s (%s)\n", name, falcon->data.data ? 183 "static code/data segments" : "self-bootstrapping"); 184 185 /* ensure any "self-bootstrapping" firmware image is in vram */ 186 if (!falcon->data.data && !falcon->core) { 187 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 188 falcon->code.size, 256, false, 189 &falcon->core); 190 if (ret) { 191 nvkm_error(subdev, "core allocation failed, %d\n", ret); 192 return ret; 193 } 194 195 nvkm_kmap(falcon->core); 196 for (i = 0; i < falcon->code.size; i += 4) 197 nvkm_wo32(falcon->core, i, falcon->code.data[i / 4]); 198 nvkm_done(falcon->core); 199 } 200 201 /* upload firmware bootloader (or the full code segments) */ 202 if (falcon->core) { 203 u64 addr = nvkm_memory_addr(falcon->core); 204 if (device->card_type < NV_C0) 205 nvkm_wr32(device, base + 0x618, 0x04000000); 206 else 207 nvkm_wr32(device, base + 0x618, 0x00000114); 208 nvkm_wr32(device, base + 0x11c, 0); 209 nvkm_wr32(device, base + 0x110, addr >> 8); 210 nvkm_wr32(device, base + 0x114, 0); 211 nvkm_wr32(device, base + 0x118, 0x00006610); 212 } else { 213 if (falcon->code.size > falcon->code.limit || 214 falcon->data.size > falcon->data.limit) { 215 nvkm_error(subdev, "ucode exceeds falcon limit(s)\n"); 216 return -EINVAL; 217 } 218 219 if (falcon->version < 3) { 220 nvkm_wr32(device, base + 0xff8, 0x00100000); 221 for (i = 0; i < falcon->code.size / 4; i++) 222 nvkm_wr32(device, base + 0xff4, falcon->code.data[i]); 223 } else { 224 nvkm_wr32(device, base + 0x180, 0x01000000); 225 for (i = 0; i < falcon->code.size / 4; i++) { 226 if ((i & 0x3f) == 0) 227 nvkm_wr32(device, base + 0x188, i >> 6); 228 nvkm_wr32(device, base + 0x184, falcon->code.data[i]); 229 } 230 } 231 } 232 233 /* upload data segment (if necessary), zeroing the remainder */ 234 if (falcon->version < 3) { 235 nvkm_wr32(device, base + 0xff8, 0x00000000); 236 for (i = 0; !falcon->core && i < falcon->data.size / 4; i++) 237 nvkm_wr32(device, base + 0xff4, falcon->data.data[i]); 238 for (; i < falcon->data.limit; i += 4) 239 nvkm_wr32(device, base + 0xff4, 0x00000000); 240 } else { 241 nvkm_wr32(device, base + 0x1c0, 0x01000000); 242 for (i = 0; !falcon->core && i < falcon->data.size / 4; i++) 243 nvkm_wr32(device, base + 0x1c4, falcon->data.data[i]); 244 for (; i < falcon->data.limit / 4; i++) 245 nvkm_wr32(device, base + 0x1c4, 0x00000000); 246 } 247 248 /* start it running */ 249 nvkm_wr32(device, base + 0x10c, 0x00000001); /* BLOCK_ON_FIFO */ 250 nvkm_wr32(device, base + 0x104, 0x00000000); /* ENTRY */ 251 nvkm_wr32(device, base + 0x100, 0x00000002); /* TRIGGER */ 252 nvkm_wr32(device, base + 0x048, 0x00000003); /* FIFO | CHSW */ 253 return 0; 254 } 255 256 int 257 _nvkm_falcon_fini(struct nvkm_object *object, bool suspend) 258 { 259 struct nvkm_falcon *falcon = (void *)object; 260 struct nvkm_device *device = falcon->engine.subdev.device; 261 const u32 base = falcon->addr; 262 263 if (!suspend) { 264 nvkm_memory_del(&falcon->core); 265 if (falcon->external) { 266 vfree(falcon->data.data); 267 vfree(falcon->code.data); 268 falcon->code.data = NULL; 269 } 270 } 271 272 nvkm_mask(device, base + 0x048, 0x00000003, 0x00000000); 273 nvkm_wr32(device, base + 0x014, 0xffffffff); 274 275 return nvkm_engine_fini_old(&falcon->engine, suspend); 276 } 277 278 int 279 nvkm_falcon_create_(const struct nvkm_falcon_func *func, 280 struct nvkm_object *parent, struct nvkm_object *engine, 281 struct nvkm_oclass *oclass, u32 addr, bool enable, 282 const char *iname, const char *fname, 283 int length, void **pobject) 284 { 285 struct nvkm_falcon *falcon; 286 int ret; 287 288 ret = nvkm_engine_create_(parent, engine, oclass, enable, iname, 289 fname, length, pobject); 290 falcon = *pobject; 291 if (ret) 292 return ret; 293 294 falcon->engine.subdev.intr = nvkm_falcon_intr; 295 falcon->func = func; 296 falcon->addr = addr; 297 return 0; 298 } 299