1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #define nv50_dmaobj(p) container_of((p), struct nv50_dmaobj, base)
25 #include "user.h"
26 
27 #include <core/client.h>
28 #include <core/gpuobj.h>
29 #include <subdev/fb.h>
30 
31 #include <nvif/cl0002.h>
32 #include <nvif/unpack.h>
33 
34 struct nv50_dmaobj {
35 	struct nvkm_dmaobj base;
36 	u32 flags0;
37 	u32 flags5;
38 };
39 
40 static int
41 nv50_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent,
42 		 int align, struct nvkm_gpuobj **pgpuobj)
43 {
44 	struct nv50_dmaobj *dmaobj = nv50_dmaobj(base);
45 	struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
46 	int ret;
47 
48 	ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj);
49 	if (ret == 0) {
50 		nvkm_kmap(*pgpuobj);
51 		nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
52 		nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));
53 		nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));
54 		nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |
55 					  upper_32_bits(dmaobj->base.start));
56 		nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
57 		nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5);
58 		nvkm_done(*pgpuobj);
59 	}
60 
61 	return ret;
62 }
63 
64 static const struct nvkm_dmaobj_func
65 nv50_dmaobj_func = {
66 	.bind = nv50_dmaobj_bind,
67 };
68 
69 int
70 nv50_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
71 		void *data, u32 size, struct nvkm_dmaobj **pdmaobj)
72 {
73 	union {
74 		struct nv50_dma_v0 v0;
75 	} *args;
76 	struct nvkm_object *parent = oclass->parent;
77 	struct nv50_dmaobj *dmaobj;
78 	u32 user, part, comp, kind;
79 	int ret;
80 
81 	if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL)))
82 		return -ENOMEM;
83 	*pdmaobj = &dmaobj->base;
84 
85 	ret = nvkm_dmaobj_ctor(&nv50_dmaobj_func, dma, oclass,
86 			       &data, &size, &dmaobj->base);
87 	if (ret)
88 		return ret;
89 
90 	ret  = -ENOSYS;
91 	args = data;
92 
93 	nvif_ioctl(parent, "create nv50 dma size %d\n", size);
94 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
95 		nvif_ioctl(parent, "create nv50 dma vers %d priv %d part %d "
96 				   "comp %d kind %02x\n", args->v0.version,
97 			   args->v0.priv, args->v0.part, args->v0.comp,
98 			   args->v0.kind);
99 		user = args->v0.priv;
100 		part = args->v0.part;
101 		comp = args->v0.comp;
102 		kind = args->v0.kind;
103 	} else
104 	if (size == 0) {
105 		if (dmaobj->base.target != NV_MEM_TARGET_VM) {
106 			user = NV50_DMA_V0_PRIV_US;
107 			part = NV50_DMA_V0_PART_256;
108 			comp = NV50_DMA_V0_COMP_NONE;
109 			kind = NV50_DMA_V0_KIND_PITCH;
110 		} else {
111 			user = NV50_DMA_V0_PRIV_VM;
112 			part = NV50_DMA_V0_PART_VM;
113 			comp = NV50_DMA_V0_COMP_VM;
114 			kind = NV50_DMA_V0_KIND_VM;
115 		}
116 	} else
117 		return ret;
118 
119 	if (user > 2 || part > 2 || comp > 3 || kind > 0x7f)
120 		return -EINVAL;
121 	dmaobj->flags0 = (comp << 29) | (kind << 22) | (user << 20) |
122 			 oclass->base.oclass;
123 	dmaobj->flags5 = (part << 16);
124 
125 	switch (dmaobj->base.target) {
126 	case NV_MEM_TARGET_VM:
127 		dmaobj->flags0 |= 0x00000000;
128 		break;
129 	case NV_MEM_TARGET_VRAM:
130 		dmaobj->flags0 |= 0x00010000;
131 		break;
132 	case NV_MEM_TARGET_PCI:
133 		dmaobj->flags0 |= 0x00020000;
134 		break;
135 	case NV_MEM_TARGET_PCI_NOSNOOP:
136 		dmaobj->flags0 |= 0x00030000;
137 		break;
138 	default:
139 		return -EINVAL;
140 	}
141 
142 	switch (dmaobj->base.access) {
143 	case NV_MEM_ACCESS_VM:
144 		break;
145 	case NV_MEM_ACCESS_RO:
146 		dmaobj->flags0 |= 0x00040000;
147 		break;
148 	case NV_MEM_ACCESS_WO:
149 	case NV_MEM_ACCESS_RW:
150 		dmaobj->flags0 |= 0x00080000;
151 		break;
152 	default:
153 		return -EINVAL;
154 	}
155 
156 	return 0;
157 }
158