1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 #include "outp.h" 26 #include "outpdp.h" 27 28 #include <core/client.h> 29 #include <core/engctx.h> 30 #include <core/enum.h> 31 #include <core/handle.h> 32 #include <core/ramht.h> 33 #include <engine/dmaobj.h> 34 #include <subdev/bios.h> 35 #include <subdev/bios/dcb.h> 36 #include <subdev/bios/disp.h> 37 #include <subdev/bios/init.h> 38 #include <subdev/bios/pll.h> 39 #include <subdev/devinit.h> 40 #include <subdev/fb.h> 41 #include <subdev/timer.h> 42 43 #include <nvif/class.h> 44 #include <nvif/event.h> 45 #include <nvif/unpack.h> 46 47 /******************************************************************************* 48 * EVO channel base class 49 ******************************************************************************/ 50 51 static int 52 nv50_disp_chan_create_(struct nvkm_object *parent, 53 struct nvkm_object *engine, 54 struct nvkm_oclass *oclass, int head, 55 int length, void **pobject) 56 { 57 const struct nv50_disp_chan_impl *impl = (void *)oclass->ofuncs; 58 struct nv50_disp_base *base = (void *)parent; 59 struct nv50_disp_chan *chan; 60 int chid = impl->chid + head; 61 int ret; 62 63 if (base->chan & (1 << chid)) 64 return -EBUSY; 65 base->chan |= (1 << chid); 66 67 ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL, 68 (1ULL << NVDEV_ENGINE_DMAOBJ), 69 length, pobject); 70 chan = *pobject; 71 if (ret) 72 return ret; 73 chan->chid = chid; 74 75 nv_parent(chan)->object_attach = impl->attach; 76 nv_parent(chan)->object_detach = impl->detach; 77 return 0; 78 } 79 80 static void 81 nv50_disp_chan_destroy(struct nv50_disp_chan *chan) 82 { 83 struct nv50_disp_base *base = (void *)nv_object(chan)->parent; 84 base->chan &= ~(1 << chan->chid); 85 nvkm_namedb_destroy(&chan->base); 86 } 87 88 static void 89 nv50_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index) 90 { 91 struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent); 92 nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000000 << index); 93 nv_wr32(priv, 0x610020, 0x00000001 << index); 94 } 95 96 static void 97 nv50_disp_chan_uevent_init(struct nvkm_event *event, int types, int index) 98 { 99 struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent); 100 nv_wr32(priv, 0x610020, 0x00000001 << index); 101 nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000001 << index); 102 } 103 104 void 105 nv50_disp_chan_uevent_send(struct nv50_disp_priv *priv, int chid) 106 { 107 struct nvif_notify_uevent_rep { 108 } rep; 109 110 nvkm_event_send(&priv->uevent, 1, chid, &rep, sizeof(rep)); 111 } 112 113 int 114 nv50_disp_chan_uevent_ctor(struct nvkm_object *object, void *data, u32 size, 115 struct nvkm_notify *notify) 116 { 117 struct nv50_disp_dmac *dmac = (void *)object; 118 union { 119 struct nvif_notify_uevent_req none; 120 } *args = data; 121 int ret; 122 123 if (nvif_unvers(args->none)) { 124 notify->size = sizeof(struct nvif_notify_uevent_rep); 125 notify->types = 1; 126 notify->index = dmac->base.chid; 127 return 0; 128 } 129 130 return ret; 131 } 132 133 const struct nvkm_event_func 134 nv50_disp_chan_uevent = { 135 .ctor = nv50_disp_chan_uevent_ctor, 136 .init = nv50_disp_chan_uevent_init, 137 .fini = nv50_disp_chan_uevent_fini, 138 }; 139 140 int 141 nv50_disp_chan_ntfy(struct nvkm_object *object, u32 type, 142 struct nvkm_event **pevent) 143 { 144 struct nv50_disp_priv *priv = (void *)object->engine; 145 switch (type) { 146 case NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT: 147 *pevent = &priv->uevent; 148 return 0; 149 default: 150 break; 151 } 152 return -EINVAL; 153 } 154 155 int 156 nv50_disp_chan_map(struct nvkm_object *object, u64 *addr, u32 *size) 157 { 158 struct nv50_disp_chan *chan = (void *)object; 159 *addr = nv_device_resource_start(nv_device(object), 0) + 160 0x640000 + (chan->chid * 0x1000); 161 *size = 0x001000; 162 return 0; 163 } 164 165 u32 166 nv50_disp_chan_rd32(struct nvkm_object *object, u64 addr) 167 { 168 struct nv50_disp_priv *priv = (void *)object->engine; 169 struct nv50_disp_chan *chan = (void *)object; 170 return nv_rd32(priv, 0x640000 + (chan->chid * 0x1000) + addr); 171 } 172 173 void 174 nv50_disp_chan_wr32(struct nvkm_object *object, u64 addr, u32 data) 175 { 176 struct nv50_disp_priv *priv = (void *)object->engine; 177 struct nv50_disp_chan *chan = (void *)object; 178 nv_wr32(priv, 0x640000 + (chan->chid * 0x1000) + addr, data); 179 } 180 181 /******************************************************************************* 182 * EVO DMA channel base class 183 ******************************************************************************/ 184 185 static int 186 nv50_disp_dmac_object_attach(struct nvkm_object *parent, 187 struct nvkm_object *object, u32 name) 188 { 189 struct nv50_disp_base *base = (void *)parent->parent; 190 struct nv50_disp_chan *chan = (void *)parent; 191 u32 addr = nv_gpuobj(object)->node->offset; 192 u32 chid = chan->chid; 193 u32 data = (chid << 28) | (addr << 10) | chid; 194 return nvkm_ramht_insert(base->ramht, chid, name, data); 195 } 196 197 static void 198 nv50_disp_dmac_object_detach(struct nvkm_object *parent, int cookie) 199 { 200 struct nv50_disp_base *base = (void *)parent->parent; 201 nvkm_ramht_remove(base->ramht, cookie); 202 } 203 204 static int 205 nv50_disp_dmac_create_(struct nvkm_object *parent, 206 struct nvkm_object *engine, 207 struct nvkm_oclass *oclass, u32 pushbuf, int head, 208 int length, void **pobject) 209 { 210 struct nv50_disp_dmac *dmac; 211 int ret; 212 213 ret = nv50_disp_chan_create_(parent, engine, oclass, head, 214 length, pobject); 215 dmac = *pobject; 216 if (ret) 217 return ret; 218 219 dmac->pushdma = (void *)nvkm_handle_ref(parent, pushbuf); 220 if (!dmac->pushdma) 221 return -ENOENT; 222 223 switch (nv_mclass(dmac->pushdma)) { 224 case 0x0002: 225 case 0x003d: 226 if (dmac->pushdma->limit - dmac->pushdma->start != 0xfff) 227 return -EINVAL; 228 229 switch (dmac->pushdma->target) { 230 case NV_MEM_TARGET_VRAM: 231 dmac->push = 0x00000001 | dmac->pushdma->start >> 8; 232 break; 233 case NV_MEM_TARGET_PCI_NOSNOOP: 234 dmac->push = 0x00000003 | dmac->pushdma->start >> 8; 235 break; 236 default: 237 return -EINVAL; 238 } 239 break; 240 default: 241 return -EINVAL; 242 } 243 244 return 0; 245 } 246 247 void 248 nv50_disp_dmac_dtor(struct nvkm_object *object) 249 { 250 struct nv50_disp_dmac *dmac = (void *)object; 251 nvkm_object_ref(NULL, (struct nvkm_object **)&dmac->pushdma); 252 nv50_disp_chan_destroy(&dmac->base); 253 } 254 255 static int 256 nv50_disp_dmac_init(struct nvkm_object *object) 257 { 258 struct nv50_disp_priv *priv = (void *)object->engine; 259 struct nv50_disp_dmac *dmac = (void *)object; 260 int chid = dmac->base.chid; 261 int ret; 262 263 ret = nv50_disp_chan_init(&dmac->base); 264 if (ret) 265 return ret; 266 267 /* enable error reporting */ 268 nv_mask(priv, 0x610028, 0x00010000 << chid, 0x00010000 << chid); 269 270 /* initialise channel for dma command submission */ 271 nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push); 272 nv_wr32(priv, 0x610208 + (chid * 0x0010), 0x00010000); 273 nv_wr32(priv, 0x61020c + (chid * 0x0010), chid); 274 nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010); 275 nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000); 276 nv_wr32(priv, 0x610200 + (chid * 0x0010), 0x00000013); 277 278 /* wait for it to go inactive */ 279 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x80000000, 0x00000000)) { 280 nv_error(dmac, "init timeout, 0x%08x\n", 281 nv_rd32(priv, 0x610200 + (chid * 0x10))); 282 return -EBUSY; 283 } 284 285 return 0; 286 } 287 288 static int 289 nv50_disp_dmac_fini(struct nvkm_object *object, bool suspend) 290 { 291 struct nv50_disp_priv *priv = (void *)object->engine; 292 struct nv50_disp_dmac *dmac = (void *)object; 293 int chid = dmac->base.chid; 294 295 /* deactivate channel */ 296 nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000); 297 nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000); 298 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x001e0000, 0x00000000)) { 299 nv_error(dmac, "fini timeout, 0x%08x\n", 300 nv_rd32(priv, 0x610200 + (chid * 0x10))); 301 if (suspend) 302 return -EBUSY; 303 } 304 305 /* disable error reporting and completion notifications */ 306 nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid); 307 308 return nv50_disp_chan_fini(&dmac->base, suspend); 309 } 310 311 /******************************************************************************* 312 * EVO master channel object 313 ******************************************************************************/ 314 315 static void 316 nv50_disp_mthd_list(struct nv50_disp_priv *priv, int debug, u32 base, int c, 317 const struct nv50_disp_mthd_list *list, int inst) 318 { 319 struct nvkm_object *disp = nv_object(priv); 320 int i; 321 322 for (i = 0; list->data[i].mthd; i++) { 323 if (list->data[i].addr) { 324 u32 next = nv_rd32(priv, list->data[i].addr + base + 0); 325 u32 prev = nv_rd32(priv, list->data[i].addr + base + c); 326 u32 mthd = list->data[i].mthd + (list->mthd * inst); 327 const char *name = list->data[i].name; 328 char mods[16]; 329 330 if (prev != next) 331 snprintf(mods, sizeof(mods), "-> 0x%08x", next); 332 else 333 snprintf(mods, sizeof(mods), "%13c", ' '); 334 335 nv_printk_(disp, debug, "\t0x%04x: 0x%08x %s%s%s\n", 336 mthd, prev, mods, name ? " // " : "", 337 name ? name : ""); 338 } 339 } 340 } 341 342 void 343 nv50_disp_mthd_chan(struct nv50_disp_priv *priv, int debug, int head, 344 const struct nv50_disp_mthd_chan *chan) 345 { 346 struct nvkm_object *disp = nv_object(priv); 347 const struct nv50_disp_impl *impl = (void *)disp->oclass; 348 const struct nv50_disp_mthd_list *list; 349 int i, j; 350 351 if (debug > nv_subdev(priv)->debug) 352 return; 353 354 for (i = 0; (list = chan->data[i].mthd) != NULL; i++) { 355 u32 base = head * chan->addr; 356 for (j = 0; j < chan->data[i].nr; j++, base += list->addr) { 357 const char *cname = chan->name; 358 const char *sname = ""; 359 char cname_[16], sname_[16]; 360 361 if (chan->addr) { 362 snprintf(cname_, sizeof(cname_), "%s %d", 363 chan->name, head); 364 cname = cname_; 365 } 366 367 if (chan->data[i].nr > 1) { 368 snprintf(sname_, sizeof(sname_), " - %s %d", 369 chan->data[i].name, j); 370 sname = sname_; 371 } 372 373 nv_printk_(disp, debug, "%s%s:\n", cname, sname); 374 nv50_disp_mthd_list(priv, debug, base, impl->mthd.prev, 375 list, j); 376 } 377 } 378 } 379 380 const struct nv50_disp_mthd_list 381 nv50_disp_core_mthd_base = { 382 .mthd = 0x0000, 383 .addr = 0x000000, 384 .data = { 385 { 0x0080, 0x000000 }, 386 { 0x0084, 0x610bb8 }, 387 { 0x0088, 0x610b9c }, 388 { 0x008c, 0x000000 }, 389 {} 390 } 391 }; 392 393 static const struct nv50_disp_mthd_list 394 nv50_disp_core_mthd_dac = { 395 .mthd = 0x0080, 396 .addr = 0x000008, 397 .data = { 398 { 0x0400, 0x610b58 }, 399 { 0x0404, 0x610bdc }, 400 { 0x0420, 0x610828 }, 401 {} 402 } 403 }; 404 405 const struct nv50_disp_mthd_list 406 nv50_disp_core_mthd_sor = { 407 .mthd = 0x0040, 408 .addr = 0x000008, 409 .data = { 410 { 0x0600, 0x610b70 }, 411 {} 412 } 413 }; 414 415 const struct nv50_disp_mthd_list 416 nv50_disp_core_mthd_pior = { 417 .mthd = 0x0040, 418 .addr = 0x000008, 419 .data = { 420 { 0x0700, 0x610b80 }, 421 {} 422 } 423 }; 424 425 static const struct nv50_disp_mthd_list 426 nv50_disp_core_mthd_head = { 427 .mthd = 0x0400, 428 .addr = 0x000540, 429 .data = { 430 { 0x0800, 0x610ad8 }, 431 { 0x0804, 0x610ad0 }, 432 { 0x0808, 0x610a48 }, 433 { 0x080c, 0x610a78 }, 434 { 0x0810, 0x610ac0 }, 435 { 0x0814, 0x610af8 }, 436 { 0x0818, 0x610b00 }, 437 { 0x081c, 0x610ae8 }, 438 { 0x0820, 0x610af0 }, 439 { 0x0824, 0x610b08 }, 440 { 0x0828, 0x610b10 }, 441 { 0x082c, 0x610a68 }, 442 { 0x0830, 0x610a60 }, 443 { 0x0834, 0x000000 }, 444 { 0x0838, 0x610a40 }, 445 { 0x0840, 0x610a24 }, 446 { 0x0844, 0x610a2c }, 447 { 0x0848, 0x610aa8 }, 448 { 0x084c, 0x610ab0 }, 449 { 0x0860, 0x610a84 }, 450 { 0x0864, 0x610a90 }, 451 { 0x0868, 0x610b18 }, 452 { 0x086c, 0x610b20 }, 453 { 0x0870, 0x610ac8 }, 454 { 0x0874, 0x610a38 }, 455 { 0x0880, 0x610a58 }, 456 { 0x0884, 0x610a9c }, 457 { 0x08a0, 0x610a70 }, 458 { 0x08a4, 0x610a50 }, 459 { 0x08a8, 0x610ae0 }, 460 { 0x08c0, 0x610b28 }, 461 { 0x08c4, 0x610b30 }, 462 { 0x08c8, 0x610b40 }, 463 { 0x08d4, 0x610b38 }, 464 { 0x08d8, 0x610b48 }, 465 { 0x08dc, 0x610b50 }, 466 { 0x0900, 0x610a18 }, 467 { 0x0904, 0x610ab8 }, 468 {} 469 } 470 }; 471 472 static const struct nv50_disp_mthd_chan 473 nv50_disp_core_mthd_chan = { 474 .name = "Core", 475 .addr = 0x000000, 476 .data = { 477 { "Global", 1, &nv50_disp_core_mthd_base }, 478 { "DAC", 3, &nv50_disp_core_mthd_dac }, 479 { "SOR", 2, &nv50_disp_core_mthd_sor }, 480 { "PIOR", 3, &nv50_disp_core_mthd_pior }, 481 { "HEAD", 2, &nv50_disp_core_mthd_head }, 482 {} 483 } 484 }; 485 486 int 487 nv50_disp_core_ctor(struct nvkm_object *parent, 488 struct nvkm_object *engine, 489 struct nvkm_oclass *oclass, void *data, u32 size, 490 struct nvkm_object **pobject) 491 { 492 union { 493 struct nv50_disp_core_channel_dma_v0 v0; 494 } *args = data; 495 struct nv50_disp_dmac *mast; 496 int ret; 497 498 nv_ioctl(parent, "create disp core channel dma size %d\n", size); 499 if (nvif_unpack(args->v0, 0, 0, false)) { 500 nv_ioctl(parent, "create disp core channel dma vers %d " 501 "pushbuf %08x\n", 502 args->v0.version, args->v0.pushbuf); 503 } else 504 return ret; 505 506 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf, 507 0, sizeof(*mast), (void **)&mast); 508 *pobject = nv_object(mast); 509 if (ret) 510 return ret; 511 512 return 0; 513 } 514 515 static int 516 nv50_disp_core_init(struct nvkm_object *object) 517 { 518 struct nv50_disp_priv *priv = (void *)object->engine; 519 struct nv50_disp_dmac *mast = (void *)object; 520 int ret; 521 522 ret = nv50_disp_chan_init(&mast->base); 523 if (ret) 524 return ret; 525 526 /* enable error reporting */ 527 nv_mask(priv, 0x610028, 0x00010000, 0x00010000); 528 529 /* attempt to unstick channel from some unknown state */ 530 if ((nv_rd32(priv, 0x610200) & 0x009f0000) == 0x00020000) 531 nv_mask(priv, 0x610200, 0x00800000, 0x00800000); 532 if ((nv_rd32(priv, 0x610200) & 0x003f0000) == 0x00030000) 533 nv_mask(priv, 0x610200, 0x00600000, 0x00600000); 534 535 /* initialise channel for dma command submission */ 536 nv_wr32(priv, 0x610204, mast->push); 537 nv_wr32(priv, 0x610208, 0x00010000); 538 nv_wr32(priv, 0x61020c, 0x00000000); 539 nv_mask(priv, 0x610200, 0x00000010, 0x00000010); 540 nv_wr32(priv, 0x640000, 0x00000000); 541 nv_wr32(priv, 0x610200, 0x01000013); 542 543 /* wait for it to go inactive */ 544 if (!nv_wait(priv, 0x610200, 0x80000000, 0x00000000)) { 545 nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610200)); 546 return -EBUSY; 547 } 548 549 return 0; 550 } 551 552 static int 553 nv50_disp_core_fini(struct nvkm_object *object, bool suspend) 554 { 555 struct nv50_disp_priv *priv = (void *)object->engine; 556 struct nv50_disp_dmac *mast = (void *)object; 557 558 /* deactivate channel */ 559 nv_mask(priv, 0x610200, 0x00000010, 0x00000000); 560 nv_mask(priv, 0x610200, 0x00000003, 0x00000000); 561 if (!nv_wait(priv, 0x610200, 0x001e0000, 0x00000000)) { 562 nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610200)); 563 if (suspend) 564 return -EBUSY; 565 } 566 567 /* disable error reporting and completion notifications */ 568 nv_mask(priv, 0x610028, 0x00010001, 0x00000000); 569 570 return nv50_disp_chan_fini(&mast->base, suspend); 571 } 572 573 struct nv50_disp_chan_impl 574 nv50_disp_core_ofuncs = { 575 .base.ctor = nv50_disp_core_ctor, 576 .base.dtor = nv50_disp_dmac_dtor, 577 .base.init = nv50_disp_core_init, 578 .base.fini = nv50_disp_core_fini, 579 .base.map = nv50_disp_chan_map, 580 .base.ntfy = nv50_disp_chan_ntfy, 581 .base.rd32 = nv50_disp_chan_rd32, 582 .base.wr32 = nv50_disp_chan_wr32, 583 .chid = 0, 584 .attach = nv50_disp_dmac_object_attach, 585 .detach = nv50_disp_dmac_object_detach, 586 }; 587 588 /******************************************************************************* 589 * EVO sync channel objects 590 ******************************************************************************/ 591 592 static const struct nv50_disp_mthd_list 593 nv50_disp_base_mthd_base = { 594 .mthd = 0x0000, 595 .addr = 0x000000, 596 .data = { 597 { 0x0080, 0x000000 }, 598 { 0x0084, 0x0008c4 }, 599 { 0x0088, 0x0008d0 }, 600 { 0x008c, 0x0008dc }, 601 { 0x0090, 0x0008e4 }, 602 { 0x0094, 0x610884 }, 603 { 0x00a0, 0x6108a0 }, 604 { 0x00a4, 0x610878 }, 605 { 0x00c0, 0x61086c }, 606 { 0x00e0, 0x610858 }, 607 { 0x00e4, 0x610860 }, 608 { 0x00e8, 0x6108ac }, 609 { 0x00ec, 0x6108b4 }, 610 { 0x0100, 0x610894 }, 611 { 0x0110, 0x6108bc }, 612 { 0x0114, 0x61088c }, 613 {} 614 } 615 }; 616 617 const struct nv50_disp_mthd_list 618 nv50_disp_base_mthd_image = { 619 .mthd = 0x0400, 620 .addr = 0x000000, 621 .data = { 622 { 0x0800, 0x6108f0 }, 623 { 0x0804, 0x6108fc }, 624 { 0x0808, 0x61090c }, 625 { 0x080c, 0x610914 }, 626 { 0x0810, 0x610904 }, 627 {} 628 } 629 }; 630 631 static const struct nv50_disp_mthd_chan 632 nv50_disp_base_mthd_chan = { 633 .name = "Base", 634 .addr = 0x000540, 635 .data = { 636 { "Global", 1, &nv50_disp_base_mthd_base }, 637 { "Image", 2, &nv50_disp_base_mthd_image }, 638 {} 639 } 640 }; 641 642 int 643 nv50_disp_base_ctor(struct nvkm_object *parent, 644 struct nvkm_object *engine, 645 struct nvkm_oclass *oclass, void *data, u32 size, 646 struct nvkm_object **pobject) 647 { 648 union { 649 struct nv50_disp_base_channel_dma_v0 v0; 650 } *args = data; 651 struct nv50_disp_priv *priv = (void *)engine; 652 struct nv50_disp_dmac *dmac; 653 int ret; 654 655 nv_ioctl(parent, "create disp base channel dma size %d\n", size); 656 if (nvif_unpack(args->v0, 0, 0, false)) { 657 nv_ioctl(parent, "create disp base channel dma vers %d " 658 "pushbuf %08x head %d\n", 659 args->v0.version, args->v0.pushbuf, args->v0.head); 660 if (args->v0.head > priv->head.nr) 661 return -EINVAL; 662 } else 663 return ret; 664 665 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf, 666 args->v0.head, sizeof(*dmac), 667 (void **)&dmac); 668 *pobject = nv_object(dmac); 669 if (ret) 670 return ret; 671 672 return 0; 673 } 674 675 struct nv50_disp_chan_impl 676 nv50_disp_base_ofuncs = { 677 .base.ctor = nv50_disp_base_ctor, 678 .base.dtor = nv50_disp_dmac_dtor, 679 .base.init = nv50_disp_dmac_init, 680 .base.fini = nv50_disp_dmac_fini, 681 .base.ntfy = nv50_disp_chan_ntfy, 682 .base.map = nv50_disp_chan_map, 683 .base.rd32 = nv50_disp_chan_rd32, 684 .base.wr32 = nv50_disp_chan_wr32, 685 .chid = 1, 686 .attach = nv50_disp_dmac_object_attach, 687 .detach = nv50_disp_dmac_object_detach, 688 }; 689 690 /******************************************************************************* 691 * EVO overlay channel objects 692 ******************************************************************************/ 693 694 const struct nv50_disp_mthd_list 695 nv50_disp_ovly_mthd_base = { 696 .mthd = 0x0000, 697 .addr = 0x000000, 698 .data = { 699 { 0x0080, 0x000000 }, 700 { 0x0084, 0x0009a0 }, 701 { 0x0088, 0x0009c0 }, 702 { 0x008c, 0x0009c8 }, 703 { 0x0090, 0x6109b4 }, 704 { 0x0094, 0x610970 }, 705 { 0x00a0, 0x610998 }, 706 { 0x00a4, 0x610964 }, 707 { 0x00c0, 0x610958 }, 708 { 0x00e0, 0x6109a8 }, 709 { 0x00e4, 0x6109d0 }, 710 { 0x00e8, 0x6109d8 }, 711 { 0x0100, 0x61094c }, 712 { 0x0104, 0x610984 }, 713 { 0x0108, 0x61098c }, 714 { 0x0800, 0x6109f8 }, 715 { 0x0808, 0x610a08 }, 716 { 0x080c, 0x610a10 }, 717 { 0x0810, 0x610a00 }, 718 {} 719 } 720 }; 721 722 static const struct nv50_disp_mthd_chan 723 nv50_disp_ovly_mthd_chan = { 724 .name = "Overlay", 725 .addr = 0x000540, 726 .data = { 727 { "Global", 1, &nv50_disp_ovly_mthd_base }, 728 {} 729 } 730 }; 731 732 int 733 nv50_disp_ovly_ctor(struct nvkm_object *parent, 734 struct nvkm_object *engine, 735 struct nvkm_oclass *oclass, void *data, u32 size, 736 struct nvkm_object **pobject) 737 { 738 union { 739 struct nv50_disp_overlay_channel_dma_v0 v0; 740 } *args = data; 741 struct nv50_disp_priv *priv = (void *)engine; 742 struct nv50_disp_dmac *dmac; 743 int ret; 744 745 nv_ioctl(parent, "create disp overlay channel dma size %d\n", size); 746 if (nvif_unpack(args->v0, 0, 0, false)) { 747 nv_ioctl(parent, "create disp overlay channel dma vers %d " 748 "pushbuf %08x head %d\n", 749 args->v0.version, args->v0.pushbuf, args->v0.head); 750 if (args->v0.head > priv->head.nr) 751 return -EINVAL; 752 } else 753 return ret; 754 755 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf, 756 args->v0.head, sizeof(*dmac), 757 (void **)&dmac); 758 *pobject = nv_object(dmac); 759 if (ret) 760 return ret; 761 762 return 0; 763 } 764 765 struct nv50_disp_chan_impl 766 nv50_disp_ovly_ofuncs = { 767 .base.ctor = nv50_disp_ovly_ctor, 768 .base.dtor = nv50_disp_dmac_dtor, 769 .base.init = nv50_disp_dmac_init, 770 .base.fini = nv50_disp_dmac_fini, 771 .base.ntfy = nv50_disp_chan_ntfy, 772 .base.map = nv50_disp_chan_map, 773 .base.rd32 = nv50_disp_chan_rd32, 774 .base.wr32 = nv50_disp_chan_wr32, 775 .chid = 3, 776 .attach = nv50_disp_dmac_object_attach, 777 .detach = nv50_disp_dmac_object_detach, 778 }; 779 780 /******************************************************************************* 781 * EVO PIO channel base class 782 ******************************************************************************/ 783 784 static int 785 nv50_disp_pioc_create_(struct nvkm_object *parent, 786 struct nvkm_object *engine, 787 struct nvkm_oclass *oclass, int head, 788 int length, void **pobject) 789 { 790 return nv50_disp_chan_create_(parent, engine, oclass, head, 791 length, pobject); 792 } 793 794 void 795 nv50_disp_pioc_dtor(struct nvkm_object *object) 796 { 797 struct nv50_disp_pioc *pioc = (void *)object; 798 nv50_disp_chan_destroy(&pioc->base); 799 } 800 801 static int 802 nv50_disp_pioc_init(struct nvkm_object *object) 803 { 804 struct nv50_disp_priv *priv = (void *)object->engine; 805 struct nv50_disp_pioc *pioc = (void *)object; 806 int chid = pioc->base.chid; 807 int ret; 808 809 ret = nv50_disp_chan_init(&pioc->base); 810 if (ret) 811 return ret; 812 813 nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00002000); 814 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00000000, 0x00000000)) { 815 nv_error(pioc, "timeout0: 0x%08x\n", 816 nv_rd32(priv, 0x610200 + (chid * 0x10))); 817 return -EBUSY; 818 } 819 820 nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00000001); 821 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00010000)) { 822 nv_error(pioc, "timeout1: 0x%08x\n", 823 nv_rd32(priv, 0x610200 + (chid * 0x10))); 824 return -EBUSY; 825 } 826 827 return 0; 828 } 829 830 static int 831 nv50_disp_pioc_fini(struct nvkm_object *object, bool suspend) 832 { 833 struct nv50_disp_priv *priv = (void *)object->engine; 834 struct nv50_disp_pioc *pioc = (void *)object; 835 int chid = pioc->base.chid; 836 837 nv_mask(priv, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000); 838 if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00000000)) { 839 nv_error(pioc, "timeout: 0x%08x\n", 840 nv_rd32(priv, 0x610200 + (chid * 0x10))); 841 if (suspend) 842 return -EBUSY; 843 } 844 845 return nv50_disp_chan_fini(&pioc->base, suspend); 846 } 847 848 /******************************************************************************* 849 * EVO immediate overlay channel objects 850 ******************************************************************************/ 851 852 int 853 nv50_disp_oimm_ctor(struct nvkm_object *parent, 854 struct nvkm_object *engine, 855 struct nvkm_oclass *oclass, void *data, u32 size, 856 struct nvkm_object **pobject) 857 { 858 union { 859 struct nv50_disp_overlay_v0 v0; 860 } *args = data; 861 struct nv50_disp_priv *priv = (void *)engine; 862 struct nv50_disp_pioc *pioc; 863 int ret; 864 865 nv_ioctl(parent, "create disp overlay size %d\n", size); 866 if (nvif_unpack(args->v0, 0, 0, false)) { 867 nv_ioctl(parent, "create disp overlay vers %d head %d\n", 868 args->v0.version, args->v0.head); 869 if (args->v0.head > priv->head.nr) 870 return -EINVAL; 871 } else 872 return ret; 873 874 ret = nv50_disp_pioc_create_(parent, engine, oclass, args->v0.head, 875 sizeof(*pioc), (void **)&pioc); 876 *pobject = nv_object(pioc); 877 if (ret) 878 return ret; 879 880 return 0; 881 } 882 883 struct nv50_disp_chan_impl 884 nv50_disp_oimm_ofuncs = { 885 .base.ctor = nv50_disp_oimm_ctor, 886 .base.dtor = nv50_disp_pioc_dtor, 887 .base.init = nv50_disp_pioc_init, 888 .base.fini = nv50_disp_pioc_fini, 889 .base.ntfy = nv50_disp_chan_ntfy, 890 .base.map = nv50_disp_chan_map, 891 .base.rd32 = nv50_disp_chan_rd32, 892 .base.wr32 = nv50_disp_chan_wr32, 893 .chid = 5, 894 }; 895 896 /******************************************************************************* 897 * EVO cursor channel objects 898 ******************************************************************************/ 899 900 int 901 nv50_disp_curs_ctor(struct nvkm_object *parent, 902 struct nvkm_object *engine, 903 struct nvkm_oclass *oclass, void *data, u32 size, 904 struct nvkm_object **pobject) 905 { 906 union { 907 struct nv50_disp_cursor_v0 v0; 908 } *args = data; 909 struct nv50_disp_priv *priv = (void *)engine; 910 struct nv50_disp_pioc *pioc; 911 int ret; 912 913 nv_ioctl(parent, "create disp cursor size %d\n", size); 914 if (nvif_unpack(args->v0, 0, 0, false)) { 915 nv_ioctl(parent, "create disp cursor vers %d head %d\n", 916 args->v0.version, args->v0.head); 917 if (args->v0.head > priv->head.nr) 918 return -EINVAL; 919 } else 920 return ret; 921 922 ret = nv50_disp_pioc_create_(parent, engine, oclass, args->v0.head, 923 sizeof(*pioc), (void **)&pioc); 924 *pobject = nv_object(pioc); 925 if (ret) 926 return ret; 927 928 return 0; 929 } 930 931 struct nv50_disp_chan_impl 932 nv50_disp_curs_ofuncs = { 933 .base.ctor = nv50_disp_curs_ctor, 934 .base.dtor = nv50_disp_pioc_dtor, 935 .base.init = nv50_disp_pioc_init, 936 .base.fini = nv50_disp_pioc_fini, 937 .base.ntfy = nv50_disp_chan_ntfy, 938 .base.map = nv50_disp_chan_map, 939 .base.rd32 = nv50_disp_chan_rd32, 940 .base.wr32 = nv50_disp_chan_wr32, 941 .chid = 7, 942 }; 943 944 /******************************************************************************* 945 * Base display object 946 ******************************************************************************/ 947 948 int 949 nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0) 950 { 951 const u32 blanke = nv_rd32(priv, 0x610aec + (head * 0x540)); 952 const u32 blanks = nv_rd32(priv, 0x610af4 + (head * 0x540)); 953 const u32 total = nv_rd32(priv, 0x610afc + (head * 0x540)); 954 union { 955 struct nv04_disp_scanoutpos_v0 v0; 956 } *args = data; 957 int ret; 958 959 nv_ioctl(object, "disp scanoutpos size %d\n", size); 960 if (nvif_unpack(args->v0, 0, 0, false)) { 961 nv_ioctl(object, "disp scanoutpos vers %d\n", args->v0.version); 962 args->v0.vblanke = (blanke & 0xffff0000) >> 16; 963 args->v0.hblanke = (blanke & 0x0000ffff); 964 args->v0.vblanks = (blanks & 0xffff0000) >> 16; 965 args->v0.hblanks = (blanks & 0x0000ffff); 966 args->v0.vtotal = ( total & 0xffff0000) >> 16; 967 args->v0.htotal = ( total & 0x0000ffff); 968 args->v0.time[0] = ktime_to_ns(ktime_get()); 969 args->v0.vline = /* vline read locks hline */ 970 nv_rd32(priv, 0x616340 + (head * 0x800)) & 0xffff; 971 args->v0.time[1] = ktime_to_ns(ktime_get()); 972 args->v0.hline = 973 nv_rd32(priv, 0x616344 + (head * 0x800)) & 0xffff; 974 } else 975 return ret; 976 977 return 0; 978 } 979 980 int 981 nv50_disp_main_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) 982 { 983 const struct nv50_disp_impl *impl = (void *)nv_oclass(object->engine); 984 union { 985 struct nv50_disp_mthd_v0 v0; 986 struct nv50_disp_mthd_v1 v1; 987 } *args = data; 988 struct nv50_disp_priv *priv = (void *)object->engine; 989 struct nvkm_output *outp = NULL; 990 struct nvkm_output *temp; 991 u16 type, mask = 0; 992 int head, ret; 993 994 if (mthd != NV50_DISP_MTHD) 995 return -EINVAL; 996 997 nv_ioctl(object, "disp mthd size %d\n", size); 998 if (nvif_unpack(args->v0, 0, 0, true)) { 999 nv_ioctl(object, "disp mthd vers %d mthd %02x head %d\n", 1000 args->v0.version, args->v0.method, args->v0.head); 1001 mthd = args->v0.method; 1002 head = args->v0.head; 1003 } else 1004 if (nvif_unpack(args->v1, 1, 1, true)) { 1005 nv_ioctl(object, "disp mthd vers %d mthd %02x " 1006 "type %04x mask %04x\n", 1007 args->v1.version, args->v1.method, 1008 args->v1.hasht, args->v1.hashm); 1009 mthd = args->v1.method; 1010 type = args->v1.hasht; 1011 mask = args->v1.hashm; 1012 head = ffs((mask >> 8) & 0x0f) - 1; 1013 } else 1014 return ret; 1015 1016 if (head < 0 || head >= priv->head.nr) 1017 return -ENXIO; 1018 1019 if (mask) { 1020 list_for_each_entry(temp, &priv->base.outp, head) { 1021 if ((temp->info.hasht == type) && 1022 (temp->info.hashm & mask) == mask) { 1023 outp = temp; 1024 break; 1025 } 1026 } 1027 if (outp == NULL) 1028 return -ENXIO; 1029 } 1030 1031 switch (mthd) { 1032 case NV50_DISP_SCANOUTPOS: 1033 return impl->head.scanoutpos(object, priv, data, size, head); 1034 default: 1035 break; 1036 } 1037 1038 switch (mthd * !!outp) { 1039 case NV50_DISP_MTHD_V1_DAC_PWR: 1040 return priv->dac.power(object, priv, data, size, head, outp); 1041 case NV50_DISP_MTHD_V1_DAC_LOAD: 1042 return priv->dac.sense(object, priv, data, size, head, outp); 1043 case NV50_DISP_MTHD_V1_SOR_PWR: 1044 return priv->sor.power(object, priv, data, size, head, outp); 1045 case NV50_DISP_MTHD_V1_SOR_HDA_ELD: 1046 if (!priv->sor.hda_eld) 1047 return -ENODEV; 1048 return priv->sor.hda_eld(object, priv, data, size, head, outp); 1049 case NV50_DISP_MTHD_V1_SOR_HDMI_PWR: 1050 if (!priv->sor.hdmi) 1051 return -ENODEV; 1052 return priv->sor.hdmi(object, priv, data, size, head, outp); 1053 case NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT: { 1054 union { 1055 struct nv50_disp_sor_lvds_script_v0 v0; 1056 } *args = data; 1057 nv_ioctl(object, "disp sor lvds script size %d\n", size); 1058 if (nvif_unpack(args->v0, 0, 0, false)) { 1059 nv_ioctl(object, "disp sor lvds script " 1060 "vers %d name %04x\n", 1061 args->v0.version, args->v0.script); 1062 priv->sor.lvdsconf = args->v0.script; 1063 return 0; 1064 } else 1065 return ret; 1066 } 1067 break; 1068 case NV50_DISP_MTHD_V1_SOR_DP_PWR: { 1069 struct nvkm_output_dp *outpdp = (void *)outp; 1070 union { 1071 struct nv50_disp_sor_dp_pwr_v0 v0; 1072 } *args = data; 1073 nv_ioctl(object, "disp sor dp pwr size %d\n", size); 1074 if (nvif_unpack(args->v0, 0, 0, false)) { 1075 nv_ioctl(object, "disp sor dp pwr vers %d state %d\n", 1076 args->v0.version, args->v0.state); 1077 if (args->v0.state == 0) { 1078 nvkm_notify_put(&outpdp->irq); 1079 ((struct nvkm_output_dp_impl *)nv_oclass(outp)) 1080 ->lnk_pwr(outpdp, 0); 1081 atomic_set(&outpdp->lt.done, 0); 1082 return 0; 1083 } else 1084 if (args->v0.state != 0) { 1085 nvkm_output_dp_train(&outpdp->base, 0, true); 1086 return 0; 1087 } 1088 } else 1089 return ret; 1090 } 1091 break; 1092 case NV50_DISP_MTHD_V1_PIOR_PWR: 1093 if (!priv->pior.power) 1094 return -ENODEV; 1095 return priv->pior.power(object, priv, data, size, head, outp); 1096 default: 1097 break; 1098 } 1099 1100 return -EINVAL; 1101 } 1102 1103 int 1104 nv50_disp_main_ctor(struct nvkm_object *parent, 1105 struct nvkm_object *engine, 1106 struct nvkm_oclass *oclass, void *data, u32 size, 1107 struct nvkm_object **pobject) 1108 { 1109 struct nv50_disp_priv *priv = (void *)engine; 1110 struct nv50_disp_base *base; 1111 int ret; 1112 1113 ret = nvkm_parent_create(parent, engine, oclass, 0, 1114 priv->sclass, 0, &base); 1115 *pobject = nv_object(base); 1116 if (ret) 1117 return ret; 1118 1119 return nvkm_ramht_new(nv_object(base), nv_object(base), 0x1000, 0, 1120 &base->ramht); 1121 } 1122 1123 void 1124 nv50_disp_main_dtor(struct nvkm_object *object) 1125 { 1126 struct nv50_disp_base *base = (void *)object; 1127 nvkm_ramht_ref(NULL, &base->ramht); 1128 nvkm_parent_destroy(&base->base); 1129 } 1130 1131 static int 1132 nv50_disp_main_init(struct nvkm_object *object) 1133 { 1134 struct nv50_disp_priv *priv = (void *)object->engine; 1135 struct nv50_disp_base *base = (void *)object; 1136 int ret, i; 1137 u32 tmp; 1138 1139 ret = nvkm_parent_init(&base->base); 1140 if (ret) 1141 return ret; 1142 1143 /* The below segments of code copying values from one register to 1144 * another appear to inform EVO of the display capabilities or 1145 * something similar. NFI what the 0x614004 caps are for.. 1146 */ 1147 tmp = nv_rd32(priv, 0x614004); 1148 nv_wr32(priv, 0x610184, tmp); 1149 1150 /* ... CRTC caps */ 1151 for (i = 0; i < priv->head.nr; i++) { 1152 tmp = nv_rd32(priv, 0x616100 + (i * 0x800)); 1153 nv_wr32(priv, 0x610190 + (i * 0x10), tmp); 1154 tmp = nv_rd32(priv, 0x616104 + (i * 0x800)); 1155 nv_wr32(priv, 0x610194 + (i * 0x10), tmp); 1156 tmp = nv_rd32(priv, 0x616108 + (i * 0x800)); 1157 nv_wr32(priv, 0x610198 + (i * 0x10), tmp); 1158 tmp = nv_rd32(priv, 0x61610c + (i * 0x800)); 1159 nv_wr32(priv, 0x61019c + (i * 0x10), tmp); 1160 } 1161 1162 /* ... DAC caps */ 1163 for (i = 0; i < priv->dac.nr; i++) { 1164 tmp = nv_rd32(priv, 0x61a000 + (i * 0x800)); 1165 nv_wr32(priv, 0x6101d0 + (i * 0x04), tmp); 1166 } 1167 1168 /* ... SOR caps */ 1169 for (i = 0; i < priv->sor.nr; i++) { 1170 tmp = nv_rd32(priv, 0x61c000 + (i * 0x800)); 1171 nv_wr32(priv, 0x6101e0 + (i * 0x04), tmp); 1172 } 1173 1174 /* ... PIOR caps */ 1175 for (i = 0; i < priv->pior.nr; i++) { 1176 tmp = nv_rd32(priv, 0x61e000 + (i * 0x800)); 1177 nv_wr32(priv, 0x6101f0 + (i * 0x04), tmp); 1178 } 1179 1180 /* steal display away from vbios, or something like that */ 1181 if (nv_rd32(priv, 0x610024) & 0x00000100) { 1182 nv_wr32(priv, 0x610024, 0x00000100); 1183 nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000); 1184 if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) { 1185 nv_error(priv, "timeout acquiring display\n"); 1186 return -EBUSY; 1187 } 1188 } 1189 1190 /* point at display engine memory area (hash table, objects) */ 1191 nv_wr32(priv, 0x610010, (nv_gpuobj(base->ramht)->addr >> 8) | 9); 1192 1193 /* enable supervisor interrupts, disable everything else */ 1194 nv_wr32(priv, 0x61002c, 0x00000370); 1195 nv_wr32(priv, 0x610028, 0x00000000); 1196 return 0; 1197 } 1198 1199 static int 1200 nv50_disp_main_fini(struct nvkm_object *object, bool suspend) 1201 { 1202 struct nv50_disp_priv *priv = (void *)object->engine; 1203 struct nv50_disp_base *base = (void *)object; 1204 1205 /* disable all interrupts */ 1206 nv_wr32(priv, 0x610024, 0x00000000); 1207 nv_wr32(priv, 0x610020, 0x00000000); 1208 1209 return nvkm_parent_fini(&base->base, suspend); 1210 } 1211 1212 struct nvkm_ofuncs 1213 nv50_disp_main_ofuncs = { 1214 .ctor = nv50_disp_main_ctor, 1215 .dtor = nv50_disp_main_dtor, 1216 .init = nv50_disp_main_init, 1217 .fini = nv50_disp_main_fini, 1218 .mthd = nv50_disp_main_mthd, 1219 .ntfy = nvkm_disp_ntfy, 1220 }; 1221 1222 static struct nvkm_oclass 1223 nv50_disp_main_oclass[] = { 1224 { NV50_DISP, &nv50_disp_main_ofuncs }, 1225 {} 1226 }; 1227 1228 static struct nvkm_oclass 1229 nv50_disp_sclass[] = { 1230 { NV50_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base }, 1231 { NV50_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base }, 1232 { NV50_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, 1233 { NV50_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base }, 1234 { NV50_DISP_CURSOR, &nv50_disp_curs_ofuncs.base }, 1235 {} 1236 }; 1237 1238 /******************************************************************************* 1239 * Display context, tracks instmem allocation and prevents more than one 1240 * client using the display hardware at any time. 1241 ******************************************************************************/ 1242 1243 static int 1244 nv50_disp_data_ctor(struct nvkm_object *parent, 1245 struct nvkm_object *engine, 1246 struct nvkm_oclass *oclass, void *data, u32 size, 1247 struct nvkm_object **pobject) 1248 { 1249 struct nv50_disp_priv *priv = (void *)engine; 1250 struct nvkm_engctx *ectx; 1251 int ret = -EBUSY; 1252 1253 /* no context needed for channel objects... */ 1254 if (nv_mclass(parent) != NV_DEVICE) { 1255 atomic_inc(&parent->refcount); 1256 *pobject = parent; 1257 return 1; 1258 } 1259 1260 /* allocate display hardware to client */ 1261 mutex_lock(&nv_subdev(priv)->mutex); 1262 if (list_empty(&nv_engine(priv)->contexts)) { 1263 ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0x10000, 1264 0x10000, NVOBJ_FLAG_HEAP, &ectx); 1265 *pobject = nv_object(ectx); 1266 } 1267 mutex_unlock(&nv_subdev(priv)->mutex); 1268 return ret; 1269 } 1270 1271 struct nvkm_oclass 1272 nv50_disp_cclass = { 1273 .handle = NV_ENGCTX(DISP, 0x50), 1274 .ofuncs = &(struct nvkm_ofuncs) { 1275 .ctor = nv50_disp_data_ctor, 1276 .dtor = _nvkm_engctx_dtor, 1277 .init = _nvkm_engctx_init, 1278 .fini = _nvkm_engctx_fini, 1279 .rd32 = _nvkm_engctx_rd32, 1280 .wr32 = _nvkm_engctx_wr32, 1281 }, 1282 }; 1283 1284 /******************************************************************************* 1285 * Display engine implementation 1286 ******************************************************************************/ 1287 1288 static void 1289 nv50_disp_vblank_fini(struct nvkm_event *event, int type, int head) 1290 { 1291 struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); 1292 nv_mask(disp, 0x61002c, (4 << head), 0); 1293 } 1294 1295 static void 1296 nv50_disp_vblank_init(struct nvkm_event *event, int type, int head) 1297 { 1298 struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); 1299 nv_mask(disp, 0x61002c, (4 << head), (4 << head)); 1300 } 1301 1302 const struct nvkm_event_func 1303 nv50_disp_vblank_func = { 1304 .ctor = nvkm_disp_vblank_ctor, 1305 .init = nv50_disp_vblank_init, 1306 .fini = nv50_disp_vblank_fini, 1307 }; 1308 1309 static const struct nvkm_enum 1310 nv50_disp_intr_error_type[] = { 1311 { 3, "ILLEGAL_MTHD" }, 1312 { 4, "INVALID_VALUE" }, 1313 { 5, "INVALID_STATE" }, 1314 { 7, "INVALID_HANDLE" }, 1315 {} 1316 }; 1317 1318 static const struct nvkm_enum 1319 nv50_disp_intr_error_code[] = { 1320 { 0x00, "" }, 1321 {} 1322 }; 1323 1324 static void 1325 nv50_disp_intr_error(struct nv50_disp_priv *priv, int chid) 1326 { 1327 struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; 1328 u32 data = nv_rd32(priv, 0x610084 + (chid * 0x08)); 1329 u32 addr = nv_rd32(priv, 0x610080 + (chid * 0x08)); 1330 u32 code = (addr & 0x00ff0000) >> 16; 1331 u32 type = (addr & 0x00007000) >> 12; 1332 u32 mthd = (addr & 0x00000ffc); 1333 const struct nvkm_enum *ec, *et; 1334 char ecunk[6], etunk[6]; 1335 1336 et = nvkm_enum_find(nv50_disp_intr_error_type, type); 1337 if (!et) 1338 snprintf(etunk, sizeof(etunk), "UNK%02X", type); 1339 1340 ec = nvkm_enum_find(nv50_disp_intr_error_code, code); 1341 if (!ec) 1342 snprintf(ecunk, sizeof(ecunk), "UNK%02X", code); 1343 1344 nv_error(priv, "%s [%s] chid %d mthd 0x%04x data 0x%08x\n", 1345 et ? et->name : etunk, ec ? ec->name : ecunk, 1346 chid, mthd, data); 1347 1348 if (chid == 0) { 1349 switch (mthd) { 1350 case 0x0080: 1351 nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 0, 1352 impl->mthd.core); 1353 break; 1354 default: 1355 break; 1356 } 1357 } else 1358 if (chid <= 2) { 1359 switch (mthd) { 1360 case 0x0080: 1361 nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 1, 1362 impl->mthd.base); 1363 break; 1364 default: 1365 break; 1366 } 1367 } else 1368 if (chid <= 4) { 1369 switch (mthd) { 1370 case 0x0080: 1371 nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 3, 1372 impl->mthd.ovly); 1373 break; 1374 default: 1375 break; 1376 } 1377 } 1378 1379 nv_wr32(priv, 0x610020, 0x00010000 << chid); 1380 nv_wr32(priv, 0x610080 + (chid * 0x08), 0x90000000); 1381 } 1382 1383 static struct nvkm_output * 1384 exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, 1385 u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, 1386 struct nvbios_outp *info) 1387 { 1388 struct nvkm_bios *bios = nvkm_bios(priv); 1389 struct nvkm_output *outp; 1390 u16 mask, type; 1391 1392 if (or < 4) { 1393 type = DCB_OUTPUT_ANALOG; 1394 mask = 0; 1395 } else 1396 if (or < 8) { 1397 switch (ctrl & 0x00000f00) { 1398 case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break; 1399 case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break; 1400 case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break; 1401 case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break; 1402 case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break; 1403 case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break; 1404 default: 1405 nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl); 1406 return NULL; 1407 } 1408 or -= 4; 1409 } else { 1410 or = or - 8; 1411 type = 0x0010; 1412 mask = 0; 1413 switch (ctrl & 0x00000f00) { 1414 case 0x00000000: type |= priv->pior.type[or]; break; 1415 default: 1416 nv_error(priv, "unknown PIOR mc 0x%08x\n", ctrl); 1417 return NULL; 1418 } 1419 } 1420 1421 mask = 0x00c0 & (mask << 6); 1422 mask |= 0x0001 << or; 1423 mask |= 0x0100 << head; 1424 1425 list_for_each_entry(outp, &priv->base.outp, head) { 1426 if ((outp->info.hasht & 0xff) == type && 1427 (outp->info.hashm & mask) == mask) { 1428 *data = nvbios_outp_match(bios, outp->info.hasht, 1429 outp->info.hashm, 1430 ver, hdr, cnt, len, info); 1431 if (!*data) 1432 return NULL; 1433 return outp; 1434 } 1435 } 1436 1437 return NULL; 1438 } 1439 1440 static struct nvkm_output * 1441 exec_script(struct nv50_disp_priv *priv, int head, int id) 1442 { 1443 struct nvkm_bios *bios = nvkm_bios(priv); 1444 struct nvkm_output *outp; 1445 struct nvbios_outp info; 1446 u8 ver, hdr, cnt, len; 1447 u32 data, ctrl = 0; 1448 u32 reg; 1449 int i; 1450 1451 /* DAC */ 1452 for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++) 1453 ctrl = nv_rd32(priv, 0x610b5c + (i * 8)); 1454 1455 /* SOR */ 1456 if (!(ctrl & (1 << head))) { 1457 if (nv_device(priv)->chipset < 0x90 || 1458 nv_device(priv)->chipset == 0x92 || 1459 nv_device(priv)->chipset == 0xa0) { 1460 reg = 0x610b74; 1461 } else { 1462 reg = 0x610798; 1463 } 1464 for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++) 1465 ctrl = nv_rd32(priv, reg + (i * 8)); 1466 i += 4; 1467 } 1468 1469 /* PIOR */ 1470 if (!(ctrl & (1 << head))) { 1471 for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++) 1472 ctrl = nv_rd32(priv, 0x610b84 + (i * 8)); 1473 i += 8; 1474 } 1475 1476 if (!(ctrl & (1 << head))) 1477 return NULL; 1478 i--; 1479 1480 outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info); 1481 if (outp) { 1482 struct nvbios_init init = { 1483 .subdev = nv_subdev(priv), 1484 .bios = bios, 1485 .offset = info.script[id], 1486 .outp = &outp->info, 1487 .crtc = head, 1488 .execute = 1, 1489 }; 1490 1491 nvbios_exec(&init); 1492 } 1493 1494 return outp; 1495 } 1496 1497 static struct nvkm_output * 1498 exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) 1499 { 1500 struct nvkm_bios *bios = nvkm_bios(priv); 1501 struct nvkm_output *outp; 1502 struct nvbios_outp info1; 1503 struct nvbios_ocfg info2; 1504 u8 ver, hdr, cnt, len; 1505 u32 data, ctrl = 0; 1506 u32 reg; 1507 int i; 1508 1509 /* DAC */ 1510 for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++) 1511 ctrl = nv_rd32(priv, 0x610b58 + (i * 8)); 1512 1513 /* SOR */ 1514 if (!(ctrl & (1 << head))) { 1515 if (nv_device(priv)->chipset < 0x90 || 1516 nv_device(priv)->chipset == 0x92 || 1517 nv_device(priv)->chipset == 0xa0) { 1518 reg = 0x610b70; 1519 } else { 1520 reg = 0x610794; 1521 } 1522 for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++) 1523 ctrl = nv_rd32(priv, reg + (i * 8)); 1524 i += 4; 1525 } 1526 1527 /* PIOR */ 1528 if (!(ctrl & (1 << head))) { 1529 for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++) 1530 ctrl = nv_rd32(priv, 0x610b80 + (i * 8)); 1531 i += 8; 1532 } 1533 1534 if (!(ctrl & (1 << head))) 1535 return NULL; 1536 i--; 1537 1538 outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1); 1539 if (!outp) 1540 return NULL; 1541 1542 if (outp->info.location == 0) { 1543 switch (outp->info.type) { 1544 case DCB_OUTPUT_TMDS: 1545 *conf = (ctrl & 0x00000f00) >> 8; 1546 if (pclk >= 165000) 1547 *conf |= 0x0100; 1548 break; 1549 case DCB_OUTPUT_LVDS: 1550 *conf = priv->sor.lvdsconf; 1551 break; 1552 case DCB_OUTPUT_DP: 1553 *conf = (ctrl & 0x00000f00) >> 8; 1554 break; 1555 case DCB_OUTPUT_ANALOG: 1556 default: 1557 *conf = 0x00ff; 1558 break; 1559 } 1560 } else { 1561 *conf = (ctrl & 0x00000f00) >> 8; 1562 pclk = pclk / 2; 1563 } 1564 1565 data = nvbios_ocfg_match(bios, data, *conf, &ver, &hdr, &cnt, &len, &info2); 1566 if (data && id < 0xff) { 1567 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk); 1568 if (data) { 1569 struct nvbios_init init = { 1570 .subdev = nv_subdev(priv), 1571 .bios = bios, 1572 .offset = data, 1573 .outp = &outp->info, 1574 .crtc = head, 1575 .execute = 1, 1576 }; 1577 1578 nvbios_exec(&init); 1579 } 1580 } 1581 1582 return outp; 1583 } 1584 1585 static void 1586 nv50_disp_intr_unk10_0(struct nv50_disp_priv *priv, int head) 1587 { 1588 exec_script(priv, head, 1); 1589 } 1590 1591 static void 1592 nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head) 1593 { 1594 struct nvkm_output *outp = exec_script(priv, head, 2); 1595 1596 /* the binary driver does this outside of the supervisor handling 1597 * (after the third supervisor from a detach). we (currently?) 1598 * allow both detach/attach to happen in the same set of 1599 * supervisor interrupts, so it would make sense to execute this 1600 * (full power down?) script after all the detach phases of the 1601 * supervisor handling. like with training if needed from the 1602 * second supervisor, nvidia doesn't do this, so who knows if it's 1603 * entirely safe, but it does appear to work.. 1604 * 1605 * without this script being run, on some configurations i've 1606 * seen, switching from DP to TMDS on a DP connector may result 1607 * in a blank screen (SOR_PWR off/on can restore it) 1608 */ 1609 if (outp && outp->info.type == DCB_OUTPUT_DP) { 1610 struct nvkm_output_dp *outpdp = (void *)outp; 1611 struct nvbios_init init = { 1612 .subdev = nv_subdev(priv), 1613 .bios = nvkm_bios(priv), 1614 .outp = &outp->info, 1615 .crtc = head, 1616 .offset = outpdp->info.script[4], 1617 .execute = 1, 1618 }; 1619 1620 nvbios_exec(&init); 1621 atomic_set(&outpdp->lt.done, 0); 1622 } 1623 } 1624 1625 static void 1626 nv50_disp_intr_unk20_1(struct nv50_disp_priv *priv, int head) 1627 { 1628 struct nvkm_devinit *devinit = nvkm_devinit(priv); 1629 u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; 1630 if (pclk) 1631 devinit->pll_set(devinit, PLL_VPLL0 + head, pclk); 1632 } 1633 1634 static void 1635 nv50_disp_intr_unk20_2_dp(struct nv50_disp_priv *priv, int head, 1636 struct dcb_output *outp, u32 pclk) 1637 { 1638 const int link = !(outp->sorconf.link & 1); 1639 const int or = ffs(outp->or) - 1; 1640 const u32 soff = ( or * 0x800); 1641 const u32 loff = (link * 0x080) + soff; 1642 const u32 ctrl = nv_rd32(priv, 0x610794 + (or * 8)); 1643 const u32 symbol = 100000; 1644 const s32 vactive = nv_rd32(priv, 0x610af8 + (head * 0x540)) & 0xffff; 1645 const s32 vblanke = nv_rd32(priv, 0x610ae8 + (head * 0x540)) & 0xffff; 1646 const s32 vblanks = nv_rd32(priv, 0x610af0 + (head * 0x540)) & 0xffff; 1647 u32 dpctrl = nv_rd32(priv, 0x61c10c + loff); 1648 u32 clksor = nv_rd32(priv, 0x614300 + soff); 1649 int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0; 1650 int TU, VTUi, VTUf, VTUa; 1651 u64 link_data_rate, link_ratio, unk; 1652 u32 best_diff = 64 * symbol; 1653 u32 link_nr, link_bw, bits; 1654 u64 value; 1655 1656 link_bw = (clksor & 0x000c0000) ? 270000 : 162000; 1657 link_nr = hweight32(dpctrl & 0x000f0000); 1658 1659 /* symbols/hblank - algorithm taken from comments in tegra driver */ 1660 value = vblanke + vactive - vblanks - 7; 1661 value = value * link_bw; 1662 do_div(value, pclk); 1663 value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr); 1664 nv_mask(priv, 0x61c1e8 + soff, 0x0000ffff, value); 1665 1666 /* symbols/vblank - algorithm taken from comments in tegra driver */ 1667 value = vblanks - vblanke - 25; 1668 value = value * link_bw; 1669 do_div(value, pclk); 1670 value = value - ((36 / link_nr) + 3) - 1; 1671 nv_mask(priv, 0x61c1ec + soff, 0x00ffffff, value); 1672 1673 /* watermark / activesym */ 1674 if ((ctrl & 0xf0000) == 0x60000) bits = 30; 1675 else if ((ctrl & 0xf0000) == 0x50000) bits = 24; 1676 else bits = 18; 1677 1678 link_data_rate = (pclk * bits / 8) / link_nr; 1679 1680 /* calculate ratio of packed data rate to link symbol rate */ 1681 link_ratio = link_data_rate * symbol; 1682 do_div(link_ratio, link_bw); 1683 1684 for (TU = 64; TU >= 32; TU--) { 1685 /* calculate average number of valid symbols in each TU */ 1686 u32 tu_valid = link_ratio * TU; 1687 u32 calc, diff; 1688 1689 /* find a hw representation for the fraction.. */ 1690 VTUi = tu_valid / symbol; 1691 calc = VTUi * symbol; 1692 diff = tu_valid - calc; 1693 if (diff) { 1694 if (diff >= (symbol / 2)) { 1695 VTUf = symbol / (symbol - diff); 1696 if (symbol - (VTUf * diff)) 1697 VTUf++; 1698 1699 if (VTUf <= 15) { 1700 VTUa = 1; 1701 calc += symbol - (symbol / VTUf); 1702 } else { 1703 VTUa = 0; 1704 VTUf = 1; 1705 calc += symbol; 1706 } 1707 } else { 1708 VTUa = 0; 1709 VTUf = min((int)(symbol / diff), 15); 1710 calc += symbol / VTUf; 1711 } 1712 1713 diff = calc - tu_valid; 1714 } else { 1715 /* no remainder, but the hw doesn't like the fractional 1716 * part to be zero. decrement the integer part and 1717 * have the fraction add a whole symbol back 1718 */ 1719 VTUa = 0; 1720 VTUf = 1; 1721 VTUi--; 1722 } 1723 1724 if (diff < best_diff) { 1725 best_diff = diff; 1726 bestTU = TU; 1727 bestVTUa = VTUa; 1728 bestVTUf = VTUf; 1729 bestVTUi = VTUi; 1730 if (diff == 0) 1731 break; 1732 } 1733 } 1734 1735 if (!bestTU) { 1736 nv_error(priv, "unable to find suitable dp config\n"); 1737 return; 1738 } 1739 1740 /* XXX close to vbios numbers, but not right */ 1741 unk = (symbol - link_ratio) * bestTU; 1742 unk *= link_ratio; 1743 do_div(unk, symbol); 1744 do_div(unk, symbol); 1745 unk += 6; 1746 1747 nv_mask(priv, 0x61c10c + loff, 0x000001fc, bestTU << 2); 1748 nv_mask(priv, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 | 1749 bestVTUf << 16 | 1750 bestVTUi << 8 | unk); 1751 } 1752 1753 static void 1754 nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) 1755 { 1756 struct nvkm_output *outp; 1757 u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; 1758 u32 hval, hreg = 0x614200 + (head * 0x800); 1759 u32 oval, oreg; 1760 u32 mask, conf; 1761 1762 outp = exec_clkcmp(priv, head, 0xff, pclk, &conf); 1763 if (!outp) 1764 return; 1765 1766 /* we allow both encoder attach and detach operations to occur 1767 * within a single supervisor (ie. modeset) sequence. the 1768 * encoder detach scripts quite often switch off power to the 1769 * lanes, which requires the link to be re-trained. 1770 * 1771 * this is not generally an issue as the sink "must" (heh) 1772 * signal an irq when it's lost sync so the driver can 1773 * re-train. 1774 * 1775 * however, on some boards, if one does not configure at least 1776 * the gpu side of the link *before* attaching, then various 1777 * things can go horribly wrong (PDISP disappearing from mmio, 1778 * third supervisor never happens, etc). 1779 * 1780 * the solution is simply to retrain here, if necessary. last 1781 * i checked, the binary driver userspace does not appear to 1782 * trigger this situation (it forces an UPDATE between steps). 1783 */ 1784 if (outp->info.type == DCB_OUTPUT_DP) { 1785 u32 soff = (ffs(outp->info.or) - 1) * 0x08; 1786 u32 ctrl, datarate; 1787 1788 if (outp->info.location == 0) { 1789 ctrl = nv_rd32(priv, 0x610794 + soff); 1790 soff = 1; 1791 } else { 1792 ctrl = nv_rd32(priv, 0x610b80 + soff); 1793 soff = 2; 1794 } 1795 1796 switch ((ctrl & 0x000f0000) >> 16) { 1797 case 6: datarate = pclk * 30; break; 1798 case 5: datarate = pclk * 24; break; 1799 case 2: 1800 default: 1801 datarate = pclk * 18; 1802 break; 1803 } 1804 1805 if (nvkm_output_dp_train(outp, datarate / soff, true)) 1806 ERR("link not trained before attach\n"); 1807 } 1808 1809 exec_clkcmp(priv, head, 0, pclk, &conf); 1810 1811 if (!outp->info.location && outp->info.type == DCB_OUTPUT_ANALOG) { 1812 oreg = 0x614280 + (ffs(outp->info.or) - 1) * 0x800; 1813 oval = 0x00000000; 1814 hval = 0x00000000; 1815 mask = 0xffffffff; 1816 } else 1817 if (!outp->info.location) { 1818 if (outp->info.type == DCB_OUTPUT_DP) 1819 nv50_disp_intr_unk20_2_dp(priv, head, &outp->info, pclk); 1820 oreg = 0x614300 + (ffs(outp->info.or) - 1) * 0x800; 1821 oval = (conf & 0x0100) ? 0x00000101 : 0x00000000; 1822 hval = 0x00000000; 1823 mask = 0x00000707; 1824 } else { 1825 oreg = 0x614380 + (ffs(outp->info.or) - 1) * 0x800; 1826 oval = 0x00000001; 1827 hval = 0x00000001; 1828 mask = 0x00000707; 1829 } 1830 1831 nv_mask(priv, hreg, 0x0000000f, hval); 1832 nv_mask(priv, oreg, mask, oval); 1833 } 1834 1835 /* If programming a TMDS output on a SOR that can also be configured for 1836 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off. 1837 * 1838 * It looks like the VBIOS TMDS scripts make an attempt at this, however, 1839 * the VBIOS scripts on at least one board I have only switch it off on 1840 * link 0, causing a blank display if the output has previously been 1841 * programmed for DisplayPort. 1842 */ 1843 static void 1844 nv50_disp_intr_unk40_0_tmds(struct nv50_disp_priv *priv, 1845 struct dcb_output *outp) 1846 { 1847 struct nvkm_bios *bios = nvkm_bios(priv); 1848 const int link = !(outp->sorconf.link & 1); 1849 const int or = ffs(outp->or) - 1; 1850 const u32 loff = (or * 0x800) + (link * 0x80); 1851 const u16 mask = (outp->sorconf.link << 6) | outp->or; 1852 struct dcb_output match; 1853 u8 ver, hdr; 1854 1855 if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, &match)) 1856 nv_mask(priv, 0x61c10c + loff, 0x00000001, 0x00000000); 1857 } 1858 1859 static void 1860 nv50_disp_intr_unk40_0(struct nv50_disp_priv *priv, int head) 1861 { 1862 struct nvkm_output *outp; 1863 u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; 1864 u32 conf; 1865 1866 outp = exec_clkcmp(priv, head, 1, pclk, &conf); 1867 if (!outp) 1868 return; 1869 1870 if (outp->info.location == 0 && outp->info.type == DCB_OUTPUT_TMDS) 1871 nv50_disp_intr_unk40_0_tmds(priv, &outp->info); 1872 } 1873 1874 void 1875 nv50_disp_intr_supervisor(struct work_struct *work) 1876 { 1877 struct nv50_disp_priv *priv = 1878 container_of(work, struct nv50_disp_priv, supervisor); 1879 struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; 1880 u32 super = nv_rd32(priv, 0x610030); 1881 int head; 1882 1883 nv_debug(priv, "supervisor 0x%08x 0x%08x\n", priv->super, super); 1884 1885 if (priv->super & 0x00000010) { 1886 nv50_disp_mthd_chan(priv, NV_DBG_DEBUG, 0, impl->mthd.core); 1887 for (head = 0; head < priv->head.nr; head++) { 1888 if (!(super & (0x00000020 << head))) 1889 continue; 1890 if (!(super & (0x00000080 << head))) 1891 continue; 1892 nv50_disp_intr_unk10_0(priv, head); 1893 } 1894 } else 1895 if (priv->super & 0x00000020) { 1896 for (head = 0; head < priv->head.nr; head++) { 1897 if (!(super & (0x00000080 << head))) 1898 continue; 1899 nv50_disp_intr_unk20_0(priv, head); 1900 } 1901 for (head = 0; head < priv->head.nr; head++) { 1902 if (!(super & (0x00000200 << head))) 1903 continue; 1904 nv50_disp_intr_unk20_1(priv, head); 1905 } 1906 for (head = 0; head < priv->head.nr; head++) { 1907 if (!(super & (0x00000080 << head))) 1908 continue; 1909 nv50_disp_intr_unk20_2(priv, head); 1910 } 1911 } else 1912 if (priv->super & 0x00000040) { 1913 for (head = 0; head < priv->head.nr; head++) { 1914 if (!(super & (0x00000080 << head))) 1915 continue; 1916 nv50_disp_intr_unk40_0(priv, head); 1917 } 1918 } 1919 1920 nv_wr32(priv, 0x610030, 0x80000000); 1921 } 1922 1923 void 1924 nv50_disp_intr(struct nvkm_subdev *subdev) 1925 { 1926 struct nv50_disp_priv *priv = (void *)subdev; 1927 u32 intr0 = nv_rd32(priv, 0x610020); 1928 u32 intr1 = nv_rd32(priv, 0x610024); 1929 1930 while (intr0 & 0x001f0000) { 1931 u32 chid = __ffs(intr0 & 0x001f0000) - 16; 1932 nv50_disp_intr_error(priv, chid); 1933 intr0 &= ~(0x00010000 << chid); 1934 } 1935 1936 while (intr0 & 0x0000001f) { 1937 u32 chid = __ffs(intr0 & 0x0000001f); 1938 nv50_disp_chan_uevent_send(priv, chid); 1939 intr0 &= ~(0x00000001 << chid); 1940 } 1941 1942 if (intr1 & 0x00000004) { 1943 nvkm_disp_vblank(&priv->base, 0); 1944 nv_wr32(priv, 0x610024, 0x00000004); 1945 intr1 &= ~0x00000004; 1946 } 1947 1948 if (intr1 & 0x00000008) { 1949 nvkm_disp_vblank(&priv->base, 1); 1950 nv_wr32(priv, 0x610024, 0x00000008); 1951 intr1 &= ~0x00000008; 1952 } 1953 1954 if (intr1 & 0x00000070) { 1955 priv->super = (intr1 & 0x00000070); 1956 schedule_work(&priv->supervisor); 1957 nv_wr32(priv, 0x610024, priv->super); 1958 intr1 &= ~0x00000070; 1959 } 1960 } 1961 1962 static int 1963 nv50_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 1964 struct nvkm_oclass *oclass, void *data, u32 size, 1965 struct nvkm_object **pobject) 1966 { 1967 struct nv50_disp_priv *priv; 1968 int ret; 1969 1970 ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", 1971 "display", &priv); 1972 *pobject = nv_object(priv); 1973 if (ret) 1974 return ret; 1975 1976 ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent); 1977 if (ret) 1978 return ret; 1979 1980 nv_engine(priv)->sclass = nv50_disp_main_oclass; 1981 nv_engine(priv)->cclass = &nv50_disp_cclass; 1982 nv_subdev(priv)->intr = nv50_disp_intr; 1983 INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); 1984 priv->sclass = nv50_disp_sclass; 1985 priv->head.nr = 2; 1986 priv->dac.nr = 3; 1987 priv->sor.nr = 2; 1988 priv->pior.nr = 3; 1989 priv->dac.power = nv50_dac_power; 1990 priv->dac.sense = nv50_dac_sense; 1991 priv->sor.power = nv50_sor_power; 1992 priv->pior.power = nv50_pior_power; 1993 return 0; 1994 } 1995 1996 struct nvkm_oclass * 1997 nv50_disp_outp_sclass[] = { 1998 &nv50_pior_dp_impl.base.base, 1999 NULL 2000 }; 2001 2002 struct nvkm_oclass * 2003 nv50_disp_oclass = &(struct nv50_disp_impl) { 2004 .base.base.handle = NV_ENGINE(DISP, 0x50), 2005 .base.base.ofuncs = &(struct nvkm_ofuncs) { 2006 .ctor = nv50_disp_ctor, 2007 .dtor = _nvkm_disp_dtor, 2008 .init = _nvkm_disp_init, 2009 .fini = _nvkm_disp_fini, 2010 }, 2011 .base.vblank = &nv50_disp_vblank_func, 2012 .base.outp = nv50_disp_outp_sclass, 2013 .mthd.core = &nv50_disp_core_mthd_chan, 2014 .mthd.base = &nv50_disp_base_mthd_chan, 2015 .mthd.ovly = &nv50_disp_ovly_mthd_chan, 2016 .mthd.prev = 0x000004, 2017 .head.scanoutpos = nv50_disp_main_scanoutpos, 2018 }.base.base; 2019