1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "priv.h"
25 
26 #include <core/client.h>
27 #include <core/device.h>
28 
29 #include <nvif/class.h>
30 #include <nvif/unpack.h>
31 
32 struct nv04_disp_priv {
33 	struct nvkm_disp base;
34 };
35 
36 static int
37 nv04_disp_scanoutpos(struct nvkm_object *object, struct nv04_disp_priv *priv,
38 		     void *data, u32 size, int head)
39 {
40 	const u32 hoff = head * 0x2000;
41 	union {
42 		struct nv04_disp_scanoutpos_v0 v0;
43 	} *args = data;
44 	u32 line;
45 	int ret;
46 
47 	nv_ioctl(object, "disp scanoutpos size %d\n", size);
48 	if (nvif_unpack(args->v0, 0, 0, false)) {
49 		nv_ioctl(object, "disp scanoutpos vers %d\n", args->v0.version);
50 		args->v0.vblanks = nv_rd32(priv, 0x680800 + hoff) & 0xffff;
51 		args->v0.vtotal  = nv_rd32(priv, 0x680804 + hoff) & 0xffff;
52 		args->v0.vblanke = args->v0.vtotal - 1;
53 
54 		args->v0.hblanks = nv_rd32(priv, 0x680820 + hoff) & 0xffff;
55 		args->v0.htotal  = nv_rd32(priv, 0x680824 + hoff) & 0xffff;
56 		args->v0.hblanke = args->v0.htotal - 1;
57 
58 		/*
59 		 * If output is vga instead of digital then vtotal/htotal is
60 		 * invalid so we have to give up and trigger the timestamping
61 		 * fallback in the drm core.
62 		 */
63 		if (!args->v0.vtotal || !args->v0.htotal)
64 			return -ENOTSUPP;
65 
66 		args->v0.time[0] = ktime_to_ns(ktime_get());
67 		line = nv_rd32(priv, 0x600868 + hoff);
68 		args->v0.time[1] = ktime_to_ns(ktime_get());
69 		args->v0.hline = (line & 0xffff0000) >> 16;
70 		args->v0.vline = (line & 0x0000ffff);
71 	} else
72 		return ret;
73 
74 	return 0;
75 }
76 
77 static int
78 nv04_disp_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
79 {
80 	union {
81 		struct nv04_disp_mthd_v0 v0;
82 	} *args = data;
83 	struct nv04_disp_priv *priv = (void *)object->engine;
84 	int head, ret;
85 
86 	nv_ioctl(object, "disp mthd size %d\n", size);
87 	if (nvif_unpack(args->v0, 0, 0, true)) {
88 		nv_ioctl(object, "disp mthd vers %d mthd %02x head %d\n",
89 			 args->v0.version, args->v0.method, args->v0.head);
90 		mthd = args->v0.method;
91 		head = args->v0.head;
92 	} else
93 		return ret;
94 
95 	if (head < 0 || head >= 2)
96 		return -ENXIO;
97 
98 	switch (mthd) {
99 	case NV04_DISP_SCANOUTPOS:
100 		return nv04_disp_scanoutpos(object, priv, data, size, head);
101 	default:
102 		break;
103 	}
104 
105 	return -EINVAL;
106 }
107 
108 static struct nvkm_ofuncs
109 nv04_disp_ofuncs = {
110 	.ctor = _nvkm_object_ctor,
111 	.dtor = nvkm_object_destroy,
112 	.init = nvkm_object_init,
113 	.fini = nvkm_object_fini,
114 	.mthd = nv04_disp_mthd,
115 	.ntfy = nvkm_disp_ntfy,
116 };
117 
118 static struct nvkm_oclass
119 nv04_disp_sclass[] = {
120 	{ NV04_DISP, &nv04_disp_ofuncs },
121 	{},
122 };
123 
124 /*******************************************************************************
125  * Display engine implementation
126  ******************************************************************************/
127 
128 static void
129 nv04_disp_vblank_init(struct nvkm_event *event, int type, int head)
130 {
131 	struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
132 	nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000001);
133 }
134 
135 static void
136 nv04_disp_vblank_fini(struct nvkm_event *event, int type, int head)
137 {
138 	struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
139 	nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000000);
140 }
141 
142 static const struct nvkm_event_func
143 nv04_disp_vblank_func = {
144 	.ctor = nvkm_disp_vblank_ctor,
145 	.init = nv04_disp_vblank_init,
146 	.fini = nv04_disp_vblank_fini,
147 };
148 
149 static void
150 nv04_disp_intr(struct nvkm_subdev *subdev)
151 {
152 	struct nv04_disp_priv *priv = (void *)subdev;
153 	u32 crtc0 = nv_rd32(priv, 0x600100);
154 	u32 crtc1 = nv_rd32(priv, 0x602100);
155 	u32 pvideo;
156 
157 	if (crtc0 & 0x00000001) {
158 		nvkm_disp_vblank(&priv->base, 0);
159 		nv_wr32(priv, 0x600100, 0x00000001);
160 	}
161 
162 	if (crtc1 & 0x00000001) {
163 		nvkm_disp_vblank(&priv->base, 1);
164 		nv_wr32(priv, 0x602100, 0x00000001);
165 	}
166 
167 	if (nv_device(priv)->chipset >= 0x10 &&
168 	    nv_device(priv)->chipset <= 0x40) {
169 		pvideo = nv_rd32(priv, 0x8100);
170 		if (pvideo & ~0x11)
171 			nv_info(priv, "PVIDEO intr: %08x\n", pvideo);
172 		nv_wr32(priv, 0x8100, pvideo);
173 	}
174 }
175 
176 static int
177 nv04_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
178 	       struct nvkm_oclass *oclass, void *data, u32 size,
179 	       struct nvkm_object **pobject)
180 {
181 	struct nv04_disp_priv *priv;
182 	int ret;
183 
184 	ret = nvkm_disp_create(parent, engine, oclass, 2, "DISPLAY",
185 			       "display", &priv);
186 	*pobject = nv_object(priv);
187 	if (ret)
188 		return ret;
189 
190 	nv_engine(priv)->sclass = nv04_disp_sclass;
191 	nv_subdev(priv)->intr = nv04_disp_intr;
192 	return 0;
193 }
194 
195 struct nvkm_oclass *
196 nv04_disp_oclass = &(struct nvkm_disp_impl) {
197 	.base.handle = NV_ENGINE(DISP, 0x04),
198 	.base.ofuncs = &(struct nvkm_ofuncs) {
199 		.ctor = nv04_disp_ctor,
200 		.dtor = _nvkm_disp_dtor,
201 		.init = _nvkm_disp_init,
202 		.fini = _nvkm_disp_fini,
203 	},
204 	.vblank = &nv04_disp_vblank_func,
205 }.base;
206