1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "priv.h" 23 #include "chan.h" 24 #include "hdmi.h" 25 #include "head.h" 26 #include "ior.h" 27 #include "outp.h" 28 29 #include <core/client.h> 30 #include <core/gpuobj.h> 31 #include <core/ramht.h> 32 #include <subdev/timer.h> 33 34 #include <nvif/class.h> 35 #include <nvif/unpack.h> 36 37 static void 38 gv100_sor_hda_device_entry(struct nvkm_ior *ior, int head) 39 { 40 struct nvkm_device *device = ior->disp->engine.subdev.device; 41 const u32 hoff = 0x800 * head; 42 43 nvkm_mask(device, 0x616528 + hoff, 0x00000070, head << 4); 44 } 45 46 const struct nvkm_ior_func_hda 47 gv100_sor_hda = { 48 .hpd = gf119_sor_hda_hpd, 49 .eld = gf119_sor_hda_eld, 50 .device_entry = gv100_sor_hda_device_entry, 51 }; 52 53 void 54 gv100_sor_dp_watermark(struct nvkm_ior *sor, int head, u8 watermark) 55 { 56 struct nvkm_device *device = sor->disp->engine.subdev.device; 57 const u32 hoff = head * 0x800; 58 59 nvkm_mask(device, 0x616550 + hoff, 0x0c00003f, 0x08000000 | watermark); 60 } 61 62 void 63 gv100_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v) 64 { 65 struct nvkm_device *device = sor->disp->engine.subdev.device; 66 const u32 hoff = head * 0x800; 67 68 nvkm_mask(device, 0x616568 + hoff, 0x0000ffff, h); 69 nvkm_mask(device, 0x61656c + hoff, 0x00ffffff, v); 70 } 71 72 void 73 gv100_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable) 74 { 75 struct nvkm_device *device = sor->disp->engine.subdev.device; 76 const u32 hoff = 0x800 * head; 77 const u32 data = 0x80000000 | (0x00000001 * enable); 78 const u32 mask = 0x8000000d; 79 80 nvkm_mask(device, 0x616560 + hoff, mask, data); 81 nvkm_msec(device, 2000, 82 if (!(nvkm_rd32(device, 0x616560 + hoff) & 0x80000000)) 83 break; 84 ); 85 } 86 87 static const struct nvkm_ior_func_dp 88 gv100_sor_dp = { 89 .lanes = { 0, 1, 2, 3 }, 90 .links = gf119_sor_dp_links, 91 .power = g94_sor_dp_power, 92 .pattern = gm107_sor_dp_pattern, 93 .drive = gm200_sor_dp_drive, 94 .audio = gv100_sor_dp_audio, 95 .audio_sym = gv100_sor_dp_audio_sym, 96 .watermark = gv100_sor_dp_watermark, 97 }; 98 99 static void 100 gv100_sor_hdmi_infoframe_vsi(struct nvkm_ior *ior, int head, void *data, u32 size) 101 { 102 struct nvkm_device *device = ior->disp->engine.subdev.device; 103 struct packed_hdmi_infoframe vsi; 104 const u32 hoff = head * 0x400; 105 106 pack_hdmi_infoframe(&vsi, data, size); 107 108 nvkm_mask(device, 0x6f0100 + hoff, 0x00010001, 0x00000000); 109 if (!size) 110 return; 111 112 nvkm_wr32(device, 0x6f0108 + hoff, vsi.header); 113 nvkm_wr32(device, 0x6f010c + hoff, vsi.subpack0_low); 114 nvkm_wr32(device, 0x6f0110 + hoff, vsi.subpack0_high); 115 nvkm_wr32(device, 0x6f0114 + hoff, 0x00000000); 116 nvkm_wr32(device, 0x6f0118 + hoff, 0x00000000); 117 nvkm_wr32(device, 0x6f011c + hoff, 0x00000000); 118 nvkm_wr32(device, 0x6f0120 + hoff, 0x00000000); 119 nvkm_wr32(device, 0x6f0124 + hoff, 0x00000000); 120 nvkm_mask(device, 0x6f0100 + hoff, 0x00000001, 0x00000001); 121 } 122 123 static void 124 gv100_sor_hdmi_infoframe_avi(struct nvkm_ior *ior, int head, void *data, u32 size) 125 { 126 struct nvkm_device *device = ior->disp->engine.subdev.device; 127 struct packed_hdmi_infoframe avi; 128 const u32 hoff = head * 0x400; 129 130 pack_hdmi_infoframe(&avi, data, size); 131 132 nvkm_mask(device, 0x6f0000 + hoff, 0x00000001, 0x00000000); 133 if (!size) 134 return; 135 136 nvkm_wr32(device, 0x6f0008 + hoff, avi.header); 137 nvkm_wr32(device, 0x6f000c + hoff, avi.subpack0_low); 138 nvkm_wr32(device, 0x6f0010 + hoff, avi.subpack0_high); 139 nvkm_wr32(device, 0x6f0014 + hoff, avi.subpack1_low); 140 nvkm_wr32(device, 0x6f0018 + hoff, avi.subpack1_high); 141 142 nvkm_mask(device, 0x6f0000 + hoff, 0x00000001, 0x00000001); 143 } 144 145 static void 146 gv100_sor_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet, u8 rekey) 147 { 148 struct nvkm_device *device = ior->disp->engine.subdev.device; 149 const u32 ctrl = 0x40000000 * enable | 150 max_ac_packet << 16 | 151 rekey; 152 const u32 hoff = head * 0x800; 153 const u32 hdmi = head * 0x400; 154 155 if (!(ctrl & 0x40000000)) { 156 nvkm_mask(device, 0x6165c0 + hoff, 0x40000000, 0x00000000); 157 nvkm_mask(device, 0x6f0100 + hdmi, 0x00000001, 0x00000000); 158 nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000000); 159 nvkm_mask(device, 0x6f0000 + hdmi, 0x00000001, 0x00000000); 160 return; 161 } 162 163 /* General Control (GCP). */ 164 nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000000); 165 nvkm_wr32(device, 0x6f00cc + hdmi, 0x00000010); 166 nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000001); 167 168 /* Audio Clock Regeneration (ACR). */ 169 nvkm_wr32(device, 0x6f0080 + hdmi, 0x82000000); 170 171 /* NV_PDISP_SF_HDMI_CTRL. */ 172 nvkm_mask(device, 0x6165c0 + hoff, 0x401f007f, ctrl); 173 } 174 175 const struct nvkm_ior_func_hdmi 176 gv100_sor_hdmi = { 177 .ctrl = gv100_sor_hdmi_ctrl, 178 .scdc = gm200_sor_hdmi_scdc, 179 .infoframe_avi = gv100_sor_hdmi_infoframe_avi, 180 .infoframe_vsi = gv100_sor_hdmi_infoframe_vsi, 181 }; 182 183 void 184 gv100_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state) 185 { 186 struct nvkm_device *device = sor->disp->engine.subdev.device; 187 const u32 coff = (state == &sor->arm) * 0x8000 + sor->id * 0x20; 188 u32 ctrl = nvkm_rd32(device, 0x680300 + coff); 189 190 state->proto_evo = (ctrl & 0x00000f00) >> 8; 191 switch (state->proto_evo) { 192 case 0: state->proto = LVDS; state->link = 1; break; 193 case 1: state->proto = TMDS; state->link = 1; break; 194 case 2: state->proto = TMDS; state->link = 2; break; 195 case 5: state->proto = TMDS; state->link = 3; break; 196 case 8: state->proto = DP; state->link = 1; break; 197 case 9: state->proto = DP; state->link = 2; break; 198 default: 199 state->proto = UNKNOWN; 200 break; 201 } 202 203 state->head = ctrl & 0x000000ff; 204 } 205 206 static const struct nvkm_ior_func 207 gv100_sor = { 208 .route = { 209 .get = gm200_sor_route_get, 210 .set = gm200_sor_route_set, 211 }, 212 .state = gv100_sor_state, 213 .power = nv50_sor_power, 214 .clock = gf119_sor_clock, 215 .hdmi = &gv100_sor_hdmi, 216 .dp = &gv100_sor_dp, 217 .hda = &gv100_sor_hda, 218 }; 219 220 static int 221 gv100_sor_new(struct nvkm_disp *disp, int id) 222 { 223 struct nvkm_device *device = disp->engine.subdev.device; 224 u32 hda; 225 226 if (!((hda = nvkm_rd32(device, 0x08a15c)) & 0x40000000)) 227 hda = nvkm_rd32(device, 0x118fb0) >> 8; 228 229 return nvkm_ior_new_(&gv100_sor, disp, SOR, id, hda & BIT(id)); 230 } 231 232 int 233 gv100_sor_cnt(struct nvkm_disp *disp, unsigned long *pmask) 234 { 235 struct nvkm_device *device = disp->engine.subdev.device; 236 237 *pmask = (nvkm_rd32(device, 0x610060) & 0x0000ff00) >> 8; 238 return (nvkm_rd32(device, 0x610074) & 0x00000f00) >> 8; 239 } 240 241 static void 242 gv100_head_vblank_put(struct nvkm_head *head) 243 { 244 struct nvkm_device *device = head->disp->engine.subdev.device; 245 nvkm_mask(device, 0x611d80 + (head->id * 4), 0x00000004, 0x00000000); 246 } 247 248 static void 249 gv100_head_vblank_get(struct nvkm_head *head) 250 { 251 struct nvkm_device *device = head->disp->engine.subdev.device; 252 nvkm_mask(device, 0x611d80 + (head->id * 4), 0x00000004, 0x00000004); 253 } 254 255 static void 256 gv100_head_rgpos(struct nvkm_head *head, u16 *hline, u16 *vline) 257 { 258 struct nvkm_device *device = head->disp->engine.subdev.device; 259 const u32 hoff = head->id * 0x800; 260 /* vline read locks hline. */ 261 *vline = nvkm_rd32(device, 0x616330 + hoff) & 0x0000ffff; 262 *hline = nvkm_rd32(device, 0x616334 + hoff) & 0x0000ffff; 263 } 264 265 static void 266 gv100_head_state(struct nvkm_head *head, struct nvkm_head_state *state) 267 { 268 struct nvkm_device *device = head->disp->engine.subdev.device; 269 const u32 hoff = (state == &head->arm) * 0x8000 + head->id * 0x400; 270 u32 data; 271 272 data = nvkm_rd32(device, 0x682064 + hoff); 273 state->vtotal = (data & 0xffff0000) >> 16; 274 state->htotal = (data & 0x0000ffff); 275 data = nvkm_rd32(device, 0x682068 + hoff); 276 state->vsynce = (data & 0xffff0000) >> 16; 277 state->hsynce = (data & 0x0000ffff); 278 data = nvkm_rd32(device, 0x68206c + hoff); 279 state->vblanke = (data & 0xffff0000) >> 16; 280 state->hblanke = (data & 0x0000ffff); 281 data = nvkm_rd32(device, 0x682070 + hoff); 282 state->vblanks = (data & 0xffff0000) >> 16; 283 state->hblanks = (data & 0x0000ffff); 284 state->hz = nvkm_rd32(device, 0x68200c + hoff); 285 286 data = nvkm_rd32(device, 0x682004 + hoff); 287 switch ((data & 0x000000f0) >> 4) { 288 case 5: state->or.depth = 30; break; 289 case 4: state->or.depth = 24; break; 290 case 1: state->or.depth = 18; break; 291 default: 292 state->or.depth = 18; 293 WARN_ON(1); 294 break; 295 } 296 } 297 298 static const struct nvkm_head_func 299 gv100_head = { 300 .state = gv100_head_state, 301 .rgpos = gv100_head_rgpos, 302 .rgclk = gf119_head_rgclk, 303 .vblank_get = gv100_head_vblank_get, 304 .vblank_put = gv100_head_vblank_put, 305 }; 306 307 int 308 gv100_head_new(struct nvkm_disp *disp, int id) 309 { 310 struct nvkm_device *device = disp->engine.subdev.device; 311 312 if (!(nvkm_rd32(device, 0x610060) & (0x00000001 << id))) 313 return 0; 314 315 return nvkm_head_new_(&gv100_head, disp, id); 316 } 317 318 int 319 gv100_head_cnt(struct nvkm_disp *disp, unsigned long *pmask) 320 { 321 struct nvkm_device *device = disp->engine.subdev.device; 322 323 *pmask = nvkm_rd32(device, 0x610060) & 0x000000ff; 324 return nvkm_rd32(device, 0x610074) & 0x0000000f; 325 } 326 327 const struct nvkm_event_func 328 gv100_disp_chan_uevent = { 329 }; 330 331 u64 332 gv100_disp_chan_user(struct nvkm_disp_chan *chan, u64 *psize) 333 { 334 *psize = 0x1000; 335 return 0x690000 + ((chan->chid.user - 1) * 0x1000); 336 } 337 338 static int 339 gv100_disp_dmac_idle(struct nvkm_disp_chan *chan) 340 { 341 struct nvkm_device *device = chan->disp->engine.subdev.device; 342 const u32 soff = (chan->chid.ctrl - 1) * 0x04; 343 nvkm_msec(device, 2000, 344 u32 stat = nvkm_rd32(device, 0x610664 + soff); 345 if ((stat & 0x000f0000) == 0x00040000) 346 return 0; 347 ); 348 return -EBUSY; 349 } 350 351 int 352 gv100_disp_dmac_bind(struct nvkm_disp_chan *chan, 353 struct nvkm_object *object, u32 handle) 354 { 355 return nvkm_ramht_insert(chan->disp->ramht, object, chan->chid.user, -9, handle, 356 chan->chid.user << 25 | 0x00000040); 357 } 358 359 void 360 gv100_disp_dmac_fini(struct nvkm_disp_chan *chan) 361 { 362 struct nvkm_device *device = chan->disp->engine.subdev.device; 363 const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; 364 const u32 coff = chan->chid.ctrl * 0x04; 365 nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000000); 366 gv100_disp_dmac_idle(chan); 367 nvkm_mask(device, 0x6104e0 + coff, 0x00000002, 0x00000000); 368 chan->suspend_put = nvkm_rd32(device, 0x690000 + uoff); 369 } 370 371 int 372 gv100_disp_dmac_init(struct nvkm_disp_chan *chan) 373 { 374 struct nvkm_subdev *subdev = &chan->disp->engine.subdev; 375 struct nvkm_device *device = subdev->device; 376 const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; 377 const u32 poff = chan->chid.ctrl * 0x10; 378 const u32 coff = chan->chid.ctrl * 0x04; 379 380 nvkm_wr32(device, 0x610b24 + poff, lower_32_bits(chan->push)); 381 nvkm_wr32(device, 0x610b20 + poff, upper_32_bits(chan->push)); 382 nvkm_wr32(device, 0x610b28 + poff, 0x00000001); 383 nvkm_wr32(device, 0x610b2c + poff, 0x00000040); 384 385 nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000010); 386 nvkm_wr32(device, 0x690000 + uoff, chan->suspend_put); 387 nvkm_wr32(device, 0x6104e0 + coff, 0x00000013); 388 return gv100_disp_dmac_idle(chan); 389 } 390 391 static void 392 gv100_disp_wimm_intr(struct nvkm_disp_chan *chan, bool en) 393 { 394 struct nvkm_device *device = chan->disp->engine.subdev.device; 395 const u32 mask = 0x00000001 << chan->head; 396 const u32 data = en ? mask : 0; 397 nvkm_mask(device, 0x611da8, mask, data); 398 } 399 400 static const struct nvkm_disp_chan_func 401 gv100_disp_wimm_func = { 402 .push = nv50_disp_dmac_push, 403 .init = gv100_disp_dmac_init, 404 .fini = gv100_disp_dmac_fini, 405 .intr = gv100_disp_wimm_intr, 406 .user = gv100_disp_chan_user, 407 }; 408 409 const struct nvkm_disp_chan_user 410 gv100_disp_wimm = { 411 .func = &gv100_disp_wimm_func, 412 .ctrl = 33, 413 .user = 33, 414 }; 415 416 static const struct nvkm_disp_mthd_list 417 gv100_disp_wndw_mthd_base = { 418 .mthd = 0x0000, 419 .addr = 0x000000, 420 .data = { 421 { 0x0200, 0x690200 }, 422 { 0x020c, 0x69020c }, 423 { 0x0210, 0x690210 }, 424 { 0x0214, 0x690214 }, 425 { 0x0218, 0x690218 }, 426 { 0x021c, 0x69021c }, 427 { 0x0220, 0x690220 }, 428 { 0x0224, 0x690224 }, 429 { 0x0228, 0x690228 }, 430 { 0x022c, 0x69022c }, 431 { 0x0230, 0x690230 }, 432 { 0x0234, 0x690234 }, 433 { 0x0238, 0x690238 }, 434 { 0x0240, 0x690240 }, 435 { 0x0244, 0x690244 }, 436 { 0x0248, 0x690248 }, 437 { 0x024c, 0x69024c }, 438 { 0x0250, 0x690250 }, 439 { 0x0254, 0x690254 }, 440 { 0x0260, 0x690260 }, 441 { 0x0264, 0x690264 }, 442 { 0x0268, 0x690268 }, 443 { 0x026c, 0x69026c }, 444 { 0x0270, 0x690270 }, 445 { 0x0274, 0x690274 }, 446 { 0x0280, 0x690280 }, 447 { 0x0284, 0x690284 }, 448 { 0x0288, 0x690288 }, 449 { 0x028c, 0x69028c }, 450 { 0x0290, 0x690290 }, 451 { 0x0298, 0x690298 }, 452 { 0x029c, 0x69029c }, 453 { 0x02a0, 0x6902a0 }, 454 { 0x02a4, 0x6902a4 }, 455 { 0x02a8, 0x6902a8 }, 456 { 0x02ac, 0x6902ac }, 457 { 0x02b0, 0x6902b0 }, 458 { 0x02b4, 0x6902b4 }, 459 { 0x02b8, 0x6902b8 }, 460 { 0x02bc, 0x6902bc }, 461 { 0x02c0, 0x6902c0 }, 462 { 0x02c4, 0x6902c4 }, 463 { 0x02c8, 0x6902c8 }, 464 { 0x02cc, 0x6902cc }, 465 { 0x02d0, 0x6902d0 }, 466 { 0x02d4, 0x6902d4 }, 467 { 0x02d8, 0x6902d8 }, 468 { 0x02dc, 0x6902dc }, 469 { 0x02e0, 0x6902e0 }, 470 { 0x02e4, 0x6902e4 }, 471 { 0x02e8, 0x6902e8 }, 472 { 0x02ec, 0x6902ec }, 473 { 0x02f0, 0x6902f0 }, 474 { 0x02f4, 0x6902f4 }, 475 { 0x02f8, 0x6902f8 }, 476 { 0x02fc, 0x6902fc }, 477 { 0x0300, 0x690300 }, 478 { 0x0304, 0x690304 }, 479 { 0x0308, 0x690308 }, 480 { 0x0310, 0x690310 }, 481 { 0x0314, 0x690314 }, 482 { 0x0318, 0x690318 }, 483 { 0x031c, 0x69031c }, 484 { 0x0320, 0x690320 }, 485 { 0x0324, 0x690324 }, 486 { 0x0328, 0x690328 }, 487 { 0x032c, 0x69032c }, 488 { 0x033c, 0x69033c }, 489 { 0x0340, 0x690340 }, 490 { 0x0344, 0x690344 }, 491 { 0x0348, 0x690348 }, 492 { 0x034c, 0x69034c }, 493 { 0x0350, 0x690350 }, 494 { 0x0354, 0x690354 }, 495 { 0x0358, 0x690358 }, 496 { 0x0364, 0x690364 }, 497 { 0x0368, 0x690368 }, 498 { 0x036c, 0x69036c }, 499 { 0x0370, 0x690370 }, 500 { 0x0374, 0x690374 }, 501 { 0x0380, 0x690380 }, 502 {} 503 } 504 }; 505 506 static const struct nvkm_disp_chan_mthd 507 gv100_disp_wndw_mthd = { 508 .name = "Window", 509 .addr = 0x001000, 510 .prev = 0x000800, 511 .data = { 512 { "Global", 1, &gv100_disp_wndw_mthd_base }, 513 {} 514 } 515 }; 516 517 static void 518 gv100_disp_wndw_intr(struct nvkm_disp_chan *chan, bool en) 519 { 520 struct nvkm_device *device = chan->disp->engine.subdev.device; 521 const u32 mask = 0x00000001 << chan->head; 522 const u32 data = en ? mask : 0; 523 nvkm_mask(device, 0x611da4, mask, data); 524 } 525 526 static const struct nvkm_disp_chan_func 527 gv100_disp_wndw_func = { 528 .push = nv50_disp_dmac_push, 529 .init = gv100_disp_dmac_init, 530 .fini = gv100_disp_dmac_fini, 531 .intr = gv100_disp_wndw_intr, 532 .user = gv100_disp_chan_user, 533 .bind = gv100_disp_dmac_bind, 534 }; 535 536 const struct nvkm_disp_chan_user 537 gv100_disp_wndw = { 538 .func = &gv100_disp_wndw_func, 539 .ctrl = 1, 540 .user = 1, 541 .mthd = &gv100_disp_wndw_mthd, 542 }; 543 544 int 545 gv100_disp_wndw_cnt(struct nvkm_disp *disp, unsigned long *pmask) 546 { 547 struct nvkm_device *device = disp->engine.subdev.device; 548 549 *pmask = nvkm_rd32(device, 0x610064); 550 return (nvkm_rd32(device, 0x610074) & 0x03f00000) >> 20; 551 } 552 553 static int 554 gv100_disp_curs_idle(struct nvkm_disp_chan *chan) 555 { 556 struct nvkm_device *device = chan->disp->engine.subdev.device; 557 const u32 soff = (chan->chid.ctrl - 1) * 0x04; 558 nvkm_msec(device, 2000, 559 u32 stat = nvkm_rd32(device, 0x610664 + soff); 560 if ((stat & 0x00070000) == 0x00040000) 561 return 0; 562 ); 563 return -EBUSY; 564 } 565 566 static void 567 gv100_disp_curs_intr(struct nvkm_disp_chan *chan, bool en) 568 { 569 struct nvkm_device *device = chan->disp->engine.subdev.device; 570 const u32 mask = 0x00010000 << chan->head; 571 const u32 data = en ? mask : 0; 572 nvkm_mask(device, 0x611dac, mask, data); 573 } 574 575 static void 576 gv100_disp_curs_fini(struct nvkm_disp_chan *chan) 577 { 578 struct nvkm_device *device = chan->disp->engine.subdev.device; 579 const u32 hoff = chan->chid.ctrl * 4; 580 nvkm_mask(device, 0x6104e0 + hoff, 0x00000010, 0x00000010); 581 gv100_disp_curs_idle(chan); 582 nvkm_mask(device, 0x6104e0 + hoff, 0x00000001, 0x00000000); 583 } 584 585 static int 586 gv100_disp_curs_init(struct nvkm_disp_chan *chan) 587 { 588 struct nvkm_subdev *subdev = &chan->disp->engine.subdev; 589 struct nvkm_device *device = subdev->device; 590 nvkm_wr32(device, 0x6104e0 + chan->chid.ctrl * 4, 0x00000001); 591 return gv100_disp_curs_idle(chan); 592 } 593 594 static const struct nvkm_disp_chan_func 595 gv100_disp_curs_func = { 596 .init = gv100_disp_curs_init, 597 .fini = gv100_disp_curs_fini, 598 .intr = gv100_disp_curs_intr, 599 .user = gv100_disp_chan_user, 600 }; 601 602 const struct nvkm_disp_chan_user 603 gv100_disp_curs = { 604 .func = &gv100_disp_curs_func, 605 .ctrl = 73, 606 .user = 73, 607 }; 608 609 static const struct nvkm_disp_mthd_list 610 gv100_disp_core_mthd_base = { 611 .mthd = 0x0000, 612 .addr = 0x000000, 613 .data = { 614 { 0x0200, 0x680200 }, 615 { 0x0208, 0x680208 }, 616 { 0x020c, 0x68020c }, 617 { 0x0210, 0x680210 }, 618 { 0x0214, 0x680214 }, 619 { 0x0218, 0x680218 }, 620 { 0x021c, 0x68021c }, 621 {} 622 } 623 }; 624 625 static const struct nvkm_disp_mthd_list 626 gv100_disp_core_mthd_sor = { 627 .mthd = 0x0020, 628 .addr = 0x000020, 629 .data = { 630 { 0x0300, 0x680300 }, 631 { 0x0304, 0x680304 }, 632 { 0x0308, 0x680308 }, 633 { 0x030c, 0x68030c }, 634 {} 635 } 636 }; 637 638 static const struct nvkm_disp_mthd_list 639 gv100_disp_core_mthd_wndw = { 640 .mthd = 0x0080, 641 .addr = 0x000080, 642 .data = { 643 { 0x1000, 0x681000 }, 644 { 0x1004, 0x681004 }, 645 { 0x1008, 0x681008 }, 646 { 0x100c, 0x68100c }, 647 { 0x1010, 0x681010 }, 648 {} 649 } 650 }; 651 652 static const struct nvkm_disp_mthd_list 653 gv100_disp_core_mthd_head = { 654 .mthd = 0x0400, 655 .addr = 0x000400, 656 .data = { 657 { 0x2000, 0x682000 }, 658 { 0x2004, 0x682004 }, 659 { 0x2008, 0x682008 }, 660 { 0x200c, 0x68200c }, 661 { 0x2014, 0x682014 }, 662 { 0x2018, 0x682018 }, 663 { 0x201c, 0x68201c }, 664 { 0x2020, 0x682020 }, 665 { 0x2028, 0x682028 }, 666 { 0x202c, 0x68202c }, 667 { 0x2030, 0x682030 }, 668 { 0x2038, 0x682038 }, 669 { 0x203c, 0x68203c }, 670 { 0x2048, 0x682048 }, 671 { 0x204c, 0x68204c }, 672 { 0x2050, 0x682050 }, 673 { 0x2054, 0x682054 }, 674 { 0x2058, 0x682058 }, 675 { 0x205c, 0x68205c }, 676 { 0x2060, 0x682060 }, 677 { 0x2064, 0x682064 }, 678 { 0x2068, 0x682068 }, 679 { 0x206c, 0x68206c }, 680 { 0x2070, 0x682070 }, 681 { 0x2074, 0x682074 }, 682 { 0x2078, 0x682078 }, 683 { 0x207c, 0x68207c }, 684 { 0x2080, 0x682080 }, 685 { 0x2088, 0x682088 }, 686 { 0x2090, 0x682090 }, 687 { 0x209c, 0x68209c }, 688 { 0x20a0, 0x6820a0 }, 689 { 0x20a4, 0x6820a4 }, 690 { 0x20a8, 0x6820a8 }, 691 { 0x20ac, 0x6820ac }, 692 { 0x2180, 0x682180 }, 693 { 0x2184, 0x682184 }, 694 { 0x218c, 0x68218c }, 695 { 0x2194, 0x682194 }, 696 { 0x2198, 0x682198 }, 697 { 0x219c, 0x68219c }, 698 { 0x21a0, 0x6821a0 }, 699 { 0x21a4, 0x6821a4 }, 700 { 0x2214, 0x682214 }, 701 { 0x2218, 0x682218 }, 702 {} 703 } 704 }; 705 706 static const struct nvkm_disp_chan_mthd 707 gv100_disp_core_mthd = { 708 .name = "Core", 709 .addr = 0x000000, 710 .prev = 0x008000, 711 .data = { 712 { "Global", 1, &gv100_disp_core_mthd_base }, 713 { "SOR", 4, &gv100_disp_core_mthd_sor }, 714 { "WINDOW", 8, &gv100_disp_core_mthd_wndw }, 715 { "HEAD", 4, &gv100_disp_core_mthd_head }, 716 {} 717 } 718 }; 719 720 static int 721 gv100_disp_core_idle(struct nvkm_disp_chan *chan) 722 { 723 struct nvkm_device *device = chan->disp->engine.subdev.device; 724 nvkm_msec(device, 2000, 725 u32 stat = nvkm_rd32(device, 0x610630); 726 if ((stat & 0x001f0000) == 0x000b0000) 727 return 0; 728 ); 729 return -EBUSY; 730 } 731 732 static u64 733 gv100_disp_core_user(struct nvkm_disp_chan *chan, u64 *psize) 734 { 735 *psize = 0x10000; 736 return 0x680000; 737 } 738 739 static void 740 gv100_disp_core_intr(struct nvkm_disp_chan *chan, bool en) 741 { 742 struct nvkm_device *device = chan->disp->engine.subdev.device; 743 const u32 mask = 0x00000001; 744 const u32 data = en ? mask : 0; 745 nvkm_mask(device, 0x611dac, mask, data); 746 } 747 748 static void 749 gv100_disp_core_fini(struct nvkm_disp_chan *chan) 750 { 751 struct nvkm_device *device = chan->disp->engine.subdev.device; 752 nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000000); 753 gv100_disp_core_idle(chan); 754 nvkm_mask(device, 0x6104e0, 0x00000002, 0x00000000); 755 chan->suspend_put = nvkm_rd32(device, 0x680000); 756 } 757 758 static int 759 gv100_disp_core_init(struct nvkm_disp_chan *chan) 760 { 761 struct nvkm_subdev *subdev = &chan->disp->engine.subdev; 762 struct nvkm_device *device = subdev->device; 763 764 nvkm_wr32(device, 0x610b24, lower_32_bits(chan->push)); 765 nvkm_wr32(device, 0x610b20, upper_32_bits(chan->push)); 766 nvkm_wr32(device, 0x610b28, 0x00000001); 767 nvkm_wr32(device, 0x610b2c, 0x00000040); 768 769 nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000010); 770 nvkm_wr32(device, 0x680000, chan->suspend_put); 771 nvkm_wr32(device, 0x6104e0, 0x00000013); 772 return gv100_disp_core_idle(chan); 773 } 774 775 static const struct nvkm_disp_chan_func 776 gv100_disp_core_func = { 777 .push = nv50_disp_dmac_push, 778 .init = gv100_disp_core_init, 779 .fini = gv100_disp_core_fini, 780 .intr = gv100_disp_core_intr, 781 .user = gv100_disp_core_user, 782 .bind = gv100_disp_dmac_bind, 783 }; 784 785 const struct nvkm_disp_chan_user 786 gv100_disp_core = { 787 .func = &gv100_disp_core_func, 788 .ctrl = 0, 789 .user = 0, 790 .mthd = &gv100_disp_core_mthd, 791 }; 792 793 #define gv100_disp_caps(p) container_of((p), struct gv100_disp_caps, object) 794 795 struct gv100_disp_caps { 796 struct nvkm_object object; 797 struct nvkm_disp *disp; 798 }; 799 800 static int 801 gv100_disp_caps_map(struct nvkm_object *object, void *argv, u32 argc, 802 enum nvkm_object_map *type, u64 *addr, u64 *size) 803 { 804 struct gv100_disp_caps *caps = gv100_disp_caps(object); 805 struct nvkm_device *device = caps->disp->engine.subdev.device; 806 *type = NVKM_OBJECT_MAP_IO; 807 *addr = 0x640000 + device->func->resource_addr(device, 0); 808 *size = 0x1000; 809 return 0; 810 } 811 812 static const struct nvkm_object_func 813 gv100_disp_caps = { 814 .map = gv100_disp_caps_map, 815 }; 816 817 int 818 gv100_disp_caps_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, 819 struct nvkm_object **pobject) 820 { 821 struct nvkm_disp *disp = nvkm_udisp(oclass->parent); 822 struct gv100_disp_caps *caps; 823 824 if (!(caps = kzalloc(sizeof(*caps), GFP_KERNEL))) 825 return -ENOMEM; 826 *pobject = &caps->object; 827 828 nvkm_object_ctor(&gv100_disp_caps, oclass, &caps->object); 829 caps->disp = disp; 830 return 0; 831 } 832 833 void 834 gv100_disp_super(struct work_struct *work) 835 { 836 struct nvkm_disp *disp = container_of(work, struct nvkm_disp, super.work); 837 struct nvkm_subdev *subdev = &disp->engine.subdev; 838 struct nvkm_device *device = subdev->device; 839 struct nvkm_head *head; 840 u32 stat, mask[4]; 841 842 mutex_lock(&disp->super.mutex); 843 stat = nvkm_rd32(device, 0x6107a8); 844 845 nvkm_debug(subdev, "supervisor %d: %08x\n", ffs(disp->super.pending), stat); 846 list_for_each_entry(head, &disp->heads, head) { 847 mask[head->id] = nvkm_rd32(device, 0x6107ac + (head->id * 4)); 848 HEAD_DBG(head, "%08x", mask[head->id]); 849 } 850 851 if (disp->super.pending & 0x00000001) { 852 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); 853 nv50_disp_super_1(disp); 854 list_for_each_entry(head, &disp->heads, head) { 855 if (!(mask[head->id] & 0x00001000)) 856 continue; 857 nv50_disp_super_1_0(disp, head); 858 } 859 } else 860 if (disp->super.pending & 0x00000002) { 861 list_for_each_entry(head, &disp->heads, head) { 862 if (!(mask[head->id] & 0x00001000)) 863 continue; 864 nv50_disp_super_2_0(disp, head); 865 } 866 nvkm_outp_route(disp); 867 list_for_each_entry(head, &disp->heads, head) { 868 if (!(mask[head->id] & 0x00010000)) 869 continue; 870 nv50_disp_super_2_1(disp, head); 871 } 872 list_for_each_entry(head, &disp->heads, head) { 873 if (!(mask[head->id] & 0x00001000)) 874 continue; 875 nv50_disp_super_2_2(disp, head); 876 } 877 } else 878 if (disp->super.pending & 0x00000004) { 879 list_for_each_entry(head, &disp->heads, head) { 880 if (!(mask[head->id] & 0x00001000)) 881 continue; 882 nv50_disp_super_3_0(disp, head); 883 } 884 } 885 886 list_for_each_entry(head, &disp->heads, head) 887 nvkm_wr32(device, 0x6107ac + (head->id * 4), 0x00000000); 888 889 nvkm_wr32(device, 0x6107a8, 0x80000000); 890 mutex_unlock(&disp->super.mutex); 891 } 892 893 static void 894 gv100_disp_exception(struct nvkm_disp *disp, int chid) 895 { 896 struct nvkm_subdev *subdev = &disp->engine.subdev; 897 struct nvkm_device *device = subdev->device; 898 u32 stat = nvkm_rd32(device, 0x611020 + (chid * 12)); 899 u32 type = (stat & 0x00007000) >> 12; 900 u32 mthd = (stat & 0x00000fff) << 2; 901 const struct nvkm_enum *reason = 902 nvkm_enum_find(nv50_disp_intr_error_type, type); 903 904 /*TODO: Suspect 33->41 are for WRBK channel exceptions, but we 905 * don't support those currently. 906 * 907 * CORE+WIN CHIDs map directly to the FE_EXCEPT() slots. 908 */ 909 if (chid <= 32) { 910 u32 data = nvkm_rd32(device, 0x611024 + (chid * 12)); 911 u32 code = nvkm_rd32(device, 0x611028 + (chid * 12)); 912 nvkm_error(subdev, "chid %d stat %08x reason %d [%s] " 913 "mthd %04x data %08x code %08x\n", 914 chid, stat, type, reason ? reason->name : "", 915 mthd, data, code); 916 } else { 917 nvkm_error(subdev, "chid %d stat %08x reason %d [%s] " 918 "mthd %04x\n", 919 chid, stat, type, reason ? reason->name : "", mthd); 920 } 921 922 if (chid < ARRAY_SIZE(disp->chan) && disp->chan[chid]) { 923 switch (mthd) { 924 case 0x0200: 925 nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR); 926 break; 927 default: 928 break; 929 } 930 } 931 932 nvkm_wr32(device, 0x611020 + (chid * 12), 0x90000000); 933 } 934 935 static void 936 gv100_disp_intr_ctrl_disp(struct nvkm_disp *disp) 937 { 938 struct nvkm_subdev *subdev = &disp->engine.subdev; 939 struct nvkm_device *device = subdev->device; 940 u32 stat = nvkm_rd32(device, 0x611c30); 941 942 if (stat & 0x00000007) { 943 disp->super.pending = (stat & 0x00000007); 944 queue_work(disp->super.wq, &disp->super.work); 945 nvkm_wr32(device, 0x611860, disp->super.pending); 946 stat &= ~0x00000007; 947 } 948 949 /*TODO: I would guess this is VBIOS_RELEASE, however, NFI how to 950 * ACK it, nor does RM appear to bother. 951 */ 952 if (stat & 0x00000008) 953 stat &= ~0x00000008; 954 955 if (stat & 0x00000080) { 956 u32 error = nvkm_mask(device, 0x611848, 0x00000000, 0x00000000); 957 nvkm_warn(subdev, "error %08x\n", error); 958 stat &= ~0x00000080; 959 } 960 961 if (stat & 0x00000100) { 962 unsigned long wndws = nvkm_rd32(device, 0x611858); 963 unsigned long other = nvkm_rd32(device, 0x61185c); 964 int wndw; 965 966 nvkm_wr32(device, 0x611858, wndws); 967 nvkm_wr32(device, 0x61185c, other); 968 969 /* AWAKEN_OTHER_CORE. */ 970 if (other & 0x00000001) 971 nv50_disp_chan_uevent_send(disp, 0); 972 973 /* AWAKEN_WIN_CH(n). */ 974 for_each_set_bit(wndw, &wndws, disp->wndw.nr) { 975 nv50_disp_chan_uevent_send(disp, 1 + wndw); 976 } 977 } 978 979 if (stat) 980 nvkm_warn(subdev, "ctrl %08x\n", stat); 981 } 982 983 static void 984 gv100_disp_intr_exc_other(struct nvkm_disp *disp) 985 { 986 struct nvkm_subdev *subdev = &disp->engine.subdev; 987 struct nvkm_device *device = subdev->device; 988 u32 stat = nvkm_rd32(device, 0x611854); 989 unsigned long mask; 990 int head; 991 992 if (stat & 0x00000001) { 993 nvkm_wr32(device, 0x611854, 0x00000001); 994 gv100_disp_exception(disp, 0); 995 stat &= ~0x00000001; 996 } 997 998 if ((mask = (stat & 0x00ff0000) >> 16)) { 999 for_each_set_bit(head, &mask, disp->wndw.nr) { 1000 nvkm_wr32(device, 0x611854, 0x00010000 << head); 1001 gv100_disp_exception(disp, 73 + head); 1002 stat &= ~(0x00010000 << head); 1003 } 1004 } 1005 1006 if (stat) { 1007 nvkm_warn(subdev, "exception %08x\n", stat); 1008 nvkm_wr32(device, 0x611854, stat); 1009 } 1010 } 1011 1012 static void 1013 gv100_disp_intr_exc_winim(struct nvkm_disp *disp) 1014 { 1015 struct nvkm_subdev *subdev = &disp->engine.subdev; 1016 struct nvkm_device *device = subdev->device; 1017 unsigned long stat = nvkm_rd32(device, 0x611850); 1018 int wndw; 1019 1020 for_each_set_bit(wndw, &stat, disp->wndw.nr) { 1021 nvkm_wr32(device, 0x611850, BIT(wndw)); 1022 gv100_disp_exception(disp, 33 + wndw); 1023 stat &= ~BIT(wndw); 1024 } 1025 1026 if (stat) { 1027 nvkm_warn(subdev, "wimm %08x\n", (u32)stat); 1028 nvkm_wr32(device, 0x611850, stat); 1029 } 1030 } 1031 1032 static void 1033 gv100_disp_intr_exc_win(struct nvkm_disp *disp) 1034 { 1035 struct nvkm_subdev *subdev = &disp->engine.subdev; 1036 struct nvkm_device *device = subdev->device; 1037 unsigned long stat = nvkm_rd32(device, 0x61184c); 1038 int wndw; 1039 1040 for_each_set_bit(wndw, &stat, disp->wndw.nr) { 1041 nvkm_wr32(device, 0x61184c, BIT(wndw)); 1042 gv100_disp_exception(disp, 1 + wndw); 1043 stat &= ~BIT(wndw); 1044 } 1045 1046 if (stat) { 1047 nvkm_warn(subdev, "wndw %08x\n", (u32)stat); 1048 nvkm_wr32(device, 0x61184c, stat); 1049 } 1050 } 1051 1052 static void 1053 gv100_disp_intr_head_timing(struct nvkm_disp *disp, int head) 1054 { 1055 struct nvkm_subdev *subdev = &disp->engine.subdev; 1056 struct nvkm_device *device = subdev->device; 1057 u32 stat = nvkm_rd32(device, 0x611800 + (head * 0x04)); 1058 1059 /* LAST_DATA, LOADV. */ 1060 if (stat & 0x00000003) { 1061 nvkm_wr32(device, 0x611800 + (head * 0x04), stat & 0x00000003); 1062 stat &= ~0x00000003; 1063 } 1064 1065 if (stat & 0x00000004) { 1066 nvkm_disp_vblank(disp, head); 1067 nvkm_wr32(device, 0x611800 + (head * 0x04), 0x00000004); 1068 stat &= ~0x00000004; 1069 } 1070 1071 if (stat) { 1072 nvkm_warn(subdev, "head %08x\n", stat); 1073 nvkm_wr32(device, 0x611800 + (head * 0x04), stat); 1074 } 1075 } 1076 1077 void 1078 gv100_disp_intr(struct nvkm_disp *disp) 1079 { 1080 struct nvkm_subdev *subdev = &disp->engine.subdev; 1081 struct nvkm_device *device = subdev->device; 1082 u32 stat = nvkm_rd32(device, 0x611ec0); 1083 unsigned long mask; 1084 int head; 1085 1086 if ((mask = (stat & 0x000000ff))) { 1087 for_each_set_bit(head, &mask, 8) { 1088 gv100_disp_intr_head_timing(disp, head); 1089 stat &= ~BIT(head); 1090 } 1091 } 1092 1093 if (stat & 0x00000200) { 1094 gv100_disp_intr_exc_win(disp); 1095 stat &= ~0x00000200; 1096 } 1097 1098 if (stat & 0x00000400) { 1099 gv100_disp_intr_exc_winim(disp); 1100 stat &= ~0x00000400; 1101 } 1102 1103 if (stat & 0x00000800) { 1104 gv100_disp_intr_exc_other(disp); 1105 stat &= ~0x00000800; 1106 } 1107 1108 if (stat & 0x00001000) { 1109 gv100_disp_intr_ctrl_disp(disp); 1110 stat &= ~0x00001000; 1111 } 1112 1113 if (stat) 1114 nvkm_warn(subdev, "intr %08x\n", stat); 1115 } 1116 1117 void 1118 gv100_disp_fini(struct nvkm_disp *disp) 1119 { 1120 struct nvkm_device *device = disp->engine.subdev.device; 1121 nvkm_wr32(device, 0x611db0, 0x00000000); 1122 } 1123 1124 static int 1125 gv100_disp_init(struct nvkm_disp *disp) 1126 { 1127 struct nvkm_device *device = disp->engine.subdev.device; 1128 struct nvkm_head *head; 1129 int i, j; 1130 u32 tmp; 1131 1132 /* Claim ownership of display. */ 1133 if (nvkm_rd32(device, 0x6254e8) & 0x00000002) { 1134 nvkm_mask(device, 0x6254e8, 0x00000001, 0x00000000); 1135 if (nvkm_msec(device, 2000, 1136 if (!(nvkm_rd32(device, 0x6254e8) & 0x00000002)) 1137 break; 1138 ) < 0) 1139 return -EBUSY; 1140 } 1141 1142 /* Lock pin capabilities. */ 1143 tmp = nvkm_rd32(device, 0x610068); 1144 nvkm_wr32(device, 0x640008, tmp); 1145 1146 /* SOR capabilities. */ 1147 for (i = 0; i < disp->sor.nr; i++) { 1148 tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); 1149 nvkm_mask(device, 0x640000, 0x00000100 << i, 0x00000100 << i); 1150 nvkm_wr32(device, 0x640144 + (i * 0x08), tmp); 1151 } 1152 1153 /* Head capabilities. */ 1154 list_for_each_entry(head, &disp->heads, head) { 1155 const int id = head->id; 1156 1157 /* RG. */ 1158 tmp = nvkm_rd32(device, 0x616300 + (id * 0x800)); 1159 nvkm_wr32(device, 0x640048 + (id * 0x020), tmp); 1160 1161 /* POSTCOMP. */ 1162 for (j = 0; j < 6 * 4; j += 4) { 1163 tmp = nvkm_rd32(device, 0x616100 + (id * 0x800) + j); 1164 nvkm_wr32(device, 0x640030 + (id * 0x20) + j, tmp); 1165 } 1166 } 1167 1168 /* Window capabilities. */ 1169 for (i = 0; i < disp->wndw.nr; i++) { 1170 nvkm_mask(device, 0x640004, 1 << i, 1 << i); 1171 for (j = 0; j < 6 * 4; j += 4) { 1172 tmp = nvkm_rd32(device, 0x630050 + (i * 0x800) + j); 1173 nvkm_wr32(device, 0x6401e4 + (i * 0x20) + j, tmp); 1174 } 1175 } 1176 1177 /* IHUB capabilities. */ 1178 for (i = 0; i < 4; i++) { 1179 tmp = nvkm_rd32(device, 0x62e000 + (i * 0x04)); 1180 nvkm_wr32(device, 0x640010 + (i * 0x04), tmp); 1181 } 1182 1183 nvkm_mask(device, 0x610078, 0x00000001, 0x00000001); 1184 1185 /* Setup instance memory. */ 1186 switch (nvkm_memory_target(disp->inst->memory)) { 1187 case NVKM_MEM_TARGET_VRAM: tmp = 0x00000001; break; 1188 case NVKM_MEM_TARGET_NCOH: tmp = 0x00000002; break; 1189 case NVKM_MEM_TARGET_HOST: tmp = 0x00000003; break; 1190 default: 1191 break; 1192 } 1193 nvkm_wr32(device, 0x610010, 0x00000008 | tmp); 1194 nvkm_wr32(device, 0x610014, disp->inst->addr >> 16); 1195 1196 /* CTRL_DISP: AWAKEN, ERROR, SUPERVISOR[1-3]. */ 1197 nvkm_wr32(device, 0x611cf0, 0x00000187); /* MSK. */ 1198 nvkm_wr32(device, 0x611db0, 0x00000187); /* EN. */ 1199 1200 /* EXC_OTHER: CURSn, CORE. */ 1201 nvkm_wr32(device, 0x611cec, disp->head.mask << 16 | 1202 0x00000001); /* MSK. */ 1203 nvkm_wr32(device, 0x611dac, 0x00000000); /* EN. */ 1204 1205 /* EXC_WINIM. */ 1206 nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */ 1207 nvkm_wr32(device, 0x611da8, 0x00000000); /* EN. */ 1208 1209 /* EXC_WIN. */ 1210 nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */ 1211 nvkm_wr32(device, 0x611da4, 0x00000000); /* EN. */ 1212 1213 /* HEAD_TIMING(n): VBLANK. */ 1214 list_for_each_entry(head, &disp->heads, head) { 1215 const u32 hoff = head->id * 4; 1216 nvkm_wr32(device, 0x611cc0 + hoff, 0x00000004); /* MSK. */ 1217 nvkm_wr32(device, 0x611d80 + hoff, 0x00000000); /* EN. */ 1218 } 1219 1220 /* OR. */ 1221 nvkm_wr32(device, 0x611cf4, 0x00000000); /* MSK. */ 1222 nvkm_wr32(device, 0x611db4, 0x00000000); /* EN. */ 1223 return 0; 1224 } 1225 1226 static const struct nvkm_disp_func 1227 gv100_disp = { 1228 .oneinit = nv50_disp_oneinit, 1229 .init = gv100_disp_init, 1230 .fini = gv100_disp_fini, 1231 .intr = gv100_disp_intr, 1232 .super = gv100_disp_super, 1233 .uevent = &gv100_disp_chan_uevent, 1234 .wndw = { .cnt = gv100_disp_wndw_cnt }, 1235 .head = { .cnt = gv100_head_cnt, .new = gv100_head_new }, 1236 .sor = { .cnt = gv100_sor_cnt, .new = gv100_sor_new }, 1237 .ramht_size = 0x2000, 1238 .root = { 0, 0,GV100_DISP }, 1239 .user = { 1240 {{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new }, 1241 {{ 0, 0,GV100_DISP_CURSOR }, nvkm_disp_chan_new, &gv100_disp_curs }, 1242 {{ 0, 0,GV100_DISP_WINDOW_IMM_CHANNEL_DMA}, nvkm_disp_wndw_new, &gv100_disp_wimm }, 1243 {{ 0, 0,GV100_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, &gv100_disp_core }, 1244 {{ 0, 0,GV100_DISP_WINDOW_CHANNEL_DMA }, nvkm_disp_wndw_new, &gv100_disp_wndw }, 1245 {} 1246 }, 1247 }; 1248 1249 int 1250 gv100_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 1251 struct nvkm_disp **pdisp) 1252 { 1253 return nvkm_disp_new_(&gv100_disp, device, type, inst, pdisp); 1254 } 1255