1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 26 #include <nvif/class.h> 27 28 /******************************************************************************* 29 * Base display object 30 ******************************************************************************/ 31 32 static struct nvkm_oclass 33 gm107_disp_sclass[] = { 34 { GM107_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base }, 35 { GK110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base }, 36 { GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base }, 37 { GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base }, 38 { GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base }, 39 {} 40 }; 41 42 static struct nvkm_oclass 43 gm107_disp_main_oclass[] = { 44 { GM107_DISP, &gf110_disp_main_ofuncs }, 45 {} 46 }; 47 48 /******************************************************************************* 49 * Display engine implementation 50 ******************************************************************************/ 51 52 static int 53 gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 54 struct nvkm_oclass *oclass, void *data, u32 size, 55 struct nvkm_object **pobject) 56 { 57 struct nv50_disp_priv *priv; 58 int heads = nv_rd32(parent, 0x022448); 59 int ret; 60 61 ret = nvkm_disp_create(parent, engine, oclass, heads, 62 "PDISP", "display", &priv); 63 *pobject = nv_object(priv); 64 if (ret) 65 return ret; 66 67 ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent); 68 if (ret) 69 return ret; 70 71 nv_engine(priv)->sclass = gm107_disp_main_oclass; 72 nv_engine(priv)->cclass = &nv50_disp_cclass; 73 nv_subdev(priv)->intr = gf110_disp_intr; 74 INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor); 75 priv->sclass = gm107_disp_sclass; 76 priv->head.nr = heads; 77 priv->dac.nr = 3; 78 priv->sor.nr = 4; 79 priv->dac.power = nv50_dac_power; 80 priv->dac.sense = nv50_dac_sense; 81 priv->sor.power = nv50_sor_power; 82 priv->sor.hda_eld = gf110_hda_eld; 83 priv->sor.hdmi = gk104_hdmi_ctrl; 84 return 0; 85 } 86 87 struct nvkm_oclass * 88 gm107_disp_oclass = &(struct nv50_disp_impl) { 89 .base.base.handle = NV_ENGINE(DISP, 0x07), 90 .base.base.ofuncs = &(struct nvkm_ofuncs) { 91 .ctor = gm107_disp_ctor, 92 .dtor = _nvkm_disp_dtor, 93 .init = _nvkm_disp_init, 94 .fini = _nvkm_disp_fini, 95 }, 96 .base.vblank = &gf110_disp_vblank_func, 97 .base.outp = gf110_disp_outp_sclass, 98 .mthd.core = &gk104_disp_core_mthd_chan, 99 .mthd.base = &gf110_disp_base_mthd_chan, 100 .mthd.ovly = &gk104_disp_ovly_mthd_chan, 101 .mthd.prev = -0x020000, 102 .head.scanoutpos = gf110_disp_main_scanoutpos, 103 }.base.base; 104