1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25 #include <engine/sw.h> 26 #include <engine/disp.h> 27 28 #include <nvif/class.h> 29 30 #include "nv50.h" 31 32 /******************************************************************************* 33 * Base display object 34 ******************************************************************************/ 35 36 static struct nouveau_oclass 37 gm107_disp_sclass[] = { 38 { GM107_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base }, 39 { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base }, 40 { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, 41 { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, 42 { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, 43 {} 44 }; 45 46 static struct nouveau_oclass 47 gm107_disp_main_oclass[] = { 48 { GM107_DISP, &nvd0_disp_main_ofuncs }, 49 {} 50 }; 51 52 /******************************************************************************* 53 * Display engine implementation 54 ******************************************************************************/ 55 56 static int 57 gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 58 struct nouveau_oclass *oclass, void *data, u32 size, 59 struct nouveau_object **pobject) 60 { 61 struct nv50_disp_priv *priv; 62 int heads = nv_rd32(parent, 0x022448); 63 int ret; 64 65 ret = nouveau_disp_create(parent, engine, oclass, heads, 66 "PDISP", "display", &priv); 67 *pobject = nv_object(priv); 68 if (ret) 69 return ret; 70 71 ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent); 72 if (ret) 73 return ret; 74 75 nv_engine(priv)->sclass = gm107_disp_main_oclass; 76 nv_engine(priv)->cclass = &nv50_disp_cclass; 77 nv_subdev(priv)->intr = nvd0_disp_intr; 78 INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); 79 priv->sclass = gm107_disp_sclass; 80 priv->head.nr = heads; 81 priv->dac.nr = 3; 82 priv->sor.nr = 4; 83 priv->dac.power = nv50_dac_power; 84 priv->dac.sense = nv50_dac_sense; 85 priv->sor.power = nv50_sor_power; 86 priv->sor.hda_eld = nvd0_hda_eld; 87 priv->sor.hdmi = nve0_hdmi_ctrl; 88 return 0; 89 } 90 91 struct nouveau_oclass * 92 gm107_disp_oclass = &(struct nv50_disp_impl) { 93 .base.base.handle = NV_ENGINE(DISP, 0x07), 94 .base.base.ofuncs = &(struct nouveau_ofuncs) { 95 .ctor = gm107_disp_ctor, 96 .dtor = _nouveau_disp_dtor, 97 .init = _nouveau_disp_init, 98 .fini = _nouveau_disp_fini, 99 }, 100 .base.vblank = &nvd0_disp_vblank_func, 101 .base.outp = nvd0_disp_outp_sclass, 102 .mthd.core = &nve0_disp_core_mthd_chan, 103 .mthd.base = &nvd0_disp_base_mthd_chan, 104 .mthd.ovly = &nve0_disp_ovly_mthd_chan, 105 .mthd.prev = -0x020000, 106 .head.scanoutpos = nvd0_disp_main_scanoutpos, 107 }.base.base; 108