1 /*
2  * Copyright 2021 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 #include "priv.h"
23 #include "chan.h"
24 #include "head.h"
25 #include "ior.h"
26 
27 #include <subdev/timer.h>
28 
29 #include <nvif/class.h>
30 
31 static int
32 ga102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
33 {
34 	struct nvkm_device *device = sor->disp->engine.subdev.device;
35 	const u32 soff = nv50_ior_base(sor);
36 	const u32 loff = nv50_sor_link(sor);
37 	u32 dpctrl = 0x00000000;
38 	u32 clksor = 0x00000000;
39 
40 	switch (sor->dp.bw) {
41 	case 0x06: clksor |= 0x00000000; break;
42 	case 0x0a: clksor |= 0x00040000; break;
43 	case 0x14: clksor |= 0x00080000; break;
44 	case 0x1e: clksor |= 0x000c0000; break;
45 	case 0x08: clksor |= 0x00100000; break;
46 	case 0x09: clksor |= 0x00140000; break;
47 	case 0x0c: clksor |= 0x00180000; break;
48 	case 0x10: clksor |= 0x001c0000; break;
49 	default:
50 		WARN_ON(1);
51 		return -EINVAL;
52 	}
53 
54 	dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
55 	if (sor->dp.mst)
56 		dpctrl |= 0x40000000;
57 	if (sor->dp.ef)
58 		dpctrl |= 0x00004000;
59 
60 	nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
61 
62 	/*XXX*/
63 	nvkm_msec(device, 40, NVKM_DELAY);
64 	nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000);
65 	nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001);
66 
67 	nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
68 	return 0;
69 }
70 
71 static const struct nvkm_ior_func_dp
72 ga102_sor_dp = {
73 	.lanes = { 0, 1, 2, 3 },
74 	.links = ga102_sor_dp_links,
75 	.power = g94_sor_dp_power,
76 	.pattern = gm107_sor_dp_pattern,
77 	.drive = gm200_sor_dp_drive,
78 	.vcpi = tu102_sor_dp_vcpi,
79 	.audio = gv100_sor_dp_audio,
80 	.audio_sym = gv100_sor_dp_audio_sym,
81 	.watermark = gv100_sor_dp_watermark,
82 };
83 
84 static void
85 ga102_sor_clock(struct nvkm_ior *sor)
86 {
87 	struct nvkm_device *device = sor->disp->engine.subdev.device;
88 	u32 div2 = 0;
89 
90 	if (sor->asy.proto == TMDS) {
91 		if (sor->tmds.high_speed)
92 			div2 = 1;
93 	}
94 
95 	nvkm_wr32(device, 0x00ec08 + (sor->id * 0x10), 0x00000000);
96 	nvkm_wr32(device, 0x00ec04 + (sor->id * 0x10), div2);
97 }
98 
99 static const struct nvkm_ior_func
100 ga102_sor = {
101 	.route = {
102 		.get = gm200_sor_route_get,
103 		.set = gm200_sor_route_set,
104 	},
105 	.state = gv100_sor_state,
106 	.power = nv50_sor_power,
107 	.clock = ga102_sor_clock,
108 	.hdmi = &gv100_sor_hdmi,
109 	.dp = &ga102_sor_dp,
110 	.hda = &gv100_sor_hda,
111 };
112 
113 static int
114 ga102_sor_new(struct nvkm_disp *disp, int id)
115 {
116 	struct nvkm_device *device = disp->engine.subdev.device;
117 	u32 hda = nvkm_rd32(device, 0x08a15c);
118 
119 	return nvkm_ior_new_(&ga102_sor, disp, SOR, id, hda & BIT(id));
120 }
121 
122 static const struct nvkm_disp_func
123 ga102_disp = {
124 	.oneinit = nv50_disp_oneinit,
125 	.init = tu102_disp_init,
126 	.fini = gv100_disp_fini,
127 	.intr = gv100_disp_intr,
128 	.super = gv100_disp_super,
129 	.uevent = &gv100_disp_chan_uevent,
130 	.wndw = { .cnt = gv100_disp_wndw_cnt },
131 	.head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
132 	.sor = { .cnt = gv100_sor_cnt, .new = ga102_sor_new },
133 	.ramht_size = 0x2000,
134 	.root = {  0, 0,GA102_DISP },
135 	.user = {
136 		{{-1,-1,GV100_DISP_CAPS                  }, gv100_disp_caps_new },
137 		{{ 0, 0,GA102_DISP_CURSOR                }, nvkm_disp_chan_new, &gv100_disp_curs },
138 		{{ 0, 0,GA102_DISP_WINDOW_IMM_CHANNEL_DMA}, nvkm_disp_wndw_new, &gv100_disp_wimm },
139 		{{ 0, 0,GA102_DISP_CORE_CHANNEL_DMA      }, nvkm_disp_core_new, &gv100_disp_core },
140 		{{ 0, 0,GA102_DISP_WINDOW_CHANNEL_DMA    }, nvkm_disp_wndw_new, &gv100_disp_wndw },
141 		{}
142 	},
143 };
144 
145 int
146 ga102_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
147 	       struct nvkm_disp **pdisp)
148 {
149 	return nvkm_disp_new_(&ga102_disp, device, type, inst, pdisp);
150 }
151