1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "priv.h" 25 #include "chan.h" 26 #include "hdmi.h" 27 #include "head.h" 28 #include "ior.h" 29 30 #include <nvif/class.h> 31 32 static void 33 g84_sor_hdmi_infoframe_vsi(struct nvkm_ior *ior, int head, void *data, u32 size) 34 { 35 struct nvkm_device *device = ior->disp->engine.subdev.device; 36 struct packed_hdmi_infoframe vsi; 37 const u32 hoff = head * 0x800; 38 39 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010000); 40 if (!size) 41 return; 42 43 pack_hdmi_infoframe(&vsi, data, size); 44 45 nvkm_wr32(device, 0x616544 + hoff, vsi.header); 46 nvkm_wr32(device, 0x616548 + hoff, vsi.subpack0_low); 47 nvkm_wr32(device, 0x61654c + hoff, vsi.subpack0_high); 48 /* Is there a second (or up to fourth?) set of subpack registers here? */ 49 /* nvkm_wr32(device, 0x616550 + hoff, vsi.subpack1_low); */ 50 /* nvkm_wr32(device, 0x616554 + hoff, vsi.subpack1_high); */ 51 52 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010001); 53 } 54 55 static void 56 g84_sor_hdmi_infoframe_avi(struct nvkm_ior *ior, int head, void *data, u32 size) 57 { 58 struct nvkm_device *device = ior->disp->engine.subdev.device; 59 struct packed_hdmi_infoframe avi; 60 const u32 hoff = head * 0x800; 61 62 pack_hdmi_infoframe(&avi, data, size); 63 64 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); 65 if (!size) 66 return; 67 68 nvkm_wr32(device, 0x616528 + hoff, avi.header); 69 nvkm_wr32(device, 0x61652c + hoff, avi.subpack0_low); 70 nvkm_wr32(device, 0x616530 + hoff, avi.subpack0_high); 71 nvkm_wr32(device, 0x616534 + hoff, avi.subpack1_low); 72 nvkm_wr32(device, 0x616538 + hoff, avi.subpack1_high); 73 74 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000001); 75 } 76 77 78 static void 79 g84_sor_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet, u8 rekey) 80 { 81 struct nvkm_device *device = ior->disp->engine.subdev.device; 82 const u32 ctrl = 0x40000000 * enable | 83 0x1f000000 /* ??? */ | 84 max_ac_packet << 16 | 85 rekey; 86 const u32 hoff = head * 0x800; 87 88 if (!(ctrl & 0x40000000)) { 89 nvkm_mask(device, 0x6165a4 + hoff, 0x40000000, 0x00000000); 90 nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000); 91 return; 92 } 93 94 /* Audio InfoFrame */ 95 nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000); 96 nvkm_wr32(device, 0x616508 + hoff, 0x000a0184); 97 nvkm_wr32(device, 0x61650c + hoff, 0x00000071); 98 nvkm_wr32(device, 0x616510 + hoff, 0x00000000); 99 nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000001); 100 101 102 nvkm_mask(device, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ 103 nvkm_mask(device, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ 104 nvkm_mask(device, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ 105 106 /* ??? */ 107 nvkm_mask(device, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ 108 nvkm_mask(device, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ 109 nvkm_mask(device, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */ 110 111 /* HDMI_CTRL */ 112 nvkm_mask(device, 0x6165a4 + hoff, 0x5f1f007f, ctrl); 113 } 114 115 const struct nvkm_ior_func_hdmi 116 g84_sor_hdmi = { 117 .ctrl = g84_sor_hdmi_ctrl, 118 .infoframe_avi = g84_sor_hdmi_infoframe_avi, 119 .infoframe_vsi = g84_sor_hdmi_infoframe_vsi, 120 }; 121 122 static const struct nvkm_ior_func 123 g84_sor = { 124 .state = nv50_sor_state, 125 .power = nv50_sor_power, 126 .clock = nv50_sor_clock, 127 .hdmi = &g84_sor_hdmi, 128 }; 129 130 int 131 g84_sor_new(struct nvkm_disp *disp, int id) 132 { 133 return nvkm_ior_new_(&g84_sor, disp, SOR, id, false); 134 } 135 136 static const struct nvkm_disp_mthd_list 137 g84_disp_ovly_mthd_base = { 138 .mthd = 0x0000, 139 .addr = 0x000000, 140 .data = { 141 { 0x0080, 0x000000 }, 142 { 0x0084, 0x6109a0 }, 143 { 0x0088, 0x6109c0 }, 144 { 0x008c, 0x6109c8 }, 145 { 0x0090, 0x6109b4 }, 146 { 0x0094, 0x610970 }, 147 { 0x00a0, 0x610998 }, 148 { 0x00a4, 0x610964 }, 149 { 0x00c0, 0x610958 }, 150 { 0x00e0, 0x6109a8 }, 151 { 0x00e4, 0x6109d0 }, 152 { 0x00e8, 0x6109d8 }, 153 { 0x0100, 0x61094c }, 154 { 0x0104, 0x610984 }, 155 { 0x0108, 0x61098c }, 156 { 0x0800, 0x6109f8 }, 157 { 0x0808, 0x610a08 }, 158 { 0x080c, 0x610a10 }, 159 { 0x0810, 0x610a00 }, 160 {} 161 } 162 }; 163 164 static const struct nvkm_disp_chan_mthd 165 g84_disp_ovly_mthd = { 166 .name = "Overlay", 167 .addr = 0x000540, 168 .prev = 0x000004, 169 .data = { 170 { "Global", 1, &g84_disp_ovly_mthd_base }, 171 {} 172 } 173 }; 174 175 const struct nvkm_disp_chan_user 176 g84_disp_ovly = { 177 .func = &nv50_disp_dmac_func, 178 .ctrl = 3, 179 .user = 3, 180 .mthd = &g84_disp_ovly_mthd, 181 }; 182 183 static const struct nvkm_disp_mthd_list 184 g84_disp_base_mthd_base = { 185 .mthd = 0x0000, 186 .addr = 0x000000, 187 .data = { 188 { 0x0080, 0x000000 }, 189 { 0x0084, 0x0008c4 }, 190 { 0x0088, 0x0008d0 }, 191 { 0x008c, 0x0008dc }, 192 { 0x0090, 0x0008e4 }, 193 { 0x0094, 0x610884 }, 194 { 0x00a0, 0x6108a0 }, 195 { 0x00a4, 0x610878 }, 196 { 0x00c0, 0x61086c }, 197 { 0x00c4, 0x610800 }, 198 { 0x00c8, 0x61080c }, 199 { 0x00cc, 0x610818 }, 200 { 0x00e0, 0x610858 }, 201 { 0x00e4, 0x610860 }, 202 { 0x00e8, 0x6108ac }, 203 { 0x00ec, 0x6108b4 }, 204 { 0x00fc, 0x610824 }, 205 { 0x0100, 0x610894 }, 206 { 0x0104, 0x61082c }, 207 { 0x0110, 0x6108bc }, 208 { 0x0114, 0x61088c }, 209 {} 210 } 211 }; 212 213 static const struct nvkm_disp_chan_mthd 214 g84_disp_base_mthd = { 215 .name = "Base", 216 .addr = 0x000540, 217 .prev = 0x000004, 218 .data = { 219 { "Global", 1, &g84_disp_base_mthd_base }, 220 { "Image", 2, &nv50_disp_base_mthd_image }, 221 {} 222 } 223 }; 224 225 const struct nvkm_disp_chan_user 226 g84_disp_base = { 227 .func = &nv50_disp_dmac_func, 228 .ctrl = 1, 229 .user = 1, 230 .mthd = &g84_disp_base_mthd, 231 }; 232 233 const struct nvkm_disp_mthd_list 234 g84_disp_core_mthd_dac = { 235 .mthd = 0x0080, 236 .addr = 0x000008, 237 .data = { 238 { 0x0400, 0x610b58 }, 239 { 0x0404, 0x610bdc }, 240 { 0x0420, 0x610bc4 }, 241 {} 242 } 243 }; 244 245 const struct nvkm_disp_mthd_list 246 g84_disp_core_mthd_head = { 247 .mthd = 0x0400, 248 .addr = 0x000540, 249 .data = { 250 { 0x0800, 0x610ad8 }, 251 { 0x0804, 0x610ad0 }, 252 { 0x0808, 0x610a48 }, 253 { 0x080c, 0x610a78 }, 254 { 0x0810, 0x610ac0 }, 255 { 0x0814, 0x610af8 }, 256 { 0x0818, 0x610b00 }, 257 { 0x081c, 0x610ae8 }, 258 { 0x0820, 0x610af0 }, 259 { 0x0824, 0x610b08 }, 260 { 0x0828, 0x610b10 }, 261 { 0x082c, 0x610a68 }, 262 { 0x0830, 0x610a60 }, 263 { 0x0834, 0x000000 }, 264 { 0x0838, 0x610a40 }, 265 { 0x0840, 0x610a24 }, 266 { 0x0844, 0x610a2c }, 267 { 0x0848, 0x610aa8 }, 268 { 0x084c, 0x610ab0 }, 269 { 0x085c, 0x610c5c }, 270 { 0x0860, 0x610a84 }, 271 { 0x0864, 0x610a90 }, 272 { 0x0868, 0x610b18 }, 273 { 0x086c, 0x610b20 }, 274 { 0x0870, 0x610ac8 }, 275 { 0x0874, 0x610a38 }, 276 { 0x0878, 0x610c50 }, 277 { 0x0880, 0x610a58 }, 278 { 0x0884, 0x610a9c }, 279 { 0x089c, 0x610c68 }, 280 { 0x08a0, 0x610a70 }, 281 { 0x08a4, 0x610a50 }, 282 { 0x08a8, 0x610ae0 }, 283 { 0x08c0, 0x610b28 }, 284 { 0x08c4, 0x610b30 }, 285 { 0x08c8, 0x610b40 }, 286 { 0x08d4, 0x610b38 }, 287 { 0x08d8, 0x610b48 }, 288 { 0x08dc, 0x610b50 }, 289 { 0x0900, 0x610a18 }, 290 { 0x0904, 0x610ab8 }, 291 { 0x0910, 0x610c70 }, 292 { 0x0914, 0x610c78 }, 293 {} 294 } 295 }; 296 297 const struct nvkm_disp_chan_mthd 298 g84_disp_core_mthd = { 299 .name = "Core", 300 .addr = 0x000000, 301 .prev = 0x000004, 302 .data = { 303 { "Global", 1, &nv50_disp_core_mthd_base }, 304 { "DAC", 3, &g84_disp_core_mthd_dac }, 305 { "SOR", 2, &nv50_disp_core_mthd_sor }, 306 { "PIOR", 3, &nv50_disp_core_mthd_pior }, 307 { "HEAD", 2, &g84_disp_core_mthd_head }, 308 {} 309 } 310 }; 311 312 const struct nvkm_disp_chan_user 313 g84_disp_core = { 314 .func = &nv50_disp_core_func, 315 .ctrl = 0, 316 .user = 0, 317 .mthd = &g84_disp_core_mthd, 318 }; 319 320 static const struct nvkm_disp_func 321 g84_disp = { 322 .oneinit = nv50_disp_oneinit, 323 .init = nv50_disp_init, 324 .fini = nv50_disp_fini, 325 .intr = nv50_disp_intr, 326 .super = nv50_disp_super, 327 .uevent = &nv50_disp_chan_uevent, 328 .head = { .cnt = nv50_head_cnt, .new = nv50_head_new }, 329 .dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new }, 330 .sor = { .cnt = nv50_sor_cnt, .new = g84_sor_new }, 331 .pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new }, 332 .root = { 0,0,G82_DISP }, 333 .user = { 334 {{0,0,G82_DISP_CURSOR }, nvkm_disp_chan_new, &nv50_disp_curs }, 335 {{0,0,G82_DISP_OVERLAY }, nvkm_disp_chan_new, &nv50_disp_oimm }, 336 {{0,0,G82_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, & g84_disp_base }, 337 {{0,0,G82_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, & g84_disp_core }, 338 {{0,0,G82_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, & g84_disp_ovly }, 339 {} 340 }, 341 }; 342 343 int 344 g84_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 345 struct nvkm_disp **pdisp) 346 { 347 return nvkm_disp_new_(&g84_disp, device, type, inst, pdisp); 348 } 349