1 #ifndef __NVKM_DISP_DP_H__ 2 #define __NVKM_DISP_DP_H__ 3 #define nvkm_dp(p) container_of((p), struct nvkm_dp, outp) 4 #include "outp.h" 5 6 #include <core/notify.h> 7 #include <subdev/bios.h> 8 #include <subdev/bios/dp.h> 9 10 struct nvkm_dp { 11 union { 12 struct nvkm_outp base; 13 struct nvkm_outp outp; 14 }; 15 16 struct nvbios_dpout info; 17 u8 version; 18 19 struct nvkm_i2c_aux *aux; 20 21 struct nvkm_notify hpd; 22 bool present; 23 u8 dpcd[16]; 24 25 struct mutex mutex; 26 struct { 27 atomic_t done; 28 bool mst; 29 } lt; 30 }; 31 32 int nvkm_dp_new(struct nvkm_disp *, int index, struct dcb_output *, 33 struct nvkm_outp **); 34 35 /* DPCD Receiver Capabilities */ 36 #define DPCD_RC00_DPCD_REV 0x00000 37 #define DPCD_RC01_MAX_LINK_RATE 0x00001 38 #define DPCD_RC02 0x00002 39 #define DPCD_RC02_ENHANCED_FRAME_CAP 0x80 40 #define DPCD_RC02_TPS3_SUPPORTED 0x40 41 #define DPCD_RC02_MAX_LANE_COUNT 0x1f 42 #define DPCD_RC03 0x00003 43 #define DPCD_RC03_MAX_DOWNSPREAD 0x01 44 #define DPCD_RC0E_AUX_RD_INTERVAL 0x0000e 45 46 /* DPCD Link Configuration */ 47 #define DPCD_LC00_LINK_BW_SET 0x00100 48 #define DPCD_LC01 0x00101 49 #define DPCD_LC01_ENHANCED_FRAME_EN 0x80 50 #define DPCD_LC01_LANE_COUNT_SET 0x1f 51 #define DPCD_LC02 0x00102 52 #define DPCD_LC02_TRAINING_PATTERN_SET 0x03 53 #define DPCD_LC03(l) ((l) + 0x00103) 54 #define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED 0x20 55 #define DPCD_LC03_PRE_EMPHASIS_SET 0x18 56 #define DPCD_LC03_MAX_SWING_REACHED 0x04 57 #define DPCD_LC03_VOLTAGE_SWING_SET 0x03 58 #define DPCD_LC0F 0x0010f 59 #define DPCD_LC0F_LANE1_MAX_POST_CURSOR2_REACHED 0x40 60 #define DPCD_LC0F_LANE1_POST_CURSOR2_SET 0x30 61 #define DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED 0x04 62 #define DPCD_LC0F_LANE0_POST_CURSOR2_SET 0x03 63 #define DPCD_LC10 0x00110 64 #define DPCD_LC10_LANE3_MAX_POST_CURSOR2_REACHED 0x40 65 #define DPCD_LC10_LANE3_POST_CURSOR2_SET 0x30 66 #define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED 0x04 67 #define DPCD_LC10_LANE2_POST_CURSOR2_SET 0x03 68 69 /* DPCD Link/Sink Status */ 70 #define DPCD_LS02 0x00202 71 #define DPCD_LS02_LANE1_SYMBOL_LOCKED 0x40 72 #define DPCD_LS02_LANE1_CHANNEL_EQ_DONE 0x20 73 #define DPCD_LS02_LANE1_CR_DONE 0x10 74 #define DPCD_LS02_LANE0_SYMBOL_LOCKED 0x04 75 #define DPCD_LS02_LANE0_CHANNEL_EQ_DONE 0x02 76 #define DPCD_LS02_LANE0_CR_DONE 0x01 77 #define DPCD_LS03 0x00203 78 #define DPCD_LS03_LANE3_SYMBOL_LOCKED 0x40 79 #define DPCD_LS03_LANE3_CHANNEL_EQ_DONE 0x20 80 #define DPCD_LS03_LANE3_CR_DONE 0x10 81 #define DPCD_LS03_LANE2_SYMBOL_LOCKED 0x04 82 #define DPCD_LS03_LANE2_CHANNEL_EQ_DONE 0x02 83 #define DPCD_LS03_LANE2_CR_DONE 0x01 84 #define DPCD_LS04 0x00204 85 #define DPCD_LS04_LINK_STATUS_UPDATED 0x80 86 #define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED 0x40 87 #define DPCD_LS04_INTERLANE_ALIGN_DONE 0x01 88 #define DPCD_LS06 0x00206 89 #define DPCD_LS06_LANE1_PRE_EMPHASIS 0xc0 90 #define DPCD_LS06_LANE1_VOLTAGE_SWING 0x30 91 #define DPCD_LS06_LANE0_PRE_EMPHASIS 0x0c 92 #define DPCD_LS06_LANE0_VOLTAGE_SWING 0x03 93 #define DPCD_LS07 0x00207 94 #define DPCD_LS07_LANE3_PRE_EMPHASIS 0xc0 95 #define DPCD_LS07_LANE3_VOLTAGE_SWING 0x30 96 #define DPCD_LS07_LANE2_PRE_EMPHASIS 0x0c 97 #define DPCD_LS07_LANE2_VOLTAGE_SWING 0x03 98 #define DPCD_LS0C 0x0020c 99 #define DPCD_LS0C_LANE3_POST_CURSOR2 0xc0 100 #define DPCD_LS0C_LANE2_POST_CURSOR2 0x30 101 #define DPCD_LS0C_LANE1_POST_CURSOR2 0x0c 102 #define DPCD_LS0C_LANE0_POST_CURSOR2 0x03 103 104 /* DPCD Sink Control */ 105 #define DPCD_SC00 0x00600 106 #define DPCD_SC00_SET_POWER 0x03 107 #define DPCD_SC00_SET_POWER_D0 0x01 108 #define DPCD_SC00_SET_POWER_D3 0x03 109 #endif 110