1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "priv.h" 25 #include "acpi.h" 26 27 #include <core/option.h> 28 29 #include <subdev/bios.h> 30 #include <subdev/therm.h> 31 32 static DEFINE_MUTEX(nv_devices_mutex); 33 static LIST_HEAD(nv_devices); 34 35 static struct nvkm_device * 36 nvkm_device_find_locked(u64 handle) 37 { 38 struct nvkm_device *device; 39 list_for_each_entry(device, &nv_devices, head) { 40 if (device->handle == handle) 41 return device; 42 } 43 return NULL; 44 } 45 46 struct nvkm_device * 47 nvkm_device_find(u64 handle) 48 { 49 struct nvkm_device *device; 50 mutex_lock(&nv_devices_mutex); 51 device = nvkm_device_find_locked(handle); 52 mutex_unlock(&nv_devices_mutex); 53 return device; 54 } 55 56 int 57 nvkm_device_list(u64 *name, int size) 58 { 59 struct nvkm_device *device; 60 int nr = 0; 61 mutex_lock(&nv_devices_mutex); 62 list_for_each_entry(device, &nv_devices, head) { 63 if (nr++ < size) 64 name[nr - 1] = device->handle; 65 } 66 mutex_unlock(&nv_devices_mutex); 67 return nr; 68 } 69 70 static const struct nvkm_device_chip 71 null_chipset = { 72 .name = "NULL", 73 .bios = { 0x00000001, nvkm_bios_new }, 74 }; 75 76 static const struct nvkm_device_chip 77 nv4_chipset = { 78 .name = "NV04", 79 .bios = { 0x00000001, nvkm_bios_new }, 80 .bus = { 0x00000001, nv04_bus_new }, 81 .clk = { 0x00000001, nv04_clk_new }, 82 .devinit = { 0x00000001, nv04_devinit_new }, 83 .fb = { 0x00000001, nv04_fb_new }, 84 .i2c = { 0x00000001, nv04_i2c_new }, 85 .imem = { 0x00000001, nv04_instmem_new }, 86 .mc = { 0x00000001, nv04_mc_new }, 87 .mmu = { 0x00000001, nv04_mmu_new }, 88 .pci = { 0x00000001, nv04_pci_new }, 89 .timer = { 0x00000001, nv04_timer_new }, 90 .disp = { 0x00000001, nv04_disp_new }, 91 .dma = { 0x00000001, nv04_dma_new }, 92 .fifo = { 0x00000001, nv04_fifo_new }, 93 .gr = { 0x00000001, nv04_gr_new }, 94 .sw = { 0x00000001, nv04_sw_new }, 95 }; 96 97 static const struct nvkm_device_chip 98 nv5_chipset = { 99 .name = "NV05", 100 .bios = { 0x00000001, nvkm_bios_new }, 101 .bus = { 0x00000001, nv04_bus_new }, 102 .clk = { 0x00000001, nv04_clk_new }, 103 .devinit = { 0x00000001, nv05_devinit_new }, 104 .fb = { 0x00000001, nv04_fb_new }, 105 .i2c = { 0x00000001, nv04_i2c_new }, 106 .imem = { 0x00000001, nv04_instmem_new }, 107 .mc = { 0x00000001, nv04_mc_new }, 108 .mmu = { 0x00000001, nv04_mmu_new }, 109 .pci = { 0x00000001, nv04_pci_new }, 110 .timer = { 0x00000001, nv04_timer_new }, 111 .disp = { 0x00000001, nv04_disp_new }, 112 .dma = { 0x00000001, nv04_dma_new }, 113 .fifo = { 0x00000001, nv04_fifo_new }, 114 .gr = { 0x00000001, nv04_gr_new }, 115 .sw = { 0x00000001, nv04_sw_new }, 116 }; 117 118 static const struct nvkm_device_chip 119 nv10_chipset = { 120 .name = "NV10", 121 .bios = { 0x00000001, nvkm_bios_new }, 122 .bus = { 0x00000001, nv04_bus_new }, 123 .clk = { 0x00000001, nv04_clk_new }, 124 .devinit = { 0x00000001, nv10_devinit_new }, 125 .fb = { 0x00000001, nv10_fb_new }, 126 .gpio = { 0x00000001, nv10_gpio_new }, 127 .i2c = { 0x00000001, nv04_i2c_new }, 128 .imem = { 0x00000001, nv04_instmem_new }, 129 .mc = { 0x00000001, nv04_mc_new }, 130 .mmu = { 0x00000001, nv04_mmu_new }, 131 .pci = { 0x00000001, nv04_pci_new }, 132 .timer = { 0x00000001, nv04_timer_new }, 133 .disp = { 0x00000001, nv04_disp_new }, 134 .dma = { 0x00000001, nv04_dma_new }, 135 .gr = { 0x00000001, nv10_gr_new }, 136 }; 137 138 static const struct nvkm_device_chip 139 nv11_chipset = { 140 .name = "NV11", 141 .bios = { 0x00000001, nvkm_bios_new }, 142 .bus = { 0x00000001, nv04_bus_new }, 143 .clk = { 0x00000001, nv04_clk_new }, 144 .devinit = { 0x00000001, nv10_devinit_new }, 145 .fb = { 0x00000001, nv10_fb_new }, 146 .gpio = { 0x00000001, nv10_gpio_new }, 147 .i2c = { 0x00000001, nv04_i2c_new }, 148 .imem = { 0x00000001, nv04_instmem_new }, 149 .mc = { 0x00000001, nv11_mc_new }, 150 .mmu = { 0x00000001, nv04_mmu_new }, 151 .pci = { 0x00000001, nv04_pci_new }, 152 .timer = { 0x00000001, nv04_timer_new }, 153 .disp = { 0x00000001, nv04_disp_new }, 154 .dma = { 0x00000001, nv04_dma_new }, 155 .fifo = { 0x00000001, nv10_fifo_new }, 156 .gr = { 0x00000001, nv15_gr_new }, 157 .sw = { 0x00000001, nv10_sw_new }, 158 }; 159 160 static const struct nvkm_device_chip 161 nv15_chipset = { 162 .name = "NV15", 163 .bios = { 0x00000001, nvkm_bios_new }, 164 .bus = { 0x00000001, nv04_bus_new }, 165 .clk = { 0x00000001, nv04_clk_new }, 166 .devinit = { 0x00000001, nv10_devinit_new }, 167 .fb = { 0x00000001, nv10_fb_new }, 168 .gpio = { 0x00000001, nv10_gpio_new }, 169 .i2c = { 0x00000001, nv04_i2c_new }, 170 .imem = { 0x00000001, nv04_instmem_new }, 171 .mc = { 0x00000001, nv04_mc_new }, 172 .mmu = { 0x00000001, nv04_mmu_new }, 173 .pci = { 0x00000001, nv04_pci_new }, 174 .timer = { 0x00000001, nv04_timer_new }, 175 .disp = { 0x00000001, nv04_disp_new }, 176 .dma = { 0x00000001, nv04_dma_new }, 177 .fifo = { 0x00000001, nv10_fifo_new }, 178 .gr = { 0x00000001, nv15_gr_new }, 179 .sw = { 0x00000001, nv10_sw_new }, 180 }; 181 182 static const struct nvkm_device_chip 183 nv17_chipset = { 184 .name = "NV17", 185 .bios = { 0x00000001, nvkm_bios_new }, 186 .bus = { 0x00000001, nv04_bus_new }, 187 .clk = { 0x00000001, nv04_clk_new }, 188 .devinit = { 0x00000001, nv10_devinit_new }, 189 .fb = { 0x00000001, nv10_fb_new }, 190 .gpio = { 0x00000001, nv10_gpio_new }, 191 .i2c = { 0x00000001, nv04_i2c_new }, 192 .imem = { 0x00000001, nv04_instmem_new }, 193 .mc = { 0x00000001, nv17_mc_new }, 194 .mmu = { 0x00000001, nv04_mmu_new }, 195 .pci = { 0x00000001, nv04_pci_new }, 196 .timer = { 0x00000001, nv04_timer_new }, 197 .disp = { 0x00000001, nv04_disp_new }, 198 .dma = { 0x00000001, nv04_dma_new }, 199 .fifo = { 0x00000001, nv17_fifo_new }, 200 .gr = { 0x00000001, nv17_gr_new }, 201 .sw = { 0x00000001, nv10_sw_new }, 202 }; 203 204 static const struct nvkm_device_chip 205 nv18_chipset = { 206 .name = "NV18", 207 .bios = { 0x00000001, nvkm_bios_new }, 208 .bus = { 0x00000001, nv04_bus_new }, 209 .clk = { 0x00000001, nv04_clk_new }, 210 .devinit = { 0x00000001, nv10_devinit_new }, 211 .fb = { 0x00000001, nv10_fb_new }, 212 .gpio = { 0x00000001, nv10_gpio_new }, 213 .i2c = { 0x00000001, nv04_i2c_new }, 214 .imem = { 0x00000001, nv04_instmem_new }, 215 .mc = { 0x00000001, nv17_mc_new }, 216 .mmu = { 0x00000001, nv04_mmu_new }, 217 .pci = { 0x00000001, nv04_pci_new }, 218 .timer = { 0x00000001, nv04_timer_new }, 219 .disp = { 0x00000001, nv04_disp_new }, 220 .dma = { 0x00000001, nv04_dma_new }, 221 .fifo = { 0x00000001, nv17_fifo_new }, 222 .gr = { 0x00000001, nv17_gr_new }, 223 .sw = { 0x00000001, nv10_sw_new }, 224 }; 225 226 static const struct nvkm_device_chip 227 nv1a_chipset = { 228 .name = "nForce", 229 .bios = { 0x00000001, nvkm_bios_new }, 230 .bus = { 0x00000001, nv04_bus_new }, 231 .clk = { 0x00000001, nv04_clk_new }, 232 .devinit = { 0x00000001, nv1a_devinit_new }, 233 .fb = { 0x00000001, nv1a_fb_new }, 234 .gpio = { 0x00000001, nv10_gpio_new }, 235 .i2c = { 0x00000001, nv04_i2c_new }, 236 .imem = { 0x00000001, nv04_instmem_new }, 237 .mc = { 0x00000001, nv04_mc_new }, 238 .mmu = { 0x00000001, nv04_mmu_new }, 239 .pci = { 0x00000001, nv04_pci_new }, 240 .timer = { 0x00000001, nv04_timer_new }, 241 .disp = { 0x00000001, nv04_disp_new }, 242 .dma = { 0x00000001, nv04_dma_new }, 243 .fifo = { 0x00000001, nv10_fifo_new }, 244 .gr = { 0x00000001, nv15_gr_new }, 245 .sw = { 0x00000001, nv10_sw_new }, 246 }; 247 248 static const struct nvkm_device_chip 249 nv1f_chipset = { 250 .name = "nForce2", 251 .bios = { 0x00000001, nvkm_bios_new }, 252 .bus = { 0x00000001, nv04_bus_new }, 253 .clk = { 0x00000001, nv04_clk_new }, 254 .devinit = { 0x00000001, nv1a_devinit_new }, 255 .fb = { 0x00000001, nv1a_fb_new }, 256 .gpio = { 0x00000001, nv10_gpio_new }, 257 .i2c = { 0x00000001, nv04_i2c_new }, 258 .imem = { 0x00000001, nv04_instmem_new }, 259 .mc = { 0x00000001, nv17_mc_new }, 260 .mmu = { 0x00000001, nv04_mmu_new }, 261 .pci = { 0x00000001, nv04_pci_new }, 262 .timer = { 0x00000001, nv04_timer_new }, 263 .disp = { 0x00000001, nv04_disp_new }, 264 .dma = { 0x00000001, nv04_dma_new }, 265 .fifo = { 0x00000001, nv17_fifo_new }, 266 .gr = { 0x00000001, nv17_gr_new }, 267 .sw = { 0x00000001, nv10_sw_new }, 268 }; 269 270 static const struct nvkm_device_chip 271 nv20_chipset = { 272 .name = "NV20", 273 .bios = { 0x00000001, nvkm_bios_new }, 274 .bus = { 0x00000001, nv04_bus_new }, 275 .clk = { 0x00000001, nv04_clk_new }, 276 .devinit = { 0x00000001, nv20_devinit_new }, 277 .fb = { 0x00000001, nv20_fb_new }, 278 .gpio = { 0x00000001, nv10_gpio_new }, 279 .i2c = { 0x00000001, nv04_i2c_new }, 280 .imem = { 0x00000001, nv04_instmem_new }, 281 .mc = { 0x00000001, nv17_mc_new }, 282 .mmu = { 0x00000001, nv04_mmu_new }, 283 .pci = { 0x00000001, nv04_pci_new }, 284 .timer = { 0x00000001, nv04_timer_new }, 285 .disp = { 0x00000001, nv04_disp_new }, 286 .dma = { 0x00000001, nv04_dma_new }, 287 .fifo = { 0x00000001, nv17_fifo_new }, 288 .gr = { 0x00000001, nv20_gr_new }, 289 .sw = { 0x00000001, nv10_sw_new }, 290 }; 291 292 static const struct nvkm_device_chip 293 nv25_chipset = { 294 .name = "NV25", 295 .bios = { 0x00000001, nvkm_bios_new }, 296 .bus = { 0x00000001, nv04_bus_new }, 297 .clk = { 0x00000001, nv04_clk_new }, 298 .devinit = { 0x00000001, nv20_devinit_new }, 299 .fb = { 0x00000001, nv25_fb_new }, 300 .gpio = { 0x00000001, nv10_gpio_new }, 301 .i2c = { 0x00000001, nv04_i2c_new }, 302 .imem = { 0x00000001, nv04_instmem_new }, 303 .mc = { 0x00000001, nv17_mc_new }, 304 .mmu = { 0x00000001, nv04_mmu_new }, 305 .pci = { 0x00000001, nv04_pci_new }, 306 .timer = { 0x00000001, nv04_timer_new }, 307 .disp = { 0x00000001, nv04_disp_new }, 308 .dma = { 0x00000001, nv04_dma_new }, 309 .fifo = { 0x00000001, nv17_fifo_new }, 310 .gr = { 0x00000001, nv25_gr_new }, 311 .sw = { 0x00000001, nv10_sw_new }, 312 }; 313 314 static const struct nvkm_device_chip 315 nv28_chipset = { 316 .name = "NV28", 317 .bios = { 0x00000001, nvkm_bios_new }, 318 .bus = { 0x00000001, nv04_bus_new }, 319 .clk = { 0x00000001, nv04_clk_new }, 320 .devinit = { 0x00000001, nv20_devinit_new }, 321 .fb = { 0x00000001, nv25_fb_new }, 322 .gpio = { 0x00000001, nv10_gpio_new }, 323 .i2c = { 0x00000001, nv04_i2c_new }, 324 .imem = { 0x00000001, nv04_instmem_new }, 325 .mc = { 0x00000001, nv17_mc_new }, 326 .mmu = { 0x00000001, nv04_mmu_new }, 327 .pci = { 0x00000001, nv04_pci_new }, 328 .timer = { 0x00000001, nv04_timer_new }, 329 .disp = { 0x00000001, nv04_disp_new }, 330 .dma = { 0x00000001, nv04_dma_new }, 331 .fifo = { 0x00000001, nv17_fifo_new }, 332 .gr = { 0x00000001, nv25_gr_new }, 333 .sw = { 0x00000001, nv10_sw_new }, 334 }; 335 336 static const struct nvkm_device_chip 337 nv2a_chipset = { 338 .name = "NV2A", 339 .bios = { 0x00000001, nvkm_bios_new }, 340 .bus = { 0x00000001, nv04_bus_new }, 341 .clk = { 0x00000001, nv04_clk_new }, 342 .devinit = { 0x00000001, nv20_devinit_new }, 343 .fb = { 0x00000001, nv25_fb_new }, 344 .gpio = { 0x00000001, nv10_gpio_new }, 345 .i2c = { 0x00000001, nv04_i2c_new }, 346 .imem = { 0x00000001, nv04_instmem_new }, 347 .mc = { 0x00000001, nv17_mc_new }, 348 .mmu = { 0x00000001, nv04_mmu_new }, 349 .pci = { 0x00000001, nv04_pci_new }, 350 .timer = { 0x00000001, nv04_timer_new }, 351 .disp = { 0x00000001, nv04_disp_new }, 352 .dma = { 0x00000001, nv04_dma_new }, 353 .fifo = { 0x00000001, nv17_fifo_new }, 354 .gr = { 0x00000001, nv2a_gr_new }, 355 .sw = { 0x00000001, nv10_sw_new }, 356 }; 357 358 static const struct nvkm_device_chip 359 nv30_chipset = { 360 .name = "NV30", 361 .bios = { 0x00000001, nvkm_bios_new }, 362 .bus = { 0x00000001, nv04_bus_new }, 363 .clk = { 0x00000001, nv04_clk_new }, 364 .devinit = { 0x00000001, nv20_devinit_new }, 365 .fb = { 0x00000001, nv30_fb_new }, 366 .gpio = { 0x00000001, nv10_gpio_new }, 367 .i2c = { 0x00000001, nv04_i2c_new }, 368 .imem = { 0x00000001, nv04_instmem_new }, 369 .mc = { 0x00000001, nv17_mc_new }, 370 .mmu = { 0x00000001, nv04_mmu_new }, 371 .pci = { 0x00000001, nv04_pci_new }, 372 .timer = { 0x00000001, nv04_timer_new }, 373 .disp = { 0x00000001, nv04_disp_new }, 374 .dma = { 0x00000001, nv04_dma_new }, 375 .fifo = { 0x00000001, nv17_fifo_new }, 376 .gr = { 0x00000001, nv30_gr_new }, 377 .sw = { 0x00000001, nv10_sw_new }, 378 }; 379 380 static const struct nvkm_device_chip 381 nv31_chipset = { 382 .name = "NV31", 383 .bios = { 0x00000001, nvkm_bios_new }, 384 .bus = { 0x00000001, nv31_bus_new }, 385 .clk = { 0x00000001, nv04_clk_new }, 386 .devinit = { 0x00000001, nv20_devinit_new }, 387 .fb = { 0x00000001, nv30_fb_new }, 388 .gpio = { 0x00000001, nv10_gpio_new }, 389 .i2c = { 0x00000001, nv04_i2c_new }, 390 .imem = { 0x00000001, nv04_instmem_new }, 391 .mc = { 0x00000001, nv17_mc_new }, 392 .mmu = { 0x00000001, nv04_mmu_new }, 393 .pci = { 0x00000001, nv04_pci_new }, 394 .timer = { 0x00000001, nv04_timer_new }, 395 .disp = { 0x00000001, nv04_disp_new }, 396 .dma = { 0x00000001, nv04_dma_new }, 397 .fifo = { 0x00000001, nv17_fifo_new }, 398 .gr = { 0x00000001, nv30_gr_new }, 399 .mpeg = { 0x00000001, nv31_mpeg_new }, 400 .sw = { 0x00000001, nv10_sw_new }, 401 }; 402 403 static const struct nvkm_device_chip 404 nv34_chipset = { 405 .name = "NV34", 406 .bios = { 0x00000001, nvkm_bios_new }, 407 .bus = { 0x00000001, nv31_bus_new }, 408 .clk = { 0x00000001, nv04_clk_new }, 409 .devinit = { 0x00000001, nv10_devinit_new }, 410 .fb = { 0x00000001, nv10_fb_new }, 411 .gpio = { 0x00000001, nv10_gpio_new }, 412 .i2c = { 0x00000001, nv04_i2c_new }, 413 .imem = { 0x00000001, nv04_instmem_new }, 414 .mc = { 0x00000001, nv17_mc_new }, 415 .mmu = { 0x00000001, nv04_mmu_new }, 416 .pci = { 0x00000001, nv04_pci_new }, 417 .timer = { 0x00000001, nv04_timer_new }, 418 .disp = { 0x00000001, nv04_disp_new }, 419 .dma = { 0x00000001, nv04_dma_new }, 420 .fifo = { 0x00000001, nv17_fifo_new }, 421 .gr = { 0x00000001, nv34_gr_new }, 422 .mpeg = { 0x00000001, nv31_mpeg_new }, 423 .sw = { 0x00000001, nv10_sw_new }, 424 }; 425 426 static const struct nvkm_device_chip 427 nv35_chipset = { 428 .name = "NV35", 429 .bios = { 0x00000001, nvkm_bios_new }, 430 .bus = { 0x00000001, nv04_bus_new }, 431 .clk = { 0x00000001, nv04_clk_new }, 432 .devinit = { 0x00000001, nv20_devinit_new }, 433 .fb = { 0x00000001, nv35_fb_new }, 434 .gpio = { 0x00000001, nv10_gpio_new }, 435 .i2c = { 0x00000001, nv04_i2c_new }, 436 .imem = { 0x00000001, nv04_instmem_new }, 437 .mc = { 0x00000001, nv17_mc_new }, 438 .mmu = { 0x00000001, nv04_mmu_new }, 439 .pci = { 0x00000001, nv04_pci_new }, 440 .timer = { 0x00000001, nv04_timer_new }, 441 .disp = { 0x00000001, nv04_disp_new }, 442 .dma = { 0x00000001, nv04_dma_new }, 443 .fifo = { 0x00000001, nv17_fifo_new }, 444 .gr = { 0x00000001, nv35_gr_new }, 445 .sw = { 0x00000001, nv10_sw_new }, 446 }; 447 448 static const struct nvkm_device_chip 449 nv36_chipset = { 450 .name = "NV36", 451 .bios = { 0x00000001, nvkm_bios_new }, 452 .bus = { 0x00000001, nv31_bus_new }, 453 .clk = { 0x00000001, nv04_clk_new }, 454 .devinit = { 0x00000001, nv20_devinit_new }, 455 .fb = { 0x00000001, nv36_fb_new }, 456 .gpio = { 0x00000001, nv10_gpio_new }, 457 .i2c = { 0x00000001, nv04_i2c_new }, 458 .imem = { 0x00000001, nv04_instmem_new }, 459 .mc = { 0x00000001, nv17_mc_new }, 460 .mmu = { 0x00000001, nv04_mmu_new }, 461 .pci = { 0x00000001, nv04_pci_new }, 462 .timer = { 0x00000001, nv04_timer_new }, 463 .disp = { 0x00000001, nv04_disp_new }, 464 .dma = { 0x00000001, nv04_dma_new }, 465 .fifo = { 0x00000001, nv17_fifo_new }, 466 .gr = { 0x00000001, nv35_gr_new }, 467 .mpeg = { 0x00000001, nv31_mpeg_new }, 468 .sw = { 0x00000001, nv10_sw_new }, 469 }; 470 471 static const struct nvkm_device_chip 472 nv40_chipset = { 473 .name = "NV40", 474 .bios = { 0x00000001, nvkm_bios_new }, 475 .bus = { 0x00000001, nv31_bus_new }, 476 .clk = { 0x00000001, nv40_clk_new }, 477 .devinit = { 0x00000001, nv1a_devinit_new }, 478 .fb = { 0x00000001, nv40_fb_new }, 479 .gpio = { 0x00000001, nv10_gpio_new }, 480 .i2c = { 0x00000001, nv04_i2c_new }, 481 .imem = { 0x00000001, nv40_instmem_new }, 482 .mc = { 0x00000001, nv17_mc_new }, 483 .mmu = { 0x00000001, nv04_mmu_new }, 484 .pci = { 0x00000001, nv40_pci_new }, 485 .therm = { 0x00000001, nv40_therm_new }, 486 .timer = { 0x00000001, nv40_timer_new }, 487 .volt = { 0x00000001, nv40_volt_new }, 488 .disp = { 0x00000001, nv04_disp_new }, 489 .dma = { 0x00000001, nv04_dma_new }, 490 .fifo = { 0x00000001, nv40_fifo_new }, 491 .gr = { 0x00000001, nv40_gr_new }, 492 .mpeg = { 0x00000001, nv40_mpeg_new }, 493 .pm = { 0x00000001, nv40_pm_new }, 494 .sw = { 0x00000001, nv10_sw_new }, 495 }; 496 497 static const struct nvkm_device_chip 498 nv41_chipset = { 499 .name = "NV41", 500 .bios = { 0x00000001, nvkm_bios_new }, 501 .bus = { 0x00000001, nv31_bus_new }, 502 .clk = { 0x00000001, nv40_clk_new }, 503 .devinit = { 0x00000001, nv1a_devinit_new }, 504 .fb = { 0x00000001, nv41_fb_new }, 505 .gpio = { 0x00000001, nv10_gpio_new }, 506 .i2c = { 0x00000001, nv04_i2c_new }, 507 .imem = { 0x00000001, nv40_instmem_new }, 508 .mc = { 0x00000001, nv17_mc_new }, 509 .mmu = { 0x00000001, nv41_mmu_new }, 510 .pci = { 0x00000001, nv40_pci_new }, 511 .therm = { 0x00000001, nv40_therm_new }, 512 .timer = { 0x00000001, nv41_timer_new }, 513 .volt = { 0x00000001, nv40_volt_new }, 514 .disp = { 0x00000001, nv04_disp_new }, 515 .dma = { 0x00000001, nv04_dma_new }, 516 .fifo = { 0x00000001, nv40_fifo_new }, 517 .gr = { 0x00000001, nv40_gr_new }, 518 .mpeg = { 0x00000001, nv40_mpeg_new }, 519 .pm = { 0x00000001, nv40_pm_new }, 520 .sw = { 0x00000001, nv10_sw_new }, 521 }; 522 523 static const struct nvkm_device_chip 524 nv42_chipset = { 525 .name = "NV42", 526 .bios = { 0x00000001, nvkm_bios_new }, 527 .bus = { 0x00000001, nv31_bus_new }, 528 .clk = { 0x00000001, nv40_clk_new }, 529 .devinit = { 0x00000001, nv1a_devinit_new }, 530 .fb = { 0x00000001, nv41_fb_new }, 531 .gpio = { 0x00000001, nv10_gpio_new }, 532 .i2c = { 0x00000001, nv04_i2c_new }, 533 .imem = { 0x00000001, nv40_instmem_new }, 534 .mc = { 0x00000001, nv17_mc_new }, 535 .mmu = { 0x00000001, nv41_mmu_new }, 536 .pci = { 0x00000001, nv40_pci_new }, 537 .therm = { 0x00000001, nv40_therm_new }, 538 .timer = { 0x00000001, nv41_timer_new }, 539 .volt = { 0x00000001, nv40_volt_new }, 540 .disp = { 0x00000001, nv04_disp_new }, 541 .dma = { 0x00000001, nv04_dma_new }, 542 .fifo = { 0x00000001, nv40_fifo_new }, 543 .gr = { 0x00000001, nv40_gr_new }, 544 .mpeg = { 0x00000001, nv40_mpeg_new }, 545 .pm = { 0x00000001, nv40_pm_new }, 546 .sw = { 0x00000001, nv10_sw_new }, 547 }; 548 549 static const struct nvkm_device_chip 550 nv43_chipset = { 551 .name = "NV43", 552 .bios = { 0x00000001, nvkm_bios_new }, 553 .bus = { 0x00000001, nv31_bus_new }, 554 .clk = { 0x00000001, nv40_clk_new }, 555 .devinit = { 0x00000001, nv1a_devinit_new }, 556 .fb = { 0x00000001, nv41_fb_new }, 557 .gpio = { 0x00000001, nv10_gpio_new }, 558 .i2c = { 0x00000001, nv04_i2c_new }, 559 .imem = { 0x00000001, nv40_instmem_new }, 560 .mc = { 0x00000001, nv17_mc_new }, 561 .mmu = { 0x00000001, nv41_mmu_new }, 562 .pci = { 0x00000001, nv40_pci_new }, 563 .therm = { 0x00000001, nv40_therm_new }, 564 .timer = { 0x00000001, nv41_timer_new }, 565 .volt = { 0x00000001, nv40_volt_new }, 566 .disp = { 0x00000001, nv04_disp_new }, 567 .dma = { 0x00000001, nv04_dma_new }, 568 .fifo = { 0x00000001, nv40_fifo_new }, 569 .gr = { 0x00000001, nv40_gr_new }, 570 .mpeg = { 0x00000001, nv40_mpeg_new }, 571 .pm = { 0x00000001, nv40_pm_new }, 572 .sw = { 0x00000001, nv10_sw_new }, 573 }; 574 575 static const struct nvkm_device_chip 576 nv44_chipset = { 577 .name = "NV44", 578 .bios = { 0x00000001, nvkm_bios_new }, 579 .bus = { 0x00000001, nv31_bus_new }, 580 .clk = { 0x00000001, nv40_clk_new }, 581 .devinit = { 0x00000001, nv1a_devinit_new }, 582 .fb = { 0x00000001, nv44_fb_new }, 583 .gpio = { 0x00000001, nv10_gpio_new }, 584 .i2c = { 0x00000001, nv04_i2c_new }, 585 .imem = { 0x00000001, nv40_instmem_new }, 586 .mc = { 0x00000001, nv44_mc_new }, 587 .mmu = { 0x00000001, nv44_mmu_new }, 588 .pci = { 0x00000001, nv40_pci_new }, 589 .therm = { 0x00000001, nv40_therm_new }, 590 .timer = { 0x00000001, nv41_timer_new }, 591 .volt = { 0x00000001, nv40_volt_new }, 592 .disp = { 0x00000001, nv04_disp_new }, 593 .dma = { 0x00000001, nv04_dma_new }, 594 .fifo = { 0x00000001, nv40_fifo_new }, 595 .gr = { 0x00000001, nv44_gr_new }, 596 .mpeg = { 0x00000001, nv44_mpeg_new }, 597 .pm = { 0x00000001, nv40_pm_new }, 598 .sw = { 0x00000001, nv10_sw_new }, 599 }; 600 601 static const struct nvkm_device_chip 602 nv45_chipset = { 603 .name = "NV45", 604 .bios = { 0x00000001, nvkm_bios_new }, 605 .bus = { 0x00000001, nv31_bus_new }, 606 .clk = { 0x00000001, nv40_clk_new }, 607 .devinit = { 0x00000001, nv1a_devinit_new }, 608 .fb = { 0x00000001, nv40_fb_new }, 609 .gpio = { 0x00000001, nv10_gpio_new }, 610 .i2c = { 0x00000001, nv04_i2c_new }, 611 .imem = { 0x00000001, nv40_instmem_new }, 612 .mc = { 0x00000001, nv17_mc_new }, 613 .mmu = { 0x00000001, nv04_mmu_new }, 614 .pci = { 0x00000001, nv40_pci_new }, 615 .therm = { 0x00000001, nv40_therm_new }, 616 .timer = { 0x00000001, nv41_timer_new }, 617 .volt = { 0x00000001, nv40_volt_new }, 618 .disp = { 0x00000001, nv04_disp_new }, 619 .dma = { 0x00000001, nv04_dma_new }, 620 .fifo = { 0x00000001, nv40_fifo_new }, 621 .gr = { 0x00000001, nv40_gr_new }, 622 .mpeg = { 0x00000001, nv44_mpeg_new }, 623 .pm = { 0x00000001, nv40_pm_new }, 624 .sw = { 0x00000001, nv10_sw_new }, 625 }; 626 627 static const struct nvkm_device_chip 628 nv46_chipset = { 629 .name = "G72", 630 .bios = { 0x00000001, nvkm_bios_new }, 631 .bus = { 0x00000001, nv31_bus_new }, 632 .clk = { 0x00000001, nv40_clk_new }, 633 .devinit = { 0x00000001, nv1a_devinit_new }, 634 .fb = { 0x00000001, nv46_fb_new }, 635 .gpio = { 0x00000001, nv10_gpio_new }, 636 .i2c = { 0x00000001, nv04_i2c_new }, 637 .imem = { 0x00000001, nv40_instmem_new }, 638 .mc = { 0x00000001, nv44_mc_new }, 639 .mmu = { 0x00000001, nv44_mmu_new }, 640 .pci = { 0x00000001, nv46_pci_new }, 641 .therm = { 0x00000001, nv40_therm_new }, 642 .timer = { 0x00000001, nv41_timer_new }, 643 .volt = { 0x00000001, nv40_volt_new }, 644 .disp = { 0x00000001, nv04_disp_new }, 645 .dma = { 0x00000001, nv04_dma_new }, 646 .fifo = { 0x00000001, nv40_fifo_new }, 647 .gr = { 0x00000001, nv44_gr_new }, 648 .mpeg = { 0x00000001, nv44_mpeg_new }, 649 .pm = { 0x00000001, nv40_pm_new }, 650 .sw = { 0x00000001, nv10_sw_new }, 651 }; 652 653 static const struct nvkm_device_chip 654 nv47_chipset = { 655 .name = "G70", 656 .bios = { 0x00000001, nvkm_bios_new }, 657 .bus = { 0x00000001, nv31_bus_new }, 658 .clk = { 0x00000001, nv40_clk_new }, 659 .devinit = { 0x00000001, nv1a_devinit_new }, 660 .fb = { 0x00000001, nv47_fb_new }, 661 .gpio = { 0x00000001, nv10_gpio_new }, 662 .i2c = { 0x00000001, nv04_i2c_new }, 663 .imem = { 0x00000001, nv40_instmem_new }, 664 .mc = { 0x00000001, nv17_mc_new }, 665 .mmu = { 0x00000001, nv41_mmu_new }, 666 .pci = { 0x00000001, nv40_pci_new }, 667 .therm = { 0x00000001, nv40_therm_new }, 668 .timer = { 0x00000001, nv41_timer_new }, 669 .volt = { 0x00000001, nv40_volt_new }, 670 .disp = { 0x00000001, nv04_disp_new }, 671 .dma = { 0x00000001, nv04_dma_new }, 672 .fifo = { 0x00000001, nv40_fifo_new }, 673 .gr = { 0x00000001, nv40_gr_new }, 674 .mpeg = { 0x00000001, nv44_mpeg_new }, 675 .pm = { 0x00000001, nv40_pm_new }, 676 .sw = { 0x00000001, nv10_sw_new }, 677 }; 678 679 static const struct nvkm_device_chip 680 nv49_chipset = { 681 .name = "G71", 682 .bios = { 0x00000001, nvkm_bios_new }, 683 .bus = { 0x00000001, nv31_bus_new }, 684 .clk = { 0x00000001, nv40_clk_new }, 685 .devinit = { 0x00000001, nv1a_devinit_new }, 686 .fb = { 0x00000001, nv49_fb_new }, 687 .gpio = { 0x00000001, nv10_gpio_new }, 688 .i2c = { 0x00000001, nv04_i2c_new }, 689 .imem = { 0x00000001, nv40_instmem_new }, 690 .mc = { 0x00000001, nv17_mc_new }, 691 .mmu = { 0x00000001, nv41_mmu_new }, 692 .pci = { 0x00000001, nv40_pci_new }, 693 .therm = { 0x00000001, nv40_therm_new }, 694 .timer = { 0x00000001, nv41_timer_new }, 695 .volt = { 0x00000001, nv40_volt_new }, 696 .disp = { 0x00000001, nv04_disp_new }, 697 .dma = { 0x00000001, nv04_dma_new }, 698 .fifo = { 0x00000001, nv40_fifo_new }, 699 .gr = { 0x00000001, nv40_gr_new }, 700 .mpeg = { 0x00000001, nv44_mpeg_new }, 701 .pm = { 0x00000001, nv40_pm_new }, 702 .sw = { 0x00000001, nv10_sw_new }, 703 }; 704 705 static const struct nvkm_device_chip 706 nv4a_chipset = { 707 .name = "NV44A", 708 .bios = { 0x00000001, nvkm_bios_new }, 709 .bus = { 0x00000001, nv31_bus_new }, 710 .clk = { 0x00000001, nv40_clk_new }, 711 .devinit = { 0x00000001, nv1a_devinit_new }, 712 .fb = { 0x00000001, nv44_fb_new }, 713 .gpio = { 0x00000001, nv10_gpio_new }, 714 .i2c = { 0x00000001, nv04_i2c_new }, 715 .imem = { 0x00000001, nv40_instmem_new }, 716 .mc = { 0x00000001, nv44_mc_new }, 717 .mmu = { 0x00000001, nv04_mmu_new }, 718 .pci = { 0x00000001, nv40_pci_new }, 719 .therm = { 0x00000001, nv40_therm_new }, 720 .timer = { 0x00000001, nv41_timer_new }, 721 .volt = { 0x00000001, nv40_volt_new }, 722 .disp = { 0x00000001, nv04_disp_new }, 723 .dma = { 0x00000001, nv04_dma_new }, 724 .fifo = { 0x00000001, nv40_fifo_new }, 725 .gr = { 0x00000001, nv44_gr_new }, 726 .mpeg = { 0x00000001, nv44_mpeg_new }, 727 .pm = { 0x00000001, nv40_pm_new }, 728 .sw = { 0x00000001, nv10_sw_new }, 729 }; 730 731 static const struct nvkm_device_chip 732 nv4b_chipset = { 733 .name = "G73", 734 .bios = { 0x00000001, nvkm_bios_new }, 735 .bus = { 0x00000001, nv31_bus_new }, 736 .clk = { 0x00000001, nv40_clk_new }, 737 .devinit = { 0x00000001, nv1a_devinit_new }, 738 .fb = { 0x00000001, nv49_fb_new }, 739 .gpio = { 0x00000001, nv10_gpio_new }, 740 .i2c = { 0x00000001, nv04_i2c_new }, 741 .imem = { 0x00000001, nv40_instmem_new }, 742 .mc = { 0x00000001, nv17_mc_new }, 743 .mmu = { 0x00000001, nv41_mmu_new }, 744 .pci = { 0x00000001, nv40_pci_new }, 745 .therm = { 0x00000001, nv40_therm_new }, 746 .timer = { 0x00000001, nv41_timer_new }, 747 .volt = { 0x00000001, nv40_volt_new }, 748 .disp = { 0x00000001, nv04_disp_new }, 749 .dma = { 0x00000001, nv04_dma_new }, 750 .fifo = { 0x00000001, nv40_fifo_new }, 751 .gr = { 0x00000001, nv40_gr_new }, 752 .mpeg = { 0x00000001, nv44_mpeg_new }, 753 .pm = { 0x00000001, nv40_pm_new }, 754 .sw = { 0x00000001, nv10_sw_new }, 755 }; 756 757 static const struct nvkm_device_chip 758 nv4c_chipset = { 759 .name = "C61", 760 .bios = { 0x00000001, nvkm_bios_new }, 761 .bus = { 0x00000001, nv31_bus_new }, 762 .clk = { 0x00000001, nv40_clk_new }, 763 .devinit = { 0x00000001, nv1a_devinit_new }, 764 .fb = { 0x00000001, nv46_fb_new }, 765 .gpio = { 0x00000001, nv10_gpio_new }, 766 .i2c = { 0x00000001, nv04_i2c_new }, 767 .imem = { 0x00000001, nv40_instmem_new }, 768 .mc = { 0x00000001, nv44_mc_new }, 769 .mmu = { 0x00000001, nv44_mmu_new }, 770 .pci = { 0x00000001, nv4c_pci_new }, 771 .therm = { 0x00000001, nv40_therm_new }, 772 .timer = { 0x00000001, nv41_timer_new }, 773 .volt = { 0x00000001, nv40_volt_new }, 774 .disp = { 0x00000001, nv04_disp_new }, 775 .dma = { 0x00000001, nv04_dma_new }, 776 .fifo = { 0x00000001, nv40_fifo_new }, 777 .gr = { 0x00000001, nv44_gr_new }, 778 .mpeg = { 0x00000001, nv44_mpeg_new }, 779 .pm = { 0x00000001, nv40_pm_new }, 780 .sw = { 0x00000001, nv10_sw_new }, 781 }; 782 783 static const struct nvkm_device_chip 784 nv4e_chipset = { 785 .name = "C51", 786 .bios = { 0x00000001, nvkm_bios_new }, 787 .bus = { 0x00000001, nv31_bus_new }, 788 .clk = { 0x00000001, nv40_clk_new }, 789 .devinit = { 0x00000001, nv1a_devinit_new }, 790 .fb = { 0x00000001, nv4e_fb_new }, 791 .gpio = { 0x00000001, nv10_gpio_new }, 792 .i2c = { 0x00000001, nv4e_i2c_new }, 793 .imem = { 0x00000001, nv40_instmem_new }, 794 .mc = { 0x00000001, nv44_mc_new }, 795 .mmu = { 0x00000001, nv44_mmu_new }, 796 .pci = { 0x00000001, nv4c_pci_new }, 797 .therm = { 0x00000001, nv40_therm_new }, 798 .timer = { 0x00000001, nv41_timer_new }, 799 .volt = { 0x00000001, nv40_volt_new }, 800 .disp = { 0x00000001, nv04_disp_new }, 801 .dma = { 0x00000001, nv04_dma_new }, 802 .fifo = { 0x00000001, nv40_fifo_new }, 803 .gr = { 0x00000001, nv44_gr_new }, 804 .mpeg = { 0x00000001, nv44_mpeg_new }, 805 .pm = { 0x00000001, nv40_pm_new }, 806 .sw = { 0x00000001, nv10_sw_new }, 807 }; 808 809 static const struct nvkm_device_chip 810 nv50_chipset = { 811 .name = "G80", 812 .bar = { 0x00000001, nv50_bar_new }, 813 .bios = { 0x00000001, nvkm_bios_new }, 814 .bus = { 0x00000001, nv50_bus_new }, 815 .clk = { 0x00000001, nv50_clk_new }, 816 .devinit = { 0x00000001, nv50_devinit_new }, 817 .fb = { 0x00000001, nv50_fb_new }, 818 .fuse = { 0x00000001, nv50_fuse_new }, 819 .gpio = { 0x00000001, nv50_gpio_new }, 820 .i2c = { 0x00000001, nv50_i2c_new }, 821 .imem = { 0x00000001, nv50_instmem_new }, 822 .mc = { 0x00000001, nv50_mc_new }, 823 .mmu = { 0x00000001, nv50_mmu_new }, 824 .mxm = { 0x00000001, nv50_mxm_new }, 825 .pci = { 0x00000001, nv46_pci_new }, 826 .therm = { 0x00000001, nv50_therm_new }, 827 .timer = { 0x00000001, nv41_timer_new }, 828 .volt = { 0x00000001, nv40_volt_new }, 829 .disp = { 0x00000001, nv50_disp_new }, 830 .dma = { 0x00000001, nv50_dma_new }, 831 .fifo = { 0x00000001, nv50_fifo_new }, 832 .gr = { 0x00000001, nv50_gr_new }, 833 .mpeg = { 0x00000001, nv50_mpeg_new }, 834 .pm = { 0x00000001, nv50_pm_new }, 835 .sw = { 0x00000001, nv50_sw_new }, 836 }; 837 838 static const struct nvkm_device_chip 839 nv63_chipset = { 840 .name = "C73", 841 .bios = { 0x00000001, nvkm_bios_new }, 842 .bus = { 0x00000001, nv31_bus_new }, 843 .clk = { 0x00000001, nv40_clk_new }, 844 .devinit = { 0x00000001, nv1a_devinit_new }, 845 .fb = { 0x00000001, nv46_fb_new }, 846 .gpio = { 0x00000001, nv10_gpio_new }, 847 .i2c = { 0x00000001, nv04_i2c_new }, 848 .imem = { 0x00000001, nv40_instmem_new }, 849 .mc = { 0x00000001, nv44_mc_new }, 850 .mmu = { 0x00000001, nv44_mmu_new }, 851 .pci = { 0x00000001, nv4c_pci_new }, 852 .therm = { 0x00000001, nv40_therm_new }, 853 .timer = { 0x00000001, nv41_timer_new }, 854 .volt = { 0x00000001, nv40_volt_new }, 855 .disp = { 0x00000001, nv04_disp_new }, 856 .dma = { 0x00000001, nv04_dma_new }, 857 .fifo = { 0x00000001, nv40_fifo_new }, 858 .gr = { 0x00000001, nv44_gr_new }, 859 .mpeg = { 0x00000001, nv44_mpeg_new }, 860 .pm = { 0x00000001, nv40_pm_new }, 861 .sw = { 0x00000001, nv10_sw_new }, 862 }; 863 864 static const struct nvkm_device_chip 865 nv67_chipset = { 866 .name = "C67", 867 .bios = { 0x00000001, nvkm_bios_new }, 868 .bus = { 0x00000001, nv31_bus_new }, 869 .clk = { 0x00000001, nv40_clk_new }, 870 .devinit = { 0x00000001, nv1a_devinit_new }, 871 .fb = { 0x00000001, nv46_fb_new }, 872 .gpio = { 0x00000001, nv10_gpio_new }, 873 .i2c = { 0x00000001, nv04_i2c_new }, 874 .imem = { 0x00000001, nv40_instmem_new }, 875 .mc = { 0x00000001, nv44_mc_new }, 876 .mmu = { 0x00000001, nv44_mmu_new }, 877 .pci = { 0x00000001, nv4c_pci_new }, 878 .therm = { 0x00000001, nv40_therm_new }, 879 .timer = { 0x00000001, nv41_timer_new }, 880 .volt = { 0x00000001, nv40_volt_new }, 881 .disp = { 0x00000001, nv04_disp_new }, 882 .dma = { 0x00000001, nv04_dma_new }, 883 .fifo = { 0x00000001, nv40_fifo_new }, 884 .gr = { 0x00000001, nv44_gr_new }, 885 .mpeg = { 0x00000001, nv44_mpeg_new }, 886 .pm = { 0x00000001, nv40_pm_new }, 887 .sw = { 0x00000001, nv10_sw_new }, 888 }; 889 890 static const struct nvkm_device_chip 891 nv68_chipset = { 892 .name = "C68", 893 .bios = { 0x00000001, nvkm_bios_new }, 894 .bus = { 0x00000001, nv31_bus_new }, 895 .clk = { 0x00000001, nv40_clk_new }, 896 .devinit = { 0x00000001, nv1a_devinit_new }, 897 .fb = { 0x00000001, nv46_fb_new }, 898 .gpio = { 0x00000001, nv10_gpio_new }, 899 .i2c = { 0x00000001, nv04_i2c_new }, 900 .imem = { 0x00000001, nv40_instmem_new }, 901 .mc = { 0x00000001, nv44_mc_new }, 902 .mmu = { 0x00000001, nv44_mmu_new }, 903 .pci = { 0x00000001, nv4c_pci_new }, 904 .therm = { 0x00000001, nv40_therm_new }, 905 .timer = { 0x00000001, nv41_timer_new }, 906 .volt = { 0x00000001, nv40_volt_new }, 907 .disp = { 0x00000001, nv04_disp_new }, 908 .dma = { 0x00000001, nv04_dma_new }, 909 .fifo = { 0x00000001, nv40_fifo_new }, 910 .gr = { 0x00000001, nv44_gr_new }, 911 .mpeg = { 0x00000001, nv44_mpeg_new }, 912 .pm = { 0x00000001, nv40_pm_new }, 913 .sw = { 0x00000001, nv10_sw_new }, 914 }; 915 916 static const struct nvkm_device_chip 917 nv84_chipset = { 918 .name = "G84", 919 .bar = { 0x00000001, g84_bar_new }, 920 .bios = { 0x00000001, nvkm_bios_new }, 921 .bus = { 0x00000001, nv50_bus_new }, 922 .clk = { 0x00000001, g84_clk_new }, 923 .devinit = { 0x00000001, g84_devinit_new }, 924 .fb = { 0x00000001, g84_fb_new }, 925 .fuse = { 0x00000001, nv50_fuse_new }, 926 .gpio = { 0x00000001, nv50_gpio_new }, 927 .i2c = { 0x00000001, nv50_i2c_new }, 928 .imem = { 0x00000001, nv50_instmem_new }, 929 .mc = { 0x00000001, g84_mc_new }, 930 .mmu = { 0x00000001, g84_mmu_new }, 931 .mxm = { 0x00000001, nv50_mxm_new }, 932 .pci = { 0x00000001, g84_pci_new }, 933 .therm = { 0x00000001, g84_therm_new }, 934 .timer = { 0x00000001, nv41_timer_new }, 935 .volt = { 0x00000001, nv40_volt_new }, 936 .bsp = { 0x00000001, g84_bsp_new }, 937 .cipher = { 0x00000001, g84_cipher_new }, 938 .disp = { 0x00000001, g84_disp_new }, 939 .dma = { 0x00000001, nv50_dma_new }, 940 .fifo = { 0x00000001, g84_fifo_new }, 941 .gr = { 0x00000001, g84_gr_new }, 942 .mpeg = { 0x00000001, g84_mpeg_new }, 943 .pm = { 0x00000001, g84_pm_new }, 944 .sw = { 0x00000001, nv50_sw_new }, 945 .vp = { 0x00000001, g84_vp_new }, 946 }; 947 948 static const struct nvkm_device_chip 949 nv86_chipset = { 950 .name = "G86", 951 .bar = { 0x00000001, g84_bar_new }, 952 .bios = { 0x00000001, nvkm_bios_new }, 953 .bus = { 0x00000001, nv50_bus_new }, 954 .clk = { 0x00000001, g84_clk_new }, 955 .devinit = { 0x00000001, g84_devinit_new }, 956 .fb = { 0x00000001, g84_fb_new }, 957 .fuse = { 0x00000001, nv50_fuse_new }, 958 .gpio = { 0x00000001, nv50_gpio_new }, 959 .i2c = { 0x00000001, nv50_i2c_new }, 960 .imem = { 0x00000001, nv50_instmem_new }, 961 .mc = { 0x00000001, g84_mc_new }, 962 .mmu = { 0x00000001, g84_mmu_new }, 963 .mxm = { 0x00000001, nv50_mxm_new }, 964 .pci = { 0x00000001, g84_pci_new }, 965 .therm = { 0x00000001, g84_therm_new }, 966 .timer = { 0x00000001, nv41_timer_new }, 967 .volt = { 0x00000001, nv40_volt_new }, 968 .bsp = { 0x00000001, g84_bsp_new }, 969 .cipher = { 0x00000001, g84_cipher_new }, 970 .disp = { 0x00000001, g84_disp_new }, 971 .dma = { 0x00000001, nv50_dma_new }, 972 .fifo = { 0x00000001, g84_fifo_new }, 973 .gr = { 0x00000001, g84_gr_new }, 974 .mpeg = { 0x00000001, g84_mpeg_new }, 975 .pm = { 0x00000001, g84_pm_new }, 976 .sw = { 0x00000001, nv50_sw_new }, 977 .vp = { 0x00000001, g84_vp_new }, 978 }; 979 980 static const struct nvkm_device_chip 981 nv92_chipset = { 982 .name = "G92", 983 .bar = { 0x00000001, g84_bar_new }, 984 .bios = { 0x00000001, nvkm_bios_new }, 985 .bus = { 0x00000001, nv50_bus_new }, 986 .clk = { 0x00000001, g84_clk_new }, 987 .devinit = { 0x00000001, g84_devinit_new }, 988 .fb = { 0x00000001, g84_fb_new }, 989 .fuse = { 0x00000001, nv50_fuse_new }, 990 .gpio = { 0x00000001, nv50_gpio_new }, 991 .i2c = { 0x00000001, nv50_i2c_new }, 992 .imem = { 0x00000001, nv50_instmem_new }, 993 .mc = { 0x00000001, g84_mc_new }, 994 .mmu = { 0x00000001, g84_mmu_new }, 995 .mxm = { 0x00000001, nv50_mxm_new }, 996 .pci = { 0x00000001, g92_pci_new }, 997 .therm = { 0x00000001, g84_therm_new }, 998 .timer = { 0x00000001, nv41_timer_new }, 999 .volt = { 0x00000001, nv40_volt_new }, 1000 .bsp = { 0x00000001, g84_bsp_new }, 1001 .cipher = { 0x00000001, g84_cipher_new }, 1002 .disp = { 0x00000001, g84_disp_new }, 1003 .dma = { 0x00000001, nv50_dma_new }, 1004 .fifo = { 0x00000001, g84_fifo_new }, 1005 .gr = { 0x00000001, g84_gr_new }, 1006 .mpeg = { 0x00000001, g84_mpeg_new }, 1007 .pm = { 0x00000001, g84_pm_new }, 1008 .sw = { 0x00000001, nv50_sw_new }, 1009 .vp = { 0x00000001, g84_vp_new }, 1010 }; 1011 1012 static const struct nvkm_device_chip 1013 nv94_chipset = { 1014 .name = "G94", 1015 .bar = { 0x00000001, g84_bar_new }, 1016 .bios = { 0x00000001, nvkm_bios_new }, 1017 .bus = { 0x00000001, g94_bus_new }, 1018 .clk = { 0x00000001, g84_clk_new }, 1019 .devinit = { 0x00000001, g84_devinit_new }, 1020 .fb = { 0x00000001, g84_fb_new }, 1021 .fuse = { 0x00000001, nv50_fuse_new }, 1022 .gpio = { 0x00000001, g94_gpio_new }, 1023 .i2c = { 0x00000001, g94_i2c_new }, 1024 .imem = { 0x00000001, nv50_instmem_new }, 1025 .mc = { 0x00000001, g84_mc_new }, 1026 .mmu = { 0x00000001, g84_mmu_new }, 1027 .mxm = { 0x00000001, nv50_mxm_new }, 1028 .pci = { 0x00000001, g94_pci_new }, 1029 .therm = { 0x00000001, g84_therm_new }, 1030 .timer = { 0x00000001, nv41_timer_new }, 1031 .volt = { 0x00000001, nv40_volt_new }, 1032 .bsp = { 0x00000001, g84_bsp_new }, 1033 .cipher = { 0x00000001, g84_cipher_new }, 1034 .disp = { 0x00000001, g94_disp_new }, 1035 .dma = { 0x00000001, nv50_dma_new }, 1036 .fifo = { 0x00000001, g84_fifo_new }, 1037 .gr = { 0x00000001, g84_gr_new }, 1038 .mpeg = { 0x00000001, g84_mpeg_new }, 1039 .pm = { 0x00000001, g84_pm_new }, 1040 .sw = { 0x00000001, nv50_sw_new }, 1041 .vp = { 0x00000001, g84_vp_new }, 1042 }; 1043 1044 static const struct nvkm_device_chip 1045 nv96_chipset = { 1046 .name = "G96", 1047 .bar = { 0x00000001, g84_bar_new }, 1048 .bios = { 0x00000001, nvkm_bios_new }, 1049 .bus = { 0x00000001, g94_bus_new }, 1050 .clk = { 0x00000001, g84_clk_new }, 1051 .devinit = { 0x00000001, g84_devinit_new }, 1052 .fb = { 0x00000001, g84_fb_new }, 1053 .fuse = { 0x00000001, nv50_fuse_new }, 1054 .gpio = { 0x00000001, g94_gpio_new }, 1055 .i2c = { 0x00000001, g94_i2c_new }, 1056 .imem = { 0x00000001, nv50_instmem_new }, 1057 .mc = { 0x00000001, g84_mc_new }, 1058 .mmu = { 0x00000001, g84_mmu_new }, 1059 .mxm = { 0x00000001, nv50_mxm_new }, 1060 .pci = { 0x00000001, g94_pci_new }, 1061 .therm = { 0x00000001, g84_therm_new }, 1062 .timer = { 0x00000001, nv41_timer_new }, 1063 .volt = { 0x00000001, nv40_volt_new }, 1064 .bsp = { 0x00000001, g84_bsp_new }, 1065 .cipher = { 0x00000001, g84_cipher_new }, 1066 .disp = { 0x00000001, g94_disp_new }, 1067 .dma = { 0x00000001, nv50_dma_new }, 1068 .fifo = { 0x00000001, g84_fifo_new }, 1069 .gr = { 0x00000001, g84_gr_new }, 1070 .mpeg = { 0x00000001, g84_mpeg_new }, 1071 .pm = { 0x00000001, g84_pm_new }, 1072 .sw = { 0x00000001, nv50_sw_new }, 1073 .vp = { 0x00000001, g84_vp_new }, 1074 }; 1075 1076 static const struct nvkm_device_chip 1077 nv98_chipset = { 1078 .name = "G98", 1079 .bar = { 0x00000001, g84_bar_new }, 1080 .bios = { 0x00000001, nvkm_bios_new }, 1081 .bus = { 0x00000001, g94_bus_new }, 1082 .clk = { 0x00000001, g84_clk_new }, 1083 .devinit = { 0x00000001, g98_devinit_new }, 1084 .fb = { 0x00000001, g84_fb_new }, 1085 .fuse = { 0x00000001, nv50_fuse_new }, 1086 .gpio = { 0x00000001, g94_gpio_new }, 1087 .i2c = { 0x00000001, g94_i2c_new }, 1088 .imem = { 0x00000001, nv50_instmem_new }, 1089 .mc = { 0x00000001, g98_mc_new }, 1090 .mmu = { 0x00000001, g84_mmu_new }, 1091 .mxm = { 0x00000001, nv50_mxm_new }, 1092 .pci = { 0x00000001, g94_pci_new }, 1093 .therm = { 0x00000001, g84_therm_new }, 1094 .timer = { 0x00000001, nv41_timer_new }, 1095 .volt = { 0x00000001, nv40_volt_new }, 1096 .disp = { 0x00000001, g94_disp_new }, 1097 .dma = { 0x00000001, nv50_dma_new }, 1098 .fifo = { 0x00000001, g98_fifo_new }, 1099 .gr = { 0x00000001, g84_gr_new }, 1100 .mspdec = { 0x00000001, g98_mspdec_new }, 1101 .msppp = { 0x00000001, g98_msppp_new }, 1102 .msvld = { 0x00000001, g98_msvld_new }, 1103 .pm = { 0x00000001, g84_pm_new }, 1104 .sec = { 0x00000001, g98_sec_new }, 1105 .sw = { 0x00000001, nv50_sw_new }, 1106 }; 1107 1108 static const struct nvkm_device_chip 1109 nva0_chipset = { 1110 .name = "GT200", 1111 .bar = { 0x00000001, g84_bar_new }, 1112 .bios = { 0x00000001, nvkm_bios_new }, 1113 .bus = { 0x00000001, g94_bus_new }, 1114 .clk = { 0x00000001, g84_clk_new }, 1115 .devinit = { 0x00000001, g84_devinit_new }, 1116 .fb = { 0x00000001, g84_fb_new }, 1117 .fuse = { 0x00000001, nv50_fuse_new }, 1118 .gpio = { 0x00000001, g94_gpio_new }, 1119 .i2c = { 0x00000001, nv50_i2c_new }, 1120 .imem = { 0x00000001, nv50_instmem_new }, 1121 .mc = { 0x00000001, g84_mc_new }, 1122 .mmu = { 0x00000001, g84_mmu_new }, 1123 .mxm = { 0x00000001, nv50_mxm_new }, 1124 .pci = { 0x00000001, g94_pci_new }, 1125 .therm = { 0x00000001, g84_therm_new }, 1126 .timer = { 0x00000001, nv41_timer_new }, 1127 .volt = { 0x00000001, nv40_volt_new }, 1128 .bsp = { 0x00000001, g84_bsp_new }, 1129 .cipher = { 0x00000001, g84_cipher_new }, 1130 .disp = { 0x00000001, gt200_disp_new }, 1131 .dma = { 0x00000001, nv50_dma_new }, 1132 .fifo = { 0x00000001, g84_fifo_new }, 1133 .gr = { 0x00000001, gt200_gr_new }, 1134 .mpeg = { 0x00000001, g84_mpeg_new }, 1135 .pm = { 0x00000001, gt200_pm_new }, 1136 .sw = { 0x00000001, nv50_sw_new }, 1137 .vp = { 0x00000001, g84_vp_new }, 1138 }; 1139 1140 static const struct nvkm_device_chip 1141 nva3_chipset = { 1142 .name = "GT215", 1143 .bar = { 0x00000001, g84_bar_new }, 1144 .bios = { 0x00000001, nvkm_bios_new }, 1145 .bus = { 0x00000001, g94_bus_new }, 1146 .clk = { 0x00000001, gt215_clk_new }, 1147 .devinit = { 0x00000001, gt215_devinit_new }, 1148 .fb = { 0x00000001, gt215_fb_new }, 1149 .fuse = { 0x00000001, nv50_fuse_new }, 1150 .gpio = { 0x00000001, g94_gpio_new }, 1151 .i2c = { 0x00000001, g94_i2c_new }, 1152 .imem = { 0x00000001, nv50_instmem_new }, 1153 .mc = { 0x00000001, gt215_mc_new }, 1154 .mmu = { 0x00000001, g84_mmu_new }, 1155 .mxm = { 0x00000001, nv50_mxm_new }, 1156 .pci = { 0x00000001, g94_pci_new }, 1157 .pmu = { 0x00000001, gt215_pmu_new }, 1158 .therm = { 0x00000001, gt215_therm_new }, 1159 .timer = { 0x00000001, nv41_timer_new }, 1160 .volt = { 0x00000001, nv40_volt_new }, 1161 .ce = { 0x00000001, gt215_ce_new }, 1162 .disp = { 0x00000001, gt215_disp_new }, 1163 .dma = { 0x00000001, nv50_dma_new }, 1164 .fifo = { 0x00000001, g98_fifo_new }, 1165 .gr = { 0x00000001, gt215_gr_new }, 1166 .mpeg = { 0x00000001, g84_mpeg_new }, 1167 .mspdec = { 0x00000001, gt215_mspdec_new }, 1168 .msppp = { 0x00000001, gt215_msppp_new }, 1169 .msvld = { 0x00000001, gt215_msvld_new }, 1170 .pm = { 0x00000001, gt215_pm_new }, 1171 .sw = { 0x00000001, nv50_sw_new }, 1172 }; 1173 1174 static const struct nvkm_device_chip 1175 nva5_chipset = { 1176 .name = "GT216", 1177 .bar = { 0x00000001, g84_bar_new }, 1178 .bios = { 0x00000001, nvkm_bios_new }, 1179 .bus = { 0x00000001, g94_bus_new }, 1180 .clk = { 0x00000001, gt215_clk_new }, 1181 .devinit = { 0x00000001, gt215_devinit_new }, 1182 .fb = { 0x00000001, gt215_fb_new }, 1183 .fuse = { 0x00000001, nv50_fuse_new }, 1184 .gpio = { 0x00000001, g94_gpio_new }, 1185 .i2c = { 0x00000001, g94_i2c_new }, 1186 .imem = { 0x00000001, nv50_instmem_new }, 1187 .mc = { 0x00000001, gt215_mc_new }, 1188 .mmu = { 0x00000001, g84_mmu_new }, 1189 .mxm = { 0x00000001, nv50_mxm_new }, 1190 .pci = { 0x00000001, g94_pci_new }, 1191 .pmu = { 0x00000001, gt215_pmu_new }, 1192 .therm = { 0x00000001, gt215_therm_new }, 1193 .timer = { 0x00000001, nv41_timer_new }, 1194 .volt = { 0x00000001, nv40_volt_new }, 1195 .ce = { 0x00000001, gt215_ce_new }, 1196 .disp = { 0x00000001, gt215_disp_new }, 1197 .dma = { 0x00000001, nv50_dma_new }, 1198 .fifo = { 0x00000001, g98_fifo_new }, 1199 .gr = { 0x00000001, gt215_gr_new }, 1200 .mspdec = { 0x00000001, gt215_mspdec_new }, 1201 .msppp = { 0x00000001, gt215_msppp_new }, 1202 .msvld = { 0x00000001, gt215_msvld_new }, 1203 .pm = { 0x00000001, gt215_pm_new }, 1204 .sw = { 0x00000001, nv50_sw_new }, 1205 }; 1206 1207 static const struct nvkm_device_chip 1208 nva8_chipset = { 1209 .name = "GT218", 1210 .bar = { 0x00000001, g84_bar_new }, 1211 .bios = { 0x00000001, nvkm_bios_new }, 1212 .bus = { 0x00000001, g94_bus_new }, 1213 .clk = { 0x00000001, gt215_clk_new }, 1214 .devinit = { 0x00000001, gt215_devinit_new }, 1215 .fb = { 0x00000001, gt215_fb_new }, 1216 .fuse = { 0x00000001, nv50_fuse_new }, 1217 .gpio = { 0x00000001, g94_gpio_new }, 1218 .i2c = { 0x00000001, g94_i2c_new }, 1219 .imem = { 0x00000001, nv50_instmem_new }, 1220 .mc = { 0x00000001, gt215_mc_new }, 1221 .mmu = { 0x00000001, g84_mmu_new }, 1222 .mxm = { 0x00000001, nv50_mxm_new }, 1223 .pci = { 0x00000001, g94_pci_new }, 1224 .pmu = { 0x00000001, gt215_pmu_new }, 1225 .therm = { 0x00000001, gt215_therm_new }, 1226 .timer = { 0x00000001, nv41_timer_new }, 1227 .volt = { 0x00000001, nv40_volt_new }, 1228 .ce = { 0x00000001, gt215_ce_new }, 1229 .disp = { 0x00000001, gt215_disp_new }, 1230 .dma = { 0x00000001, nv50_dma_new }, 1231 .fifo = { 0x00000001, g98_fifo_new }, 1232 .gr = { 0x00000001, gt215_gr_new }, 1233 .mspdec = { 0x00000001, gt215_mspdec_new }, 1234 .msppp = { 0x00000001, gt215_msppp_new }, 1235 .msvld = { 0x00000001, gt215_msvld_new }, 1236 .pm = { 0x00000001, gt215_pm_new }, 1237 .sw = { 0x00000001, nv50_sw_new }, 1238 }; 1239 1240 static const struct nvkm_device_chip 1241 nvaa_chipset = { 1242 .name = "MCP77/MCP78", 1243 .bar = { 0x00000001, g84_bar_new }, 1244 .bios = { 0x00000001, nvkm_bios_new }, 1245 .bus = { 0x00000001, g94_bus_new }, 1246 .clk = { 0x00000001, mcp77_clk_new }, 1247 .devinit = { 0x00000001, g98_devinit_new }, 1248 .fb = { 0x00000001, mcp77_fb_new }, 1249 .fuse = { 0x00000001, nv50_fuse_new }, 1250 .gpio = { 0x00000001, g94_gpio_new }, 1251 .i2c = { 0x00000001, g94_i2c_new }, 1252 .imem = { 0x00000001, nv50_instmem_new }, 1253 .mc = { 0x00000001, g98_mc_new }, 1254 .mmu = { 0x00000001, mcp77_mmu_new }, 1255 .mxm = { 0x00000001, nv50_mxm_new }, 1256 .pci = { 0x00000001, g94_pci_new }, 1257 .therm = { 0x00000001, g84_therm_new }, 1258 .timer = { 0x00000001, nv41_timer_new }, 1259 .volt = { 0x00000001, nv40_volt_new }, 1260 .disp = { 0x00000001, mcp77_disp_new }, 1261 .dma = { 0x00000001, nv50_dma_new }, 1262 .fifo = { 0x00000001, g98_fifo_new }, 1263 .gr = { 0x00000001, gt200_gr_new }, 1264 .mspdec = { 0x00000001, g98_mspdec_new }, 1265 .msppp = { 0x00000001, g98_msppp_new }, 1266 .msvld = { 0x00000001, g98_msvld_new }, 1267 .pm = { 0x00000001, g84_pm_new }, 1268 .sec = { 0x00000001, g98_sec_new }, 1269 .sw = { 0x00000001, nv50_sw_new }, 1270 }; 1271 1272 static const struct nvkm_device_chip 1273 nvac_chipset = { 1274 .name = "MCP79/MCP7A", 1275 .bar = { 0x00000001, g84_bar_new }, 1276 .bios = { 0x00000001, nvkm_bios_new }, 1277 .bus = { 0x00000001, g94_bus_new }, 1278 .clk = { 0x00000001, mcp77_clk_new }, 1279 .devinit = { 0x00000001, g98_devinit_new }, 1280 .fb = { 0x00000001, mcp77_fb_new }, 1281 .fuse = { 0x00000001, nv50_fuse_new }, 1282 .gpio = { 0x00000001, g94_gpio_new }, 1283 .i2c = { 0x00000001, g94_i2c_new }, 1284 .imem = { 0x00000001, nv50_instmem_new }, 1285 .mc = { 0x00000001, g98_mc_new }, 1286 .mmu = { 0x00000001, mcp77_mmu_new }, 1287 .mxm = { 0x00000001, nv50_mxm_new }, 1288 .pci = { 0x00000001, g94_pci_new }, 1289 .therm = { 0x00000001, g84_therm_new }, 1290 .timer = { 0x00000001, nv41_timer_new }, 1291 .volt = { 0x00000001, nv40_volt_new }, 1292 .disp = { 0x00000001, mcp77_disp_new }, 1293 .dma = { 0x00000001, nv50_dma_new }, 1294 .fifo = { 0x00000001, g98_fifo_new }, 1295 .gr = { 0x00000001, mcp79_gr_new }, 1296 .mspdec = { 0x00000001, g98_mspdec_new }, 1297 .msppp = { 0x00000001, g98_msppp_new }, 1298 .msvld = { 0x00000001, g98_msvld_new }, 1299 .pm = { 0x00000001, g84_pm_new }, 1300 .sec = { 0x00000001, g98_sec_new }, 1301 .sw = { 0x00000001, nv50_sw_new }, 1302 }; 1303 1304 static const struct nvkm_device_chip 1305 nvaf_chipset = { 1306 .name = "MCP89", 1307 .bar = { 0x00000001, g84_bar_new }, 1308 .bios = { 0x00000001, nvkm_bios_new }, 1309 .bus = { 0x00000001, g94_bus_new }, 1310 .clk = { 0x00000001, gt215_clk_new }, 1311 .devinit = { 0x00000001, mcp89_devinit_new }, 1312 .fb = { 0x00000001, mcp89_fb_new }, 1313 .fuse = { 0x00000001, nv50_fuse_new }, 1314 .gpio = { 0x00000001, g94_gpio_new }, 1315 .i2c = { 0x00000001, g94_i2c_new }, 1316 .imem = { 0x00000001, nv50_instmem_new }, 1317 .mc = { 0x00000001, gt215_mc_new }, 1318 .mmu = { 0x00000001, mcp77_mmu_new }, 1319 .mxm = { 0x00000001, nv50_mxm_new }, 1320 .pci = { 0x00000001, g94_pci_new }, 1321 .pmu = { 0x00000001, gt215_pmu_new }, 1322 .therm = { 0x00000001, gt215_therm_new }, 1323 .timer = { 0x00000001, nv41_timer_new }, 1324 .volt = { 0x00000001, nv40_volt_new }, 1325 .ce = { 0x00000001, gt215_ce_new }, 1326 .disp = { 0x00000001, mcp89_disp_new }, 1327 .dma = { 0x00000001, nv50_dma_new }, 1328 .fifo = { 0x00000001, g98_fifo_new }, 1329 .gr = { 0x00000001, mcp89_gr_new }, 1330 .mspdec = { 0x00000001, gt215_mspdec_new }, 1331 .msppp = { 0x00000001, gt215_msppp_new }, 1332 .msvld = { 0x00000001, mcp89_msvld_new }, 1333 .pm = { 0x00000001, gt215_pm_new }, 1334 .sw = { 0x00000001, nv50_sw_new }, 1335 }; 1336 1337 static const struct nvkm_device_chip 1338 nvc0_chipset = { 1339 .name = "GF100", 1340 .bar = { 0x00000001, gf100_bar_new }, 1341 .bios = { 0x00000001, nvkm_bios_new }, 1342 .bus = { 0x00000001, gf100_bus_new }, 1343 .clk = { 0x00000001, gf100_clk_new }, 1344 .devinit = { 0x00000001, gf100_devinit_new }, 1345 .fb = { 0x00000001, gf100_fb_new }, 1346 .fuse = { 0x00000001, gf100_fuse_new }, 1347 .gpio = { 0x00000001, g94_gpio_new }, 1348 .i2c = { 0x00000001, g94_i2c_new }, 1349 .iccsense = { 0x00000001, gf100_iccsense_new }, 1350 .imem = { 0x00000001, nv50_instmem_new }, 1351 .ltc = { 0x00000001, gf100_ltc_new }, 1352 .mc = { 0x00000001, gf100_mc_new }, 1353 .mmu = { 0x00000001, gf100_mmu_new }, 1354 .mxm = { 0x00000001, nv50_mxm_new }, 1355 .pci = { 0x00000001, gf100_pci_new }, 1356 .pmu = { 0x00000001, gf100_pmu_new }, 1357 .privring = { 0x00000001, gf100_privring_new }, 1358 .therm = { 0x00000001, gt215_therm_new }, 1359 .timer = { 0x00000001, nv41_timer_new }, 1360 .volt = { 0x00000001, gf100_volt_new }, 1361 .ce = { 0x00000003, gf100_ce_new }, 1362 .disp = { 0x00000001, gt215_disp_new }, 1363 .dma = { 0x00000001, gf100_dma_new }, 1364 .fifo = { 0x00000001, gf100_fifo_new }, 1365 .gr = { 0x00000001, gf100_gr_new }, 1366 .mspdec = { 0x00000001, gf100_mspdec_new }, 1367 .msppp = { 0x00000001, gf100_msppp_new }, 1368 .msvld = { 0x00000001, gf100_msvld_new }, 1369 .pm = { 0x00000001, gf100_pm_new }, 1370 .sw = { 0x00000001, gf100_sw_new }, 1371 }; 1372 1373 static const struct nvkm_device_chip 1374 nvc1_chipset = { 1375 .name = "GF108", 1376 .bar = { 0x00000001, gf100_bar_new }, 1377 .bios = { 0x00000001, nvkm_bios_new }, 1378 .bus = { 0x00000001, gf100_bus_new }, 1379 .clk = { 0x00000001, gf100_clk_new }, 1380 .devinit = { 0x00000001, gf100_devinit_new }, 1381 .fb = { 0x00000001, gf108_fb_new }, 1382 .fuse = { 0x00000001, gf100_fuse_new }, 1383 .gpio = { 0x00000001, g94_gpio_new }, 1384 .i2c = { 0x00000001, g94_i2c_new }, 1385 .iccsense = { 0x00000001, gf100_iccsense_new }, 1386 .imem = { 0x00000001, nv50_instmem_new }, 1387 .ltc = { 0x00000001, gf100_ltc_new }, 1388 .mc = { 0x00000001, gf100_mc_new }, 1389 .mmu = { 0x00000001, gf100_mmu_new }, 1390 .mxm = { 0x00000001, nv50_mxm_new }, 1391 .pci = { 0x00000001, gf106_pci_new }, 1392 .pmu = { 0x00000001, gf100_pmu_new }, 1393 .privring = { 0x00000001, gf100_privring_new }, 1394 .therm = { 0x00000001, gt215_therm_new }, 1395 .timer = { 0x00000001, nv41_timer_new }, 1396 .volt = { 0x00000001, gf100_volt_new }, 1397 .ce = { 0x00000001, gf100_ce_new }, 1398 .disp = { 0x00000001, gt215_disp_new }, 1399 .dma = { 0x00000001, gf100_dma_new }, 1400 .fifo = { 0x00000001, gf100_fifo_new }, 1401 .gr = { 0x00000001, gf108_gr_new }, 1402 .mspdec = { 0x00000001, gf100_mspdec_new }, 1403 .msppp = { 0x00000001, gf100_msppp_new }, 1404 .msvld = { 0x00000001, gf100_msvld_new }, 1405 .pm = { 0x00000001, gf108_pm_new }, 1406 .sw = { 0x00000001, gf100_sw_new }, 1407 }; 1408 1409 static const struct nvkm_device_chip 1410 nvc3_chipset = { 1411 .name = "GF106", 1412 .bar = { 0x00000001, gf100_bar_new }, 1413 .bios = { 0x00000001, nvkm_bios_new }, 1414 .bus = { 0x00000001, gf100_bus_new }, 1415 .clk = { 0x00000001, gf100_clk_new }, 1416 .devinit = { 0x00000001, gf100_devinit_new }, 1417 .fb = { 0x00000001, gf100_fb_new }, 1418 .fuse = { 0x00000001, gf100_fuse_new }, 1419 .gpio = { 0x00000001, g94_gpio_new }, 1420 .i2c = { 0x00000001, g94_i2c_new }, 1421 .iccsense = { 0x00000001, gf100_iccsense_new }, 1422 .imem = { 0x00000001, nv50_instmem_new }, 1423 .ltc = { 0x00000001, gf100_ltc_new }, 1424 .mc = { 0x00000001, gf100_mc_new }, 1425 .mmu = { 0x00000001, gf100_mmu_new }, 1426 .mxm = { 0x00000001, nv50_mxm_new }, 1427 .pci = { 0x00000001, gf106_pci_new }, 1428 .pmu = { 0x00000001, gf100_pmu_new }, 1429 .privring = { 0x00000001, gf100_privring_new }, 1430 .therm = { 0x00000001, gt215_therm_new }, 1431 .timer = { 0x00000001, nv41_timer_new }, 1432 .volt = { 0x00000001, gf100_volt_new }, 1433 .ce = { 0x00000001, gf100_ce_new }, 1434 .disp = { 0x00000001, gt215_disp_new }, 1435 .dma = { 0x00000001, gf100_dma_new }, 1436 .fifo = { 0x00000001, gf100_fifo_new }, 1437 .gr = { 0x00000001, gf104_gr_new }, 1438 .mspdec = { 0x00000001, gf100_mspdec_new }, 1439 .msppp = { 0x00000001, gf100_msppp_new }, 1440 .msvld = { 0x00000001, gf100_msvld_new }, 1441 .pm = { 0x00000001, gf100_pm_new }, 1442 .sw = { 0x00000001, gf100_sw_new }, 1443 }; 1444 1445 static const struct nvkm_device_chip 1446 nvc4_chipset = { 1447 .name = "GF104", 1448 .bar = { 0x00000001, gf100_bar_new }, 1449 .bios = { 0x00000001, nvkm_bios_new }, 1450 .bus = { 0x00000001, gf100_bus_new }, 1451 .clk = { 0x00000001, gf100_clk_new }, 1452 .devinit = { 0x00000001, gf100_devinit_new }, 1453 .fb = { 0x00000001, gf100_fb_new }, 1454 .fuse = { 0x00000001, gf100_fuse_new }, 1455 .gpio = { 0x00000001, g94_gpio_new }, 1456 .i2c = { 0x00000001, g94_i2c_new }, 1457 .iccsense = { 0x00000001, gf100_iccsense_new }, 1458 .imem = { 0x00000001, nv50_instmem_new }, 1459 .ltc = { 0x00000001, gf100_ltc_new }, 1460 .mc = { 0x00000001, gf100_mc_new }, 1461 .mmu = { 0x00000001, gf100_mmu_new }, 1462 .mxm = { 0x00000001, nv50_mxm_new }, 1463 .pci = { 0x00000001, gf100_pci_new }, 1464 .pmu = { 0x00000001, gf100_pmu_new }, 1465 .privring = { 0x00000001, gf100_privring_new }, 1466 .therm = { 0x00000001, gt215_therm_new }, 1467 .timer = { 0x00000001, nv41_timer_new }, 1468 .volt = { 0x00000001, gf100_volt_new }, 1469 .ce = { 0x00000003, gf100_ce_new }, 1470 .disp = { 0x00000001, gt215_disp_new }, 1471 .dma = { 0x00000001, gf100_dma_new }, 1472 .fifo = { 0x00000001, gf100_fifo_new }, 1473 .gr = { 0x00000001, gf104_gr_new }, 1474 .mspdec = { 0x00000001, gf100_mspdec_new }, 1475 .msppp = { 0x00000001, gf100_msppp_new }, 1476 .msvld = { 0x00000001, gf100_msvld_new }, 1477 .pm = { 0x00000001, gf100_pm_new }, 1478 .sw = { 0x00000001, gf100_sw_new }, 1479 }; 1480 1481 static const struct nvkm_device_chip 1482 nvc8_chipset = { 1483 .name = "GF110", 1484 .bar = { 0x00000001, gf100_bar_new }, 1485 .bios = { 0x00000001, nvkm_bios_new }, 1486 .bus = { 0x00000001, gf100_bus_new }, 1487 .clk = { 0x00000001, gf100_clk_new }, 1488 .devinit = { 0x00000001, gf100_devinit_new }, 1489 .fb = { 0x00000001, gf100_fb_new }, 1490 .fuse = { 0x00000001, gf100_fuse_new }, 1491 .gpio = { 0x00000001, g94_gpio_new }, 1492 .i2c = { 0x00000001, g94_i2c_new }, 1493 .iccsense = { 0x00000001, gf100_iccsense_new }, 1494 .imem = { 0x00000001, nv50_instmem_new }, 1495 .ltc = { 0x00000001, gf100_ltc_new }, 1496 .mc = { 0x00000001, gf100_mc_new }, 1497 .mmu = { 0x00000001, gf100_mmu_new }, 1498 .mxm = { 0x00000001, nv50_mxm_new }, 1499 .pci = { 0x00000001, gf100_pci_new }, 1500 .pmu = { 0x00000001, gf100_pmu_new }, 1501 .privring = { 0x00000001, gf100_privring_new }, 1502 .therm = { 0x00000001, gt215_therm_new }, 1503 .timer = { 0x00000001, nv41_timer_new }, 1504 .volt = { 0x00000001, gf100_volt_new }, 1505 .ce = { 0x00000003, gf100_ce_new }, 1506 .disp = { 0x00000001, gt215_disp_new }, 1507 .dma = { 0x00000001, gf100_dma_new }, 1508 .fifo = { 0x00000001, gf100_fifo_new }, 1509 .gr = { 0x00000001, gf110_gr_new }, 1510 .mspdec = { 0x00000001, gf100_mspdec_new }, 1511 .msppp = { 0x00000001, gf100_msppp_new }, 1512 .msvld = { 0x00000001, gf100_msvld_new }, 1513 .pm = { 0x00000001, gf100_pm_new }, 1514 .sw = { 0x00000001, gf100_sw_new }, 1515 }; 1516 1517 static const struct nvkm_device_chip 1518 nvce_chipset = { 1519 .name = "GF114", 1520 .bar = { 0x00000001, gf100_bar_new }, 1521 .bios = { 0x00000001, nvkm_bios_new }, 1522 .bus = { 0x00000001, gf100_bus_new }, 1523 .clk = { 0x00000001, gf100_clk_new }, 1524 .devinit = { 0x00000001, gf100_devinit_new }, 1525 .fb = { 0x00000001, gf100_fb_new }, 1526 .fuse = { 0x00000001, gf100_fuse_new }, 1527 .gpio = { 0x00000001, g94_gpio_new }, 1528 .i2c = { 0x00000001, g94_i2c_new }, 1529 .iccsense = { 0x00000001, gf100_iccsense_new }, 1530 .imem = { 0x00000001, nv50_instmem_new }, 1531 .ltc = { 0x00000001, gf100_ltc_new }, 1532 .mc = { 0x00000001, gf100_mc_new }, 1533 .mmu = { 0x00000001, gf100_mmu_new }, 1534 .mxm = { 0x00000001, nv50_mxm_new }, 1535 .pci = { 0x00000001, gf100_pci_new }, 1536 .pmu = { 0x00000001, gf100_pmu_new }, 1537 .privring = { 0x00000001, gf100_privring_new }, 1538 .therm = { 0x00000001, gt215_therm_new }, 1539 .timer = { 0x00000001, nv41_timer_new }, 1540 .volt = { 0x00000001, gf100_volt_new }, 1541 .ce = { 0x00000003, gf100_ce_new }, 1542 .disp = { 0x00000001, gt215_disp_new }, 1543 .dma = { 0x00000001, gf100_dma_new }, 1544 .fifo = { 0x00000001, gf100_fifo_new }, 1545 .gr = { 0x00000001, gf104_gr_new }, 1546 .mspdec = { 0x00000001, gf100_mspdec_new }, 1547 .msppp = { 0x00000001, gf100_msppp_new }, 1548 .msvld = { 0x00000001, gf100_msvld_new }, 1549 .pm = { 0x00000001, gf100_pm_new }, 1550 .sw = { 0x00000001, gf100_sw_new }, 1551 }; 1552 1553 static const struct nvkm_device_chip 1554 nvcf_chipset = { 1555 .name = "GF116", 1556 .bar = { 0x00000001, gf100_bar_new }, 1557 .bios = { 0x00000001, nvkm_bios_new }, 1558 .bus = { 0x00000001, gf100_bus_new }, 1559 .clk = { 0x00000001, gf100_clk_new }, 1560 .devinit = { 0x00000001, gf100_devinit_new }, 1561 .fb = { 0x00000001, gf100_fb_new }, 1562 .fuse = { 0x00000001, gf100_fuse_new }, 1563 .gpio = { 0x00000001, g94_gpio_new }, 1564 .i2c = { 0x00000001, g94_i2c_new }, 1565 .iccsense = { 0x00000001, gf100_iccsense_new }, 1566 .imem = { 0x00000001, nv50_instmem_new }, 1567 .ltc = { 0x00000001, gf100_ltc_new }, 1568 .mc = { 0x00000001, gf100_mc_new }, 1569 .mmu = { 0x00000001, gf100_mmu_new }, 1570 .mxm = { 0x00000001, nv50_mxm_new }, 1571 .pci = { 0x00000001, gf106_pci_new }, 1572 .pmu = { 0x00000001, gf100_pmu_new }, 1573 .privring = { 0x00000001, gf100_privring_new }, 1574 .therm = { 0x00000001, gt215_therm_new }, 1575 .timer = { 0x00000001, nv41_timer_new }, 1576 .volt = { 0x00000001, gf100_volt_new }, 1577 .ce = { 0x00000001, gf100_ce_new }, 1578 .disp = { 0x00000001, gt215_disp_new }, 1579 .dma = { 0x00000001, gf100_dma_new }, 1580 .fifo = { 0x00000001, gf100_fifo_new }, 1581 .gr = { 0x00000001, gf104_gr_new }, 1582 .mspdec = { 0x00000001, gf100_mspdec_new }, 1583 .msppp = { 0x00000001, gf100_msppp_new }, 1584 .msvld = { 0x00000001, gf100_msvld_new }, 1585 .pm = { 0x00000001, gf100_pm_new }, 1586 .sw = { 0x00000001, gf100_sw_new }, 1587 }; 1588 1589 static const struct nvkm_device_chip 1590 nvd7_chipset = { 1591 .name = "GF117", 1592 .bar = { 0x00000001, gf100_bar_new }, 1593 .bios = { 0x00000001, nvkm_bios_new }, 1594 .bus = { 0x00000001, gf100_bus_new }, 1595 .clk = { 0x00000001, gf100_clk_new }, 1596 .devinit = { 0x00000001, gf100_devinit_new }, 1597 .fb = { 0x00000001, gf100_fb_new }, 1598 .fuse = { 0x00000001, gf100_fuse_new }, 1599 .gpio = { 0x00000001, gf119_gpio_new }, 1600 .i2c = { 0x00000001, gf117_i2c_new }, 1601 .iccsense = { 0x00000001, gf100_iccsense_new }, 1602 .imem = { 0x00000001, nv50_instmem_new }, 1603 .ltc = { 0x00000001, gf100_ltc_new }, 1604 .mc = { 0x00000001, gf100_mc_new }, 1605 .mmu = { 0x00000001, gf100_mmu_new }, 1606 .mxm = { 0x00000001, nv50_mxm_new }, 1607 .pci = { 0x00000001, gf106_pci_new }, 1608 .privring = { 0x00000001, gf117_privring_new }, 1609 .therm = { 0x00000001, gf119_therm_new }, 1610 .timer = { 0x00000001, nv41_timer_new }, 1611 .volt = { 0x00000001, gf117_volt_new }, 1612 .ce = { 0x00000001, gf100_ce_new }, 1613 .disp = { 0x00000001, gf119_disp_new }, 1614 .dma = { 0x00000001, gf119_dma_new }, 1615 .fifo = { 0x00000001, gf100_fifo_new }, 1616 .gr = { 0x00000001, gf117_gr_new }, 1617 .mspdec = { 0x00000001, gf100_mspdec_new }, 1618 .msppp = { 0x00000001, gf100_msppp_new }, 1619 .msvld = { 0x00000001, gf100_msvld_new }, 1620 .pm = { 0x00000001, gf117_pm_new }, 1621 .sw = { 0x00000001, gf100_sw_new }, 1622 }; 1623 1624 static const struct nvkm_device_chip 1625 nvd9_chipset = { 1626 .name = "GF119", 1627 .bar = { 0x00000001, gf100_bar_new }, 1628 .bios = { 0x00000001, nvkm_bios_new }, 1629 .bus = { 0x00000001, gf100_bus_new }, 1630 .clk = { 0x00000001, gf100_clk_new }, 1631 .devinit = { 0x00000001, gf100_devinit_new }, 1632 .fb = { 0x00000001, gf100_fb_new }, 1633 .fuse = { 0x00000001, gf100_fuse_new }, 1634 .gpio = { 0x00000001, gf119_gpio_new }, 1635 .i2c = { 0x00000001, gf119_i2c_new }, 1636 .iccsense = { 0x00000001, gf100_iccsense_new }, 1637 .imem = { 0x00000001, nv50_instmem_new }, 1638 .ltc = { 0x00000001, gf100_ltc_new }, 1639 .mc = { 0x00000001, gf100_mc_new }, 1640 .mmu = { 0x00000001, gf100_mmu_new }, 1641 .mxm = { 0x00000001, nv50_mxm_new }, 1642 .pci = { 0x00000001, gf106_pci_new }, 1643 .pmu = { 0x00000001, gf119_pmu_new }, 1644 .privring = { 0x00000001, gf117_privring_new }, 1645 .therm = { 0x00000001, gf119_therm_new }, 1646 .timer = { 0x00000001, nv41_timer_new }, 1647 .volt = { 0x00000001, gf100_volt_new }, 1648 .ce = { 0x00000001, gf100_ce_new }, 1649 .disp = { 0x00000001, gf119_disp_new }, 1650 .dma = { 0x00000001, gf119_dma_new }, 1651 .fifo = { 0x00000001, gf100_fifo_new }, 1652 .gr = { 0x00000001, gf119_gr_new }, 1653 .mspdec = { 0x00000001, gf100_mspdec_new }, 1654 .msppp = { 0x00000001, gf100_msppp_new }, 1655 .msvld = { 0x00000001, gf100_msvld_new }, 1656 .pm = { 0x00000001, gf117_pm_new }, 1657 .sw = { 0x00000001, gf100_sw_new }, 1658 }; 1659 1660 static const struct nvkm_device_chip 1661 nve4_chipset = { 1662 .name = "GK104", 1663 .bar = { 0x00000001, gf100_bar_new }, 1664 .bios = { 0x00000001, nvkm_bios_new }, 1665 .bus = { 0x00000001, gf100_bus_new }, 1666 .clk = { 0x00000001, gk104_clk_new }, 1667 .devinit = { 0x00000001, gf100_devinit_new }, 1668 .fb = { 0x00000001, gk104_fb_new }, 1669 .fuse = { 0x00000001, gf100_fuse_new }, 1670 .gpio = { 0x00000001, gk104_gpio_new }, 1671 .i2c = { 0x00000001, gk104_i2c_new }, 1672 .iccsense = { 0x00000001, gf100_iccsense_new }, 1673 .imem = { 0x00000001, nv50_instmem_new }, 1674 .ltc = { 0x00000001, gk104_ltc_new }, 1675 .mc = { 0x00000001, gk104_mc_new }, 1676 .mmu = { 0x00000001, gk104_mmu_new }, 1677 .mxm = { 0x00000001, nv50_mxm_new }, 1678 .pci = { 0x00000001, gk104_pci_new }, 1679 .pmu = { 0x00000001, gk104_pmu_new }, 1680 .privring = { 0x00000001, gk104_privring_new }, 1681 .therm = { 0x00000001, gk104_therm_new }, 1682 .timer = { 0x00000001, nv41_timer_new }, 1683 .top = { 0x00000001, gk104_top_new }, 1684 .volt = { 0x00000001, gk104_volt_new }, 1685 .ce = { 0x00000007, gk104_ce_new }, 1686 .disp = { 0x00000001, gk104_disp_new }, 1687 .dma = { 0x00000001, gf119_dma_new }, 1688 .fifo = { 0x00000001, gk104_fifo_new }, 1689 .gr = { 0x00000001, gk104_gr_new }, 1690 .mspdec = { 0x00000001, gk104_mspdec_new }, 1691 .msppp = { 0x00000001, gf100_msppp_new }, 1692 .msvld = { 0x00000001, gk104_msvld_new }, 1693 .pm = { 0x00000001, gk104_pm_new }, 1694 .sw = { 0x00000001, gf100_sw_new }, 1695 }; 1696 1697 static const struct nvkm_device_chip 1698 nve6_chipset = { 1699 .name = "GK106", 1700 .bar = { 0x00000001, gf100_bar_new }, 1701 .bios = { 0x00000001, nvkm_bios_new }, 1702 .bus = { 0x00000001, gf100_bus_new }, 1703 .clk = { 0x00000001, gk104_clk_new }, 1704 .devinit = { 0x00000001, gf100_devinit_new }, 1705 .fb = { 0x00000001, gk104_fb_new }, 1706 .fuse = { 0x00000001, gf100_fuse_new }, 1707 .gpio = { 0x00000001, gk104_gpio_new }, 1708 .i2c = { 0x00000001, gk104_i2c_new }, 1709 .iccsense = { 0x00000001, gf100_iccsense_new }, 1710 .imem = { 0x00000001, nv50_instmem_new }, 1711 .ltc = { 0x00000001, gk104_ltc_new }, 1712 .mc = { 0x00000001, gk104_mc_new }, 1713 .mmu = { 0x00000001, gk104_mmu_new }, 1714 .mxm = { 0x00000001, nv50_mxm_new }, 1715 .pci = { 0x00000001, gk104_pci_new }, 1716 .pmu = { 0x00000001, gk104_pmu_new }, 1717 .privring = { 0x00000001, gk104_privring_new }, 1718 .therm = { 0x00000001, gk104_therm_new }, 1719 .timer = { 0x00000001, nv41_timer_new }, 1720 .top = { 0x00000001, gk104_top_new }, 1721 .volt = { 0x00000001, gk104_volt_new }, 1722 .ce = { 0x00000007, gk104_ce_new }, 1723 .disp = { 0x00000001, gk104_disp_new }, 1724 .dma = { 0x00000001, gf119_dma_new }, 1725 .fifo = { 0x00000001, gk104_fifo_new }, 1726 .gr = { 0x00000001, gk104_gr_new }, 1727 .mspdec = { 0x00000001, gk104_mspdec_new }, 1728 .msppp = { 0x00000001, gf100_msppp_new }, 1729 .msvld = { 0x00000001, gk104_msvld_new }, 1730 .pm = { 0x00000001, gk104_pm_new }, 1731 .sw = { 0x00000001, gf100_sw_new }, 1732 }; 1733 1734 static const struct nvkm_device_chip 1735 nve7_chipset = { 1736 .name = "GK107", 1737 .bar = { 0x00000001, gf100_bar_new }, 1738 .bios = { 0x00000001, nvkm_bios_new }, 1739 .bus = { 0x00000001, gf100_bus_new }, 1740 .clk = { 0x00000001, gk104_clk_new }, 1741 .devinit = { 0x00000001, gf100_devinit_new }, 1742 .fb = { 0x00000001, gk104_fb_new }, 1743 .fuse = { 0x00000001, gf100_fuse_new }, 1744 .gpio = { 0x00000001, gk104_gpio_new }, 1745 .i2c = { 0x00000001, gk104_i2c_new }, 1746 .iccsense = { 0x00000001, gf100_iccsense_new }, 1747 .imem = { 0x00000001, nv50_instmem_new }, 1748 .ltc = { 0x00000001, gk104_ltc_new }, 1749 .mc = { 0x00000001, gk104_mc_new }, 1750 .mmu = { 0x00000001, gk104_mmu_new }, 1751 .mxm = { 0x00000001, nv50_mxm_new }, 1752 .pci = { 0x00000001, gk104_pci_new }, 1753 .pmu = { 0x00000001, gk104_pmu_new }, 1754 .privring = { 0x00000001, gk104_privring_new }, 1755 .therm = { 0x00000001, gk104_therm_new }, 1756 .timer = { 0x00000001, nv41_timer_new }, 1757 .top = { 0x00000001, gk104_top_new }, 1758 .volt = { 0x00000001, gk104_volt_new }, 1759 .ce = { 0x00000007, gk104_ce_new }, 1760 .disp = { 0x00000001, gk104_disp_new }, 1761 .dma = { 0x00000001, gf119_dma_new }, 1762 .fifo = { 0x00000001, gk104_fifo_new }, 1763 .gr = { 0x00000001, gk104_gr_new }, 1764 .mspdec = { 0x00000001, gk104_mspdec_new }, 1765 .msppp = { 0x00000001, gf100_msppp_new }, 1766 .msvld = { 0x00000001, gk104_msvld_new }, 1767 .pm = { 0x00000001, gk104_pm_new }, 1768 .sw = { 0x00000001, gf100_sw_new }, 1769 }; 1770 1771 static const struct nvkm_device_chip 1772 nvea_chipset = { 1773 .name = "GK20A", 1774 .bar = { 0x00000001, gk20a_bar_new }, 1775 .bus = { 0x00000001, gf100_bus_new }, 1776 .clk = { 0x00000001, gk20a_clk_new }, 1777 .fb = { 0x00000001, gk20a_fb_new }, 1778 .fuse = { 0x00000001, gf100_fuse_new }, 1779 .imem = { 0x00000001, gk20a_instmem_new }, 1780 .ltc = { 0x00000001, gk104_ltc_new }, 1781 .mc = { 0x00000001, gk20a_mc_new }, 1782 .mmu = { 0x00000001, gk20a_mmu_new }, 1783 .pmu = { 0x00000001, gk20a_pmu_new }, 1784 .privring = { 0x00000001, gk20a_privring_new }, 1785 .timer = { 0x00000001, gk20a_timer_new }, 1786 .top = { 0x00000001, gk104_top_new }, 1787 .volt = { 0x00000001, gk20a_volt_new }, 1788 .ce = { 0x00000004, gk104_ce_new }, 1789 .dma = { 0x00000001, gf119_dma_new }, 1790 .fifo = { 0x00000001, gk20a_fifo_new }, 1791 .gr = { 0x00000001, gk20a_gr_new }, 1792 .pm = { 0x00000001, gk104_pm_new }, 1793 .sw = { 0x00000001, gf100_sw_new }, 1794 }; 1795 1796 static const struct nvkm_device_chip 1797 nvf0_chipset = { 1798 .name = "GK110", 1799 .bar = { 0x00000001, gf100_bar_new }, 1800 .bios = { 0x00000001, nvkm_bios_new }, 1801 .bus = { 0x00000001, gf100_bus_new }, 1802 .clk = { 0x00000001, gk104_clk_new }, 1803 .devinit = { 0x00000001, gf100_devinit_new }, 1804 .fb = { 0x00000001, gk110_fb_new }, 1805 .fuse = { 0x00000001, gf100_fuse_new }, 1806 .gpio = { 0x00000001, gk104_gpio_new }, 1807 .i2c = { 0x00000001, gk110_i2c_new }, 1808 .iccsense = { 0x00000001, gf100_iccsense_new }, 1809 .imem = { 0x00000001, nv50_instmem_new }, 1810 .ltc = { 0x00000001, gk104_ltc_new }, 1811 .mc = { 0x00000001, gk104_mc_new }, 1812 .mmu = { 0x00000001, gk104_mmu_new }, 1813 .mxm = { 0x00000001, nv50_mxm_new }, 1814 .pci = { 0x00000001, gk104_pci_new }, 1815 .pmu = { 0x00000001, gk110_pmu_new }, 1816 .privring = { 0x00000001, gk104_privring_new }, 1817 .therm = { 0x00000001, gk104_therm_new }, 1818 .timer = { 0x00000001, nv41_timer_new }, 1819 .top = { 0x00000001, gk104_top_new }, 1820 .volt = { 0x00000001, gk104_volt_new }, 1821 .ce = { 0x00000007, gk104_ce_new }, 1822 .disp = { 0x00000001, gk110_disp_new }, 1823 .dma = { 0x00000001, gf119_dma_new }, 1824 .fifo = { 0x00000001, gk110_fifo_new }, 1825 .gr = { 0x00000001, gk110_gr_new }, 1826 .mspdec = { 0x00000001, gk104_mspdec_new }, 1827 .msppp = { 0x00000001, gf100_msppp_new }, 1828 .msvld = { 0x00000001, gk104_msvld_new }, 1829 .sw = { 0x00000001, gf100_sw_new }, 1830 }; 1831 1832 static const struct nvkm_device_chip 1833 nvf1_chipset = { 1834 .name = "GK110B", 1835 .bar = { 0x00000001, gf100_bar_new }, 1836 .bios = { 0x00000001, nvkm_bios_new }, 1837 .bus = { 0x00000001, gf100_bus_new }, 1838 .clk = { 0x00000001, gk104_clk_new }, 1839 .devinit = { 0x00000001, gf100_devinit_new }, 1840 .fb = { 0x00000001, gk110_fb_new }, 1841 .fuse = { 0x00000001, gf100_fuse_new }, 1842 .gpio = { 0x00000001, gk104_gpio_new }, 1843 .i2c = { 0x00000001, gk110_i2c_new }, 1844 .iccsense = { 0x00000001, gf100_iccsense_new }, 1845 .imem = { 0x00000001, nv50_instmem_new }, 1846 .ltc = { 0x00000001, gk104_ltc_new }, 1847 .mc = { 0x00000001, gk104_mc_new }, 1848 .mmu = { 0x00000001, gk104_mmu_new }, 1849 .mxm = { 0x00000001, nv50_mxm_new }, 1850 .pci = { 0x00000001, gk104_pci_new }, 1851 .pmu = { 0x00000001, gk110_pmu_new }, 1852 .privring = { 0x00000001, gk104_privring_new }, 1853 .therm = { 0x00000001, gk104_therm_new }, 1854 .timer = { 0x00000001, nv41_timer_new }, 1855 .top = { 0x00000001, gk104_top_new }, 1856 .volt = { 0x00000001, gk104_volt_new }, 1857 .ce = { 0x00000007, gk104_ce_new }, 1858 .disp = { 0x00000001, gk110_disp_new }, 1859 .dma = { 0x00000001, gf119_dma_new }, 1860 .fifo = { 0x00000001, gk110_fifo_new }, 1861 .gr = { 0x00000001, gk110b_gr_new }, 1862 .mspdec = { 0x00000001, gk104_mspdec_new }, 1863 .msppp = { 0x00000001, gf100_msppp_new }, 1864 .msvld = { 0x00000001, gk104_msvld_new }, 1865 .sw = { 0x00000001, gf100_sw_new }, 1866 }; 1867 1868 static const struct nvkm_device_chip 1869 nv106_chipset = { 1870 .name = "GK208B", 1871 .bar = { 0x00000001, gf100_bar_new }, 1872 .bios = { 0x00000001, nvkm_bios_new }, 1873 .bus = { 0x00000001, gf100_bus_new }, 1874 .clk = { 0x00000001, gk104_clk_new }, 1875 .devinit = { 0x00000001, gf100_devinit_new }, 1876 .fb = { 0x00000001, gk110_fb_new }, 1877 .fuse = { 0x00000001, gf100_fuse_new }, 1878 .gpio = { 0x00000001, gk104_gpio_new }, 1879 .i2c = { 0x00000001, gk110_i2c_new }, 1880 .iccsense = { 0x00000001, gf100_iccsense_new }, 1881 .imem = { 0x00000001, nv50_instmem_new }, 1882 .ltc = { 0x00000001, gk104_ltc_new }, 1883 .mc = { 0x00000001, gk20a_mc_new }, 1884 .mmu = { 0x00000001, gk104_mmu_new }, 1885 .mxm = { 0x00000001, nv50_mxm_new }, 1886 .pci = { 0x00000001, gk104_pci_new }, 1887 .pmu = { 0x00000001, gk208_pmu_new }, 1888 .privring = { 0x00000001, gk104_privring_new }, 1889 .therm = { 0x00000001, gk104_therm_new }, 1890 .timer = { 0x00000001, nv41_timer_new }, 1891 .top = { 0x00000001, gk104_top_new }, 1892 .volt = { 0x00000001, gk104_volt_new }, 1893 .ce = { 0x00000007, gk104_ce_new }, 1894 .disp = { 0x00000001, gk110_disp_new }, 1895 .dma = { 0x00000001, gf119_dma_new }, 1896 .fifo = { 0x00000001, gk208_fifo_new }, 1897 .gr = { 0x00000001, gk208_gr_new }, 1898 .mspdec = { 0x00000001, gk104_mspdec_new }, 1899 .msppp = { 0x00000001, gf100_msppp_new }, 1900 .msvld = { 0x00000001, gk104_msvld_new }, 1901 .sw = { 0x00000001, gf100_sw_new }, 1902 }; 1903 1904 static const struct nvkm_device_chip 1905 nv108_chipset = { 1906 .name = "GK208", 1907 .bar = { 0x00000001, gf100_bar_new }, 1908 .bios = { 0x00000001, nvkm_bios_new }, 1909 .bus = { 0x00000001, gf100_bus_new }, 1910 .clk = { 0x00000001, gk104_clk_new }, 1911 .devinit = { 0x00000001, gf100_devinit_new }, 1912 .fb = { 0x00000001, gk110_fb_new }, 1913 .fuse = { 0x00000001, gf100_fuse_new }, 1914 .gpio = { 0x00000001, gk104_gpio_new }, 1915 .i2c = { 0x00000001, gk110_i2c_new }, 1916 .iccsense = { 0x00000001, gf100_iccsense_new }, 1917 .imem = { 0x00000001, nv50_instmem_new }, 1918 .ltc = { 0x00000001, gk104_ltc_new }, 1919 .mc = { 0x00000001, gk20a_mc_new }, 1920 .mmu = { 0x00000001, gk104_mmu_new }, 1921 .mxm = { 0x00000001, nv50_mxm_new }, 1922 .pci = { 0x00000001, gk104_pci_new }, 1923 .pmu = { 0x00000001, gk208_pmu_new }, 1924 .privring = { 0x00000001, gk104_privring_new }, 1925 .therm = { 0x00000001, gk104_therm_new }, 1926 .timer = { 0x00000001, nv41_timer_new }, 1927 .top = { 0x00000001, gk104_top_new }, 1928 .volt = { 0x00000001, gk104_volt_new }, 1929 .ce = { 0x00000007, gk104_ce_new }, 1930 .disp = { 0x00000001, gk110_disp_new }, 1931 .dma = { 0x00000001, gf119_dma_new }, 1932 .fifo = { 0x00000001, gk208_fifo_new }, 1933 .gr = { 0x00000001, gk208_gr_new }, 1934 .mspdec = { 0x00000001, gk104_mspdec_new }, 1935 .msppp = { 0x00000001, gf100_msppp_new }, 1936 .msvld = { 0x00000001, gk104_msvld_new }, 1937 .sw = { 0x00000001, gf100_sw_new }, 1938 }; 1939 1940 static const struct nvkm_device_chip 1941 nv117_chipset = { 1942 .name = "GM107", 1943 .bar = { 0x00000001, gm107_bar_new }, 1944 .bios = { 0x00000001, nvkm_bios_new }, 1945 .bus = { 0x00000001, gf100_bus_new }, 1946 .clk = { 0x00000001, gk104_clk_new }, 1947 .devinit = { 0x00000001, gm107_devinit_new }, 1948 .fb = { 0x00000001, gm107_fb_new }, 1949 .fuse = { 0x00000001, gm107_fuse_new }, 1950 .gpio = { 0x00000001, gk104_gpio_new }, 1951 .i2c = { 0x00000001, gk110_i2c_new }, 1952 .iccsense = { 0x00000001, gf100_iccsense_new }, 1953 .imem = { 0x00000001, nv50_instmem_new }, 1954 .ltc = { 0x00000001, gm107_ltc_new }, 1955 .mc = { 0x00000001, gk20a_mc_new }, 1956 .mmu = { 0x00000001, gk104_mmu_new }, 1957 .mxm = { 0x00000001, nv50_mxm_new }, 1958 .pci = { 0x00000001, gk104_pci_new }, 1959 .pmu = { 0x00000001, gm107_pmu_new }, 1960 .privring = { 0x00000001, gk104_privring_new }, 1961 .therm = { 0x00000001, gm107_therm_new }, 1962 .timer = { 0x00000001, gk20a_timer_new }, 1963 .top = { 0x00000001, gk104_top_new }, 1964 .volt = { 0x00000001, gk104_volt_new }, 1965 .ce = { 0x00000005, gm107_ce_new }, 1966 .disp = { 0x00000001, gm107_disp_new }, 1967 .dma = { 0x00000001, gf119_dma_new }, 1968 .fifo = { 0x00000001, gm107_fifo_new }, 1969 .gr = { 0x00000001, gm107_gr_new }, 1970 .nvdec = { 0x00000001, gm107_nvdec_new }, 1971 .nvenc = { 0x00000001, gm107_nvenc_new }, 1972 .sw = { 0x00000001, gf100_sw_new }, 1973 }; 1974 1975 static const struct nvkm_device_chip 1976 nv118_chipset = { 1977 .name = "GM108", 1978 .bar = { 0x00000001, gm107_bar_new }, 1979 .bios = { 0x00000001, nvkm_bios_new }, 1980 .bus = { 0x00000001, gf100_bus_new }, 1981 .clk = { 0x00000001, gk104_clk_new }, 1982 .devinit = { 0x00000001, gm107_devinit_new }, 1983 .fb = { 0x00000001, gm107_fb_new }, 1984 .fuse = { 0x00000001, gm107_fuse_new }, 1985 .gpio = { 0x00000001, gk104_gpio_new }, 1986 .i2c = { 0x00000001, gk110_i2c_new }, 1987 .iccsense = { 0x00000001, gf100_iccsense_new }, 1988 .imem = { 0x00000001, nv50_instmem_new }, 1989 .ltc = { 0x00000001, gm107_ltc_new }, 1990 .mc = { 0x00000001, gk20a_mc_new }, 1991 .mmu = { 0x00000001, gk104_mmu_new }, 1992 .mxm = { 0x00000001, nv50_mxm_new }, 1993 .pci = { 0x00000001, gk104_pci_new }, 1994 .pmu = { 0x00000001, gm107_pmu_new }, 1995 .privring = { 0x00000001, gk104_privring_new }, 1996 .therm = { 0x00000001, gm107_therm_new }, 1997 .timer = { 0x00000001, gk20a_timer_new }, 1998 .top = { 0x00000001, gk104_top_new }, 1999 .volt = { 0x00000001, gk104_volt_new }, 2000 .ce = { 0x00000005, gm107_ce_new }, 2001 .disp = { 0x00000001, gm107_disp_new }, 2002 .dma = { 0x00000001, gf119_dma_new }, 2003 .fifo = { 0x00000001, gm107_fifo_new }, 2004 .gr = { 0x00000001, gm107_gr_new }, 2005 .sw = { 0x00000001, gf100_sw_new }, 2006 }; 2007 2008 static const struct nvkm_device_chip 2009 nv120_chipset = { 2010 .name = "GM200", 2011 .acr = { 0x00000001, gm200_acr_new }, 2012 .bar = { 0x00000001, gm107_bar_new }, 2013 .bios = { 0x00000001, nvkm_bios_new }, 2014 .bus = { 0x00000001, gf100_bus_new }, 2015 .devinit = { 0x00000001, gm200_devinit_new }, 2016 .fb = { 0x00000001, gm200_fb_new }, 2017 .fuse = { 0x00000001, gm107_fuse_new }, 2018 .gpio = { 0x00000001, gk104_gpio_new }, 2019 .i2c = { 0x00000001, gm200_i2c_new }, 2020 .iccsense = { 0x00000001, gf100_iccsense_new }, 2021 .imem = { 0x00000001, nv50_instmem_new }, 2022 .ltc = { 0x00000001, gm200_ltc_new }, 2023 .mc = { 0x00000001, gk20a_mc_new }, 2024 .mmu = { 0x00000001, gm200_mmu_new }, 2025 .mxm = { 0x00000001, nv50_mxm_new }, 2026 .pci = { 0x00000001, gk104_pci_new }, 2027 .pmu = { 0x00000001, gm200_pmu_new }, 2028 .privring = { 0x00000001, gm200_privring_new }, 2029 .therm = { 0x00000001, gm200_therm_new }, 2030 .timer = { 0x00000001, gk20a_timer_new }, 2031 .top = { 0x00000001, gk104_top_new }, 2032 .volt = { 0x00000001, gk104_volt_new }, 2033 .ce = { 0x00000007, gm200_ce_new }, 2034 .disp = { 0x00000001, gm200_disp_new }, 2035 .dma = { 0x00000001, gf119_dma_new }, 2036 .fifo = { 0x00000001, gm200_fifo_new }, 2037 .gr = { 0x00000001, gm200_gr_new }, 2038 .nvdec = { 0x00000001, gm107_nvdec_new }, 2039 .nvenc = { 0x00000003, gm107_nvenc_new }, 2040 .sw = { 0x00000001, gf100_sw_new }, 2041 }; 2042 2043 static const struct nvkm_device_chip 2044 nv124_chipset = { 2045 .name = "GM204", 2046 .acr = { 0x00000001, gm200_acr_new }, 2047 .bar = { 0x00000001, gm107_bar_new }, 2048 .bios = { 0x00000001, nvkm_bios_new }, 2049 .bus = { 0x00000001, gf100_bus_new }, 2050 .devinit = { 0x00000001, gm200_devinit_new }, 2051 .fb = { 0x00000001, gm200_fb_new }, 2052 .fuse = { 0x00000001, gm107_fuse_new }, 2053 .gpio = { 0x00000001, gk104_gpio_new }, 2054 .i2c = { 0x00000001, gm200_i2c_new }, 2055 .iccsense = { 0x00000001, gf100_iccsense_new }, 2056 .imem = { 0x00000001, nv50_instmem_new }, 2057 .ltc = { 0x00000001, gm200_ltc_new }, 2058 .mc = { 0x00000001, gk20a_mc_new }, 2059 .mmu = { 0x00000001, gm200_mmu_new }, 2060 .mxm = { 0x00000001, nv50_mxm_new }, 2061 .pci = { 0x00000001, gk104_pci_new }, 2062 .pmu = { 0x00000001, gm200_pmu_new }, 2063 .privring = { 0x00000001, gm200_privring_new }, 2064 .therm = { 0x00000001, gm200_therm_new }, 2065 .timer = { 0x00000001, gk20a_timer_new }, 2066 .top = { 0x00000001, gk104_top_new }, 2067 .volt = { 0x00000001, gk104_volt_new }, 2068 .ce = { 0x00000007, gm200_ce_new }, 2069 .disp = { 0x00000001, gm200_disp_new }, 2070 .dma = { 0x00000001, gf119_dma_new }, 2071 .fifo = { 0x00000001, gm200_fifo_new }, 2072 .gr = { 0x00000001, gm200_gr_new }, 2073 .nvdec = { 0x00000001, gm107_nvdec_new }, 2074 .nvenc = { 0x00000003, gm107_nvenc_new }, 2075 .sw = { 0x00000001, gf100_sw_new }, 2076 }; 2077 2078 static const struct nvkm_device_chip 2079 nv126_chipset = { 2080 .name = "GM206", 2081 .acr = { 0x00000001, gm200_acr_new }, 2082 .bar = { 0x00000001, gm107_bar_new }, 2083 .bios = { 0x00000001, nvkm_bios_new }, 2084 .bus = { 0x00000001, gf100_bus_new }, 2085 .devinit = { 0x00000001, gm200_devinit_new }, 2086 .fb = { 0x00000001, gm200_fb_new }, 2087 .fuse = { 0x00000001, gm107_fuse_new }, 2088 .gpio = { 0x00000001, gk104_gpio_new }, 2089 .i2c = { 0x00000001, gm200_i2c_new }, 2090 .iccsense = { 0x00000001, gf100_iccsense_new }, 2091 .imem = { 0x00000001, nv50_instmem_new }, 2092 .ltc = { 0x00000001, gm200_ltc_new }, 2093 .mc = { 0x00000001, gk20a_mc_new }, 2094 .mmu = { 0x00000001, gm200_mmu_new }, 2095 .mxm = { 0x00000001, nv50_mxm_new }, 2096 .pci = { 0x00000001, gk104_pci_new }, 2097 .pmu = { 0x00000001, gm200_pmu_new }, 2098 .privring = { 0x00000001, gm200_privring_new }, 2099 .therm = { 0x00000001, gm200_therm_new }, 2100 .timer = { 0x00000001, gk20a_timer_new }, 2101 .top = { 0x00000001, gk104_top_new }, 2102 .volt = { 0x00000001, gk104_volt_new }, 2103 .ce = { 0x00000007, gm200_ce_new }, 2104 .disp = { 0x00000001, gm200_disp_new }, 2105 .dma = { 0x00000001, gf119_dma_new }, 2106 .fifo = { 0x00000001, gm200_fifo_new }, 2107 .gr = { 0x00000001, gm200_gr_new }, 2108 .nvdec = { 0x00000001, gm107_nvdec_new }, 2109 .nvenc = { 0x00000001, gm107_nvenc_new }, 2110 .sw = { 0x00000001, gf100_sw_new }, 2111 }; 2112 2113 static const struct nvkm_device_chip 2114 nv12b_chipset = { 2115 .name = "GM20B", 2116 .acr = { 0x00000001, gm20b_acr_new }, 2117 .bar = { 0x00000001, gm20b_bar_new }, 2118 .bus = { 0x00000001, gf100_bus_new }, 2119 .clk = { 0x00000001, gm20b_clk_new }, 2120 .fb = { 0x00000001, gm20b_fb_new }, 2121 .fuse = { 0x00000001, gm107_fuse_new }, 2122 .imem = { 0x00000001, gk20a_instmem_new }, 2123 .ltc = { 0x00000001, gm200_ltc_new }, 2124 .mc = { 0x00000001, gk20a_mc_new }, 2125 .mmu = { 0x00000001, gm20b_mmu_new }, 2126 .pmu = { 0x00000001, gm20b_pmu_new }, 2127 .privring = { 0x00000001, gk20a_privring_new }, 2128 .timer = { 0x00000001, gk20a_timer_new }, 2129 .top = { 0x00000001, gk104_top_new }, 2130 .volt = { 0x00000001, gm20b_volt_new }, 2131 .ce = { 0x00000004, gm200_ce_new }, 2132 .dma = { 0x00000001, gf119_dma_new }, 2133 .fifo = { 0x00000001, gm200_fifo_new }, 2134 .gr = { 0x00000001, gm20b_gr_new }, 2135 .sw = { 0x00000001, gf100_sw_new }, 2136 }; 2137 2138 static const struct nvkm_device_chip 2139 nv130_chipset = { 2140 .name = "GP100", 2141 .acr = { 0x00000001, gm200_acr_new }, 2142 .bar = { 0x00000001, gm107_bar_new }, 2143 .bios = { 0x00000001, nvkm_bios_new }, 2144 .bus = { 0x00000001, gf100_bus_new }, 2145 .devinit = { 0x00000001, gm200_devinit_new }, 2146 .fault = { 0x00000001, gp100_fault_new }, 2147 .fb = { 0x00000001, gp100_fb_new }, 2148 .fuse = { 0x00000001, gm107_fuse_new }, 2149 .gpio = { 0x00000001, gk104_gpio_new }, 2150 .i2c = { 0x00000001, gm200_i2c_new }, 2151 .imem = { 0x00000001, nv50_instmem_new }, 2152 .ltc = { 0x00000001, gp100_ltc_new }, 2153 .mc = { 0x00000001, gp100_mc_new }, 2154 .mmu = { 0x00000001, gp100_mmu_new }, 2155 .therm = { 0x00000001, gp100_therm_new }, 2156 .pci = { 0x00000001, gp100_pci_new }, 2157 .pmu = { 0x00000001, gm200_pmu_new }, 2158 .privring = { 0x00000001, gm200_privring_new }, 2159 .timer = { 0x00000001, gk20a_timer_new }, 2160 .top = { 0x00000001, gk104_top_new }, 2161 .ce = { 0x0000003f, gp100_ce_new }, 2162 .dma = { 0x00000001, gf119_dma_new }, 2163 .disp = { 0x00000001, gp100_disp_new }, 2164 .fifo = { 0x00000001, gp100_fifo_new }, 2165 .gr = { 0x00000001, gp100_gr_new }, 2166 .nvdec = { 0x00000001, gm107_nvdec_new }, 2167 .nvenc = { 0x00000007, gm107_nvenc_new }, 2168 .sw = { 0x00000001, gf100_sw_new }, 2169 }; 2170 2171 static const struct nvkm_device_chip 2172 nv132_chipset = { 2173 .name = "GP102", 2174 .acr = { 0x00000001, gp102_acr_new }, 2175 .bar = { 0x00000001, gm107_bar_new }, 2176 .bios = { 0x00000001, nvkm_bios_new }, 2177 .bus = { 0x00000001, gf100_bus_new }, 2178 .devinit = { 0x00000001, gm200_devinit_new }, 2179 .fault = { 0x00000001, gp100_fault_new }, 2180 .fb = { 0x00000001, gp102_fb_new }, 2181 .fuse = { 0x00000001, gm107_fuse_new }, 2182 .gpio = { 0x00000001, gk104_gpio_new }, 2183 .i2c = { 0x00000001, gm200_i2c_new }, 2184 .imem = { 0x00000001, nv50_instmem_new }, 2185 .ltc = { 0x00000001, gp102_ltc_new }, 2186 .mc = { 0x00000001, gp100_mc_new }, 2187 .mmu = { 0x00000001, gp100_mmu_new }, 2188 .therm = { 0x00000001, gp100_therm_new }, 2189 .pci = { 0x00000001, gp100_pci_new }, 2190 .pmu = { 0x00000001, gp102_pmu_new }, 2191 .privring = { 0x00000001, gm200_privring_new }, 2192 .timer = { 0x00000001, gk20a_timer_new }, 2193 .top = { 0x00000001, gk104_top_new }, 2194 .ce = { 0x0000000f, gp102_ce_new }, 2195 .disp = { 0x00000001, gp102_disp_new }, 2196 .dma = { 0x00000001, gf119_dma_new }, 2197 .fifo = { 0x00000001, gp100_fifo_new }, 2198 .gr = { 0x00000001, gp102_gr_new }, 2199 .nvdec = { 0x00000001, gm107_nvdec_new }, 2200 .nvenc = { 0x00000003, gm107_nvenc_new }, 2201 .sec2 = { 0x00000001, gp102_sec2_new }, 2202 .sw = { 0x00000001, gf100_sw_new }, 2203 }; 2204 2205 static const struct nvkm_device_chip 2206 nv134_chipset = { 2207 .name = "GP104", 2208 .acr = { 0x00000001, gp102_acr_new }, 2209 .bar = { 0x00000001, gm107_bar_new }, 2210 .bios = { 0x00000001, nvkm_bios_new }, 2211 .bus = { 0x00000001, gf100_bus_new }, 2212 .devinit = { 0x00000001, gm200_devinit_new }, 2213 .fault = { 0x00000001, gp100_fault_new }, 2214 .fb = { 0x00000001, gp102_fb_new }, 2215 .fuse = { 0x00000001, gm107_fuse_new }, 2216 .gpio = { 0x00000001, gk104_gpio_new }, 2217 .i2c = { 0x00000001, gm200_i2c_new }, 2218 .imem = { 0x00000001, nv50_instmem_new }, 2219 .ltc = { 0x00000001, gp102_ltc_new }, 2220 .mc = { 0x00000001, gp100_mc_new }, 2221 .mmu = { 0x00000001, gp100_mmu_new }, 2222 .therm = { 0x00000001, gp100_therm_new }, 2223 .pci = { 0x00000001, gp100_pci_new }, 2224 .pmu = { 0x00000001, gp102_pmu_new }, 2225 .privring = { 0x00000001, gm200_privring_new }, 2226 .timer = { 0x00000001, gk20a_timer_new }, 2227 .top = { 0x00000001, gk104_top_new }, 2228 .ce = { 0x0000000f, gp102_ce_new }, 2229 .disp = { 0x00000001, gp102_disp_new }, 2230 .dma = { 0x00000001, gf119_dma_new }, 2231 .fifo = { 0x00000001, gp100_fifo_new }, 2232 .gr = { 0x00000001, gp104_gr_new }, 2233 .nvdec = { 0x00000001, gm107_nvdec_new }, 2234 .nvenc = { 0x00000003, gm107_nvenc_new }, 2235 .sec2 = { 0x00000001, gp102_sec2_new }, 2236 .sw = { 0x00000001, gf100_sw_new }, 2237 }; 2238 2239 static const struct nvkm_device_chip 2240 nv136_chipset = { 2241 .name = "GP106", 2242 .acr = { 0x00000001, gp102_acr_new }, 2243 .bar = { 0x00000001, gm107_bar_new }, 2244 .bios = { 0x00000001, nvkm_bios_new }, 2245 .bus = { 0x00000001, gf100_bus_new }, 2246 .devinit = { 0x00000001, gm200_devinit_new }, 2247 .fault = { 0x00000001, gp100_fault_new }, 2248 .fb = { 0x00000001, gp102_fb_new }, 2249 .fuse = { 0x00000001, gm107_fuse_new }, 2250 .gpio = { 0x00000001, gk104_gpio_new }, 2251 .i2c = { 0x00000001, gm200_i2c_new }, 2252 .imem = { 0x00000001, nv50_instmem_new }, 2253 .ltc = { 0x00000001, gp102_ltc_new }, 2254 .mc = { 0x00000001, gp100_mc_new }, 2255 .mmu = { 0x00000001, gp100_mmu_new }, 2256 .therm = { 0x00000001, gp100_therm_new }, 2257 .pci = { 0x00000001, gp100_pci_new }, 2258 .pmu = { 0x00000001, gp102_pmu_new }, 2259 .privring = { 0x00000001, gm200_privring_new }, 2260 .timer = { 0x00000001, gk20a_timer_new }, 2261 .top = { 0x00000001, gk104_top_new }, 2262 .ce = { 0x0000000f, gp102_ce_new }, 2263 .disp = { 0x00000001, gp102_disp_new }, 2264 .dma = { 0x00000001, gf119_dma_new }, 2265 .fifo = { 0x00000001, gp100_fifo_new }, 2266 .gr = { 0x00000001, gp104_gr_new }, 2267 .nvdec = { 0x00000001, gm107_nvdec_new }, 2268 .nvenc = { 0x00000001, gm107_nvenc_new }, 2269 .sec2 = { 0x00000001, gp102_sec2_new }, 2270 .sw = { 0x00000001, gf100_sw_new }, 2271 }; 2272 2273 static const struct nvkm_device_chip 2274 nv137_chipset = { 2275 .name = "GP107", 2276 .acr = { 0x00000001, gp102_acr_new }, 2277 .bar = { 0x00000001, gm107_bar_new }, 2278 .bios = { 0x00000001, nvkm_bios_new }, 2279 .bus = { 0x00000001, gf100_bus_new }, 2280 .devinit = { 0x00000001, gm200_devinit_new }, 2281 .fault = { 0x00000001, gp100_fault_new }, 2282 .fb = { 0x00000001, gp102_fb_new }, 2283 .fuse = { 0x00000001, gm107_fuse_new }, 2284 .gpio = { 0x00000001, gk104_gpio_new }, 2285 .i2c = { 0x00000001, gm200_i2c_new }, 2286 .imem = { 0x00000001, nv50_instmem_new }, 2287 .ltc = { 0x00000001, gp102_ltc_new }, 2288 .mc = { 0x00000001, gp100_mc_new }, 2289 .mmu = { 0x00000001, gp100_mmu_new }, 2290 .therm = { 0x00000001, gp100_therm_new }, 2291 .pci = { 0x00000001, gp100_pci_new }, 2292 .pmu = { 0x00000001, gp102_pmu_new }, 2293 .privring = { 0x00000001, gm200_privring_new }, 2294 .timer = { 0x00000001, gk20a_timer_new }, 2295 .top = { 0x00000001, gk104_top_new }, 2296 .ce = { 0x0000000f, gp102_ce_new }, 2297 .disp = { 0x00000001, gp102_disp_new }, 2298 .dma = { 0x00000001, gf119_dma_new }, 2299 .fifo = { 0x00000001, gp100_fifo_new }, 2300 .gr = { 0x00000001, gp107_gr_new }, 2301 .nvdec = { 0x00000001, gm107_nvdec_new }, 2302 .nvenc = { 0x00000003, gm107_nvenc_new }, 2303 .sec2 = { 0x00000001, gp102_sec2_new }, 2304 .sw = { 0x00000001, gf100_sw_new }, 2305 }; 2306 2307 static const struct nvkm_device_chip 2308 nv138_chipset = { 2309 .name = "GP108", 2310 .acr = { 0x00000001, gp108_acr_new }, 2311 .bar = { 0x00000001, gm107_bar_new }, 2312 .bios = { 0x00000001, nvkm_bios_new }, 2313 .bus = { 0x00000001, gf100_bus_new }, 2314 .devinit = { 0x00000001, gm200_devinit_new }, 2315 .fault = { 0x00000001, gp100_fault_new }, 2316 .fb = { 0x00000001, gp102_fb_new }, 2317 .fuse = { 0x00000001, gm107_fuse_new }, 2318 .gpio = { 0x00000001, gk104_gpio_new }, 2319 .i2c = { 0x00000001, gm200_i2c_new }, 2320 .imem = { 0x00000001, nv50_instmem_new }, 2321 .ltc = { 0x00000001, gp102_ltc_new }, 2322 .mc = { 0x00000001, gp100_mc_new }, 2323 .mmu = { 0x00000001, gp100_mmu_new }, 2324 .therm = { 0x00000001, gp100_therm_new }, 2325 .pci = { 0x00000001, gp100_pci_new }, 2326 .pmu = { 0x00000001, gp102_pmu_new }, 2327 .privring = { 0x00000001, gm200_privring_new }, 2328 .timer = { 0x00000001, gk20a_timer_new }, 2329 .top = { 0x00000001, gk104_top_new }, 2330 .ce = { 0x0000000f, gp102_ce_new }, 2331 .disp = { 0x00000001, gp102_disp_new }, 2332 .dma = { 0x00000001, gf119_dma_new }, 2333 .fifo = { 0x00000001, gp100_fifo_new }, 2334 .gr = { 0x00000001, gp108_gr_new }, 2335 .nvdec = { 0x00000001, gm107_nvdec_new }, 2336 .sec2 = { 0x00000001, gp108_sec2_new }, 2337 .sw = { 0x00000001, gf100_sw_new }, 2338 }; 2339 2340 static const struct nvkm_device_chip 2341 nv13b_chipset = { 2342 .name = "GP10B", 2343 .acr = { 0x00000001, gp10b_acr_new }, 2344 .bar = { 0x00000001, gm20b_bar_new }, 2345 .bus = { 0x00000001, gf100_bus_new }, 2346 .fault = { 0x00000001, gp10b_fault_new }, 2347 .fb = { 0x00000001, gp10b_fb_new }, 2348 .fuse = { 0x00000001, gm107_fuse_new }, 2349 .imem = { 0x00000001, gk20a_instmem_new }, 2350 .ltc = { 0x00000001, gp10b_ltc_new }, 2351 .mc = { 0x00000001, gp10b_mc_new }, 2352 .mmu = { 0x00000001, gp10b_mmu_new }, 2353 .pmu = { 0x00000001, gp10b_pmu_new }, 2354 .privring = { 0x00000001, gp10b_privring_new }, 2355 .timer = { 0x00000001, gk20a_timer_new }, 2356 .top = { 0x00000001, gk104_top_new }, 2357 .ce = { 0x00000001, gp100_ce_new }, 2358 .dma = { 0x00000001, gf119_dma_new }, 2359 .fifo = { 0x00000001, gp100_fifo_new }, 2360 .gr = { 0x00000001, gp10b_gr_new }, 2361 .sw = { 0x00000001, gf100_sw_new }, 2362 }; 2363 2364 static const struct nvkm_device_chip 2365 nv140_chipset = { 2366 .name = "GV100", 2367 .acr = { 0x00000001, gv100_acr_new }, 2368 .bar = { 0x00000001, gm107_bar_new }, 2369 .bios = { 0x00000001, nvkm_bios_new }, 2370 .bus = { 0x00000001, gf100_bus_new }, 2371 .devinit = { 0x00000001, gv100_devinit_new }, 2372 .fault = { 0x00000001, gv100_fault_new }, 2373 .fb = { 0x00000001, gv100_fb_new }, 2374 .fuse = { 0x00000001, gm107_fuse_new }, 2375 .gpio = { 0x00000001, gk104_gpio_new }, 2376 .gsp = { 0x00000001, gv100_gsp_new }, 2377 .i2c = { 0x00000001, gm200_i2c_new }, 2378 .imem = { 0x00000001, nv50_instmem_new }, 2379 .ltc = { 0x00000001, gp102_ltc_new }, 2380 .mc = { 0x00000001, gp100_mc_new }, 2381 .mmu = { 0x00000001, gv100_mmu_new }, 2382 .pci = { 0x00000001, gp100_pci_new }, 2383 .pmu = { 0x00000001, gp102_pmu_new }, 2384 .privring = { 0x00000001, gm200_privring_new }, 2385 .therm = { 0x00000001, gp100_therm_new }, 2386 .timer = { 0x00000001, gk20a_timer_new }, 2387 .top = { 0x00000001, gk104_top_new }, 2388 .vfn = { 0x00000001, gv100_vfn_new }, 2389 .ce = { 0x000001ff, gv100_ce_new }, 2390 .disp = { 0x00000001, gv100_disp_new }, 2391 .dma = { 0x00000001, gv100_dma_new }, 2392 .fifo = { 0x00000001, gv100_fifo_new }, 2393 .gr = { 0x00000001, gv100_gr_new }, 2394 .nvdec = { 0x00000001, gm107_nvdec_new }, 2395 .nvenc = { 0x00000007, gm107_nvenc_new }, 2396 .sec2 = { 0x00000001, gp108_sec2_new }, 2397 }; 2398 2399 static const struct nvkm_device_chip 2400 nv162_chipset = { 2401 .name = "TU102", 2402 .acr = { 0x00000001, tu102_acr_new }, 2403 .bar = { 0x00000001, tu102_bar_new }, 2404 .bios = { 0x00000001, nvkm_bios_new }, 2405 .bus = { 0x00000001, gf100_bus_new }, 2406 .devinit = { 0x00000001, tu102_devinit_new }, 2407 .fault = { 0x00000001, tu102_fault_new }, 2408 .fb = { 0x00000001, tu102_fb_new }, 2409 .fuse = { 0x00000001, gm107_fuse_new }, 2410 .gpio = { 0x00000001, gk104_gpio_new }, 2411 .gsp = { 0x00000001, gv100_gsp_new }, 2412 .i2c = { 0x00000001, gm200_i2c_new }, 2413 .imem = { 0x00000001, nv50_instmem_new }, 2414 .ltc = { 0x00000001, gp102_ltc_new }, 2415 .mc = { 0x00000001, gp100_mc_new }, 2416 .mmu = { 0x00000001, tu102_mmu_new }, 2417 .pci = { 0x00000001, gp100_pci_new }, 2418 .pmu = { 0x00000001, gp102_pmu_new }, 2419 .privring = { 0x00000001, gm200_privring_new }, 2420 .therm = { 0x00000001, gp100_therm_new }, 2421 .timer = { 0x00000001, gk20a_timer_new }, 2422 .top = { 0x00000001, gk104_top_new }, 2423 .vfn = { 0x00000001, tu102_vfn_new }, 2424 .ce = { 0x0000001f, tu102_ce_new }, 2425 .disp = { 0x00000001, tu102_disp_new }, 2426 .dma = { 0x00000001, gv100_dma_new }, 2427 .fifo = { 0x00000001, tu102_fifo_new }, 2428 .gr = { 0x00000001, tu102_gr_new }, 2429 .nvdec = { 0x00000001, gm107_nvdec_new }, 2430 .nvenc = { 0x00000001, gm107_nvenc_new }, 2431 .sec2 = { 0x00000001, tu102_sec2_new }, 2432 }; 2433 2434 static const struct nvkm_device_chip 2435 nv164_chipset = { 2436 .name = "TU104", 2437 .acr = { 0x00000001, tu102_acr_new }, 2438 .bar = { 0x00000001, tu102_bar_new }, 2439 .bios = { 0x00000001, nvkm_bios_new }, 2440 .bus = { 0x00000001, gf100_bus_new }, 2441 .devinit = { 0x00000001, tu102_devinit_new }, 2442 .fault = { 0x00000001, tu102_fault_new }, 2443 .fb = { 0x00000001, tu102_fb_new }, 2444 .fuse = { 0x00000001, gm107_fuse_new }, 2445 .gpio = { 0x00000001, gk104_gpio_new }, 2446 .gsp = { 0x00000001, gv100_gsp_new }, 2447 .i2c = { 0x00000001, gm200_i2c_new }, 2448 .imem = { 0x00000001, nv50_instmem_new }, 2449 .ltc = { 0x00000001, gp102_ltc_new }, 2450 .mc = { 0x00000001, gp100_mc_new }, 2451 .mmu = { 0x00000001, tu102_mmu_new }, 2452 .pci = { 0x00000001, gp100_pci_new }, 2453 .pmu = { 0x00000001, gp102_pmu_new }, 2454 .privring = { 0x00000001, gm200_privring_new }, 2455 .therm = { 0x00000001, gp100_therm_new }, 2456 .timer = { 0x00000001, gk20a_timer_new }, 2457 .top = { 0x00000001, gk104_top_new }, 2458 .vfn = { 0x00000001, tu102_vfn_new }, 2459 .ce = { 0x0000001f, tu102_ce_new }, 2460 .disp = { 0x00000001, tu102_disp_new }, 2461 .dma = { 0x00000001, gv100_dma_new }, 2462 .fifo = { 0x00000001, tu102_fifo_new }, 2463 .gr = { 0x00000001, tu102_gr_new }, 2464 .nvdec = { 0x00000003, gm107_nvdec_new }, 2465 .nvenc = { 0x00000001, gm107_nvenc_new }, 2466 .sec2 = { 0x00000001, tu102_sec2_new }, 2467 }; 2468 2469 static const struct nvkm_device_chip 2470 nv166_chipset = { 2471 .name = "TU106", 2472 .acr = { 0x00000001, tu102_acr_new }, 2473 .bar = { 0x00000001, tu102_bar_new }, 2474 .bios = { 0x00000001, nvkm_bios_new }, 2475 .bus = { 0x00000001, gf100_bus_new }, 2476 .devinit = { 0x00000001, tu102_devinit_new }, 2477 .fault = { 0x00000001, tu102_fault_new }, 2478 .fb = { 0x00000001, tu102_fb_new }, 2479 .fuse = { 0x00000001, gm107_fuse_new }, 2480 .gpio = { 0x00000001, gk104_gpio_new }, 2481 .gsp = { 0x00000001, gv100_gsp_new }, 2482 .i2c = { 0x00000001, gm200_i2c_new }, 2483 .imem = { 0x00000001, nv50_instmem_new }, 2484 .ltc = { 0x00000001, gp102_ltc_new }, 2485 .mc = { 0x00000001, gp100_mc_new }, 2486 .mmu = { 0x00000001, tu102_mmu_new }, 2487 .pci = { 0x00000001, gp100_pci_new }, 2488 .pmu = { 0x00000001, gp102_pmu_new }, 2489 .privring = { 0x00000001, gm200_privring_new }, 2490 .therm = { 0x00000001, gp100_therm_new }, 2491 .timer = { 0x00000001, gk20a_timer_new }, 2492 .top = { 0x00000001, gk104_top_new }, 2493 .vfn = { 0x00000001, tu102_vfn_new }, 2494 .ce = { 0x0000001f, tu102_ce_new }, 2495 .disp = { 0x00000001, tu102_disp_new }, 2496 .dma = { 0x00000001, gv100_dma_new }, 2497 .fifo = { 0x00000001, tu102_fifo_new }, 2498 .gr = { 0x00000001, tu102_gr_new }, 2499 .nvdec = { 0x00000007, gm107_nvdec_new }, 2500 .nvenc = { 0x00000001, gm107_nvenc_new }, 2501 .sec2 = { 0x00000001, tu102_sec2_new }, 2502 }; 2503 2504 static const struct nvkm_device_chip 2505 nv167_chipset = { 2506 .name = "TU117", 2507 .acr = { 0x00000001, tu102_acr_new }, 2508 .bar = { 0x00000001, tu102_bar_new }, 2509 .bios = { 0x00000001, nvkm_bios_new }, 2510 .bus = { 0x00000001, gf100_bus_new }, 2511 .devinit = { 0x00000001, tu102_devinit_new }, 2512 .fault = { 0x00000001, tu102_fault_new }, 2513 .fb = { 0x00000001, tu102_fb_new }, 2514 .fuse = { 0x00000001, gm107_fuse_new }, 2515 .gpio = { 0x00000001, gk104_gpio_new }, 2516 .gsp = { 0x00000001, gv100_gsp_new }, 2517 .i2c = { 0x00000001, gm200_i2c_new }, 2518 .imem = { 0x00000001, nv50_instmem_new }, 2519 .ltc = { 0x00000001, gp102_ltc_new }, 2520 .mc = { 0x00000001, gp100_mc_new }, 2521 .mmu = { 0x00000001, tu102_mmu_new }, 2522 .pci = { 0x00000001, gp100_pci_new }, 2523 .pmu = { 0x00000001, gp102_pmu_new }, 2524 .privring = { 0x00000001, gm200_privring_new }, 2525 .therm = { 0x00000001, gp100_therm_new }, 2526 .timer = { 0x00000001, gk20a_timer_new }, 2527 .top = { 0x00000001, gk104_top_new }, 2528 .vfn = { 0x00000001, tu102_vfn_new }, 2529 .ce = { 0x0000001f, tu102_ce_new }, 2530 .disp = { 0x00000001, tu102_disp_new }, 2531 .dma = { 0x00000001, gv100_dma_new }, 2532 .fifo = { 0x00000001, tu102_fifo_new }, 2533 .gr = { 0x00000001, tu102_gr_new }, 2534 .nvdec = { 0x00000001, gm107_nvdec_new }, 2535 .nvenc = { 0x00000001, gm107_nvenc_new }, 2536 .sec2 = { 0x00000001, tu102_sec2_new }, 2537 }; 2538 2539 static const struct nvkm_device_chip 2540 nv168_chipset = { 2541 .name = "TU116", 2542 .acr = { 0x00000001, tu102_acr_new }, 2543 .bar = { 0x00000001, tu102_bar_new }, 2544 .bios = { 0x00000001, nvkm_bios_new }, 2545 .bus = { 0x00000001, gf100_bus_new }, 2546 .devinit = { 0x00000001, tu102_devinit_new }, 2547 .fault = { 0x00000001, tu102_fault_new }, 2548 .fb = { 0x00000001, tu102_fb_new }, 2549 .fuse = { 0x00000001, gm107_fuse_new }, 2550 .gpio = { 0x00000001, gk104_gpio_new }, 2551 .gsp = { 0x00000001, gv100_gsp_new }, 2552 .i2c = { 0x00000001, gm200_i2c_new }, 2553 .imem = { 0x00000001, nv50_instmem_new }, 2554 .ltc = { 0x00000001, gp102_ltc_new }, 2555 .mc = { 0x00000001, gp100_mc_new }, 2556 .mmu = { 0x00000001, tu102_mmu_new }, 2557 .pci = { 0x00000001, gp100_pci_new }, 2558 .pmu = { 0x00000001, gp102_pmu_new }, 2559 .privring = { 0x00000001, gm200_privring_new }, 2560 .therm = { 0x00000001, gp100_therm_new }, 2561 .timer = { 0x00000001, gk20a_timer_new }, 2562 .top = { 0x00000001, gk104_top_new }, 2563 .vfn = { 0x00000001, tu102_vfn_new }, 2564 .ce = { 0x0000001f, tu102_ce_new }, 2565 .disp = { 0x00000001, tu102_disp_new }, 2566 .dma = { 0x00000001, gv100_dma_new }, 2567 .fifo = { 0x00000001, tu102_fifo_new }, 2568 .gr = { 0x00000001, tu102_gr_new }, 2569 .nvdec = { 0x00000001, gm107_nvdec_new }, 2570 .nvenc = { 0x00000001, gm107_nvenc_new }, 2571 .sec2 = { 0x00000001, tu102_sec2_new }, 2572 }; 2573 2574 static const struct nvkm_device_chip 2575 nv170_chipset = { 2576 .name = "GA100", 2577 .bar = { 0x00000001, tu102_bar_new }, 2578 .bios = { 0x00000001, nvkm_bios_new }, 2579 .devinit = { 0x00000001, ga100_devinit_new }, 2580 .fault = { 0x00000001, tu102_fault_new }, 2581 .fb = { 0x00000001, ga100_fb_new }, 2582 .gpio = { 0x00000001, gk104_gpio_new }, 2583 .i2c = { 0x00000001, gm200_i2c_new }, 2584 .imem = { 0x00000001, nv50_instmem_new }, 2585 .mc = { 0x00000001, ga100_mc_new }, 2586 .mmu = { 0x00000001, tu102_mmu_new }, 2587 .pci = { 0x00000001, gp100_pci_new }, 2588 .privring = { 0x00000001, gm200_privring_new }, 2589 .timer = { 0x00000001, gk20a_timer_new }, 2590 .top = { 0x00000001, ga100_top_new }, 2591 .vfn = { 0x00000001, ga100_vfn_new }, 2592 .ce = { 0x000003ff, ga100_ce_new }, 2593 .fifo = { 0x00000001, ga100_fifo_new }, 2594 }; 2595 2596 static const struct nvkm_device_chip 2597 nv172_chipset = { 2598 .name = "GA102", 2599 .acr = { 0x00000001, ga102_acr_new }, 2600 .bar = { 0x00000001, tu102_bar_new }, 2601 .bios = { 0x00000001, nvkm_bios_new }, 2602 .devinit = { 0x00000001, ga100_devinit_new }, 2603 .fault = { 0x00000001, tu102_fault_new }, 2604 .fb = { 0x00000001, ga102_fb_new }, 2605 .gpio = { 0x00000001, ga102_gpio_new }, 2606 .gsp = { 0x00000001, ga102_gsp_new }, 2607 .i2c = { 0x00000001, gm200_i2c_new }, 2608 .imem = { 0x00000001, nv50_instmem_new }, 2609 .ltc = { 0x00000001, ga102_ltc_new }, 2610 .mc = { 0x00000001, ga100_mc_new }, 2611 .mmu = { 0x00000001, tu102_mmu_new }, 2612 .pci = { 0x00000001, gp100_pci_new }, 2613 .privring = { 0x00000001, gm200_privring_new }, 2614 .timer = { 0x00000001, gk20a_timer_new }, 2615 .top = { 0x00000001, ga100_top_new }, 2616 .vfn = { 0x00000001, ga100_vfn_new }, 2617 .ce = { 0x0000001f, ga102_ce_new }, 2618 .disp = { 0x00000001, ga102_disp_new }, 2619 .dma = { 0x00000001, gv100_dma_new }, 2620 .fifo = { 0x00000001, ga102_fifo_new }, 2621 .gr = { 0x00000001, ga102_gr_new }, 2622 .nvdec = { 0x00000001, ga102_nvdec_new }, 2623 .sec2 = { 0x00000001, ga102_sec2_new }, 2624 }; 2625 2626 static const struct nvkm_device_chip 2627 nv173_chipset = { 2628 .name = "GA103", 2629 .acr = { 0x00000001, ga102_acr_new }, 2630 .bar = { 0x00000001, tu102_bar_new }, 2631 .bios = { 0x00000001, nvkm_bios_new }, 2632 .devinit = { 0x00000001, ga100_devinit_new }, 2633 .fault = { 0x00000001, tu102_fault_new }, 2634 .fb = { 0x00000001, ga102_fb_new }, 2635 .gpio = { 0x00000001, ga102_gpio_new }, 2636 .gsp = { 0x00000001, ga102_gsp_new }, 2637 .i2c = { 0x00000001, gm200_i2c_new }, 2638 .imem = { 0x00000001, nv50_instmem_new }, 2639 .ltc = { 0x00000001, ga102_ltc_new }, 2640 .mc = { 0x00000001, ga100_mc_new }, 2641 .mmu = { 0x00000001, tu102_mmu_new }, 2642 .pci = { 0x00000001, gp100_pci_new }, 2643 .privring = { 0x00000001, gm200_privring_new }, 2644 .timer = { 0x00000001, gk20a_timer_new }, 2645 .top = { 0x00000001, ga100_top_new }, 2646 .vfn = { 0x00000001, ga100_vfn_new }, 2647 .ce = { 0x0000001f, ga102_ce_new }, 2648 .disp = { 0x00000001, ga102_disp_new }, 2649 .dma = { 0x00000001, gv100_dma_new }, 2650 .fifo = { 0x00000001, ga102_fifo_new }, 2651 .gr = { 0x00000001, ga102_gr_new }, 2652 .nvdec = { 0x00000001, ga102_nvdec_new }, 2653 .sec2 = { 0x00000001, ga102_sec2_new }, 2654 }; 2655 2656 static const struct nvkm_device_chip 2657 nv174_chipset = { 2658 .name = "GA104", 2659 .acr = { 0x00000001, ga102_acr_new }, 2660 .bar = { 0x00000001, tu102_bar_new }, 2661 .bios = { 0x00000001, nvkm_bios_new }, 2662 .devinit = { 0x00000001, ga100_devinit_new }, 2663 .fault = { 0x00000001, tu102_fault_new }, 2664 .fb = { 0x00000001, ga102_fb_new }, 2665 .gpio = { 0x00000001, ga102_gpio_new }, 2666 .gsp = { 0x00000001, ga102_gsp_new }, 2667 .i2c = { 0x00000001, gm200_i2c_new }, 2668 .imem = { 0x00000001, nv50_instmem_new }, 2669 .ltc = { 0x00000001, ga102_ltc_new }, 2670 .mc = { 0x00000001, ga100_mc_new }, 2671 .mmu = { 0x00000001, tu102_mmu_new }, 2672 .pci = { 0x00000001, gp100_pci_new }, 2673 .privring = { 0x00000001, gm200_privring_new }, 2674 .timer = { 0x00000001, gk20a_timer_new }, 2675 .top = { 0x00000001, ga100_top_new }, 2676 .vfn = { 0x00000001, ga100_vfn_new }, 2677 .ce = { 0x0000001f, ga102_ce_new }, 2678 .disp = { 0x00000001, ga102_disp_new }, 2679 .dma = { 0x00000001, gv100_dma_new }, 2680 .fifo = { 0x00000001, ga102_fifo_new }, 2681 .gr = { 0x00000001, ga102_gr_new }, 2682 .nvdec = { 0x00000001, ga102_nvdec_new }, 2683 .sec2 = { 0x00000001, ga102_sec2_new }, 2684 }; 2685 2686 static const struct nvkm_device_chip 2687 nv176_chipset = { 2688 .name = "GA106", 2689 .acr = { 0x00000001, ga102_acr_new }, 2690 .bar = { 0x00000001, tu102_bar_new }, 2691 .bios = { 0x00000001, nvkm_bios_new }, 2692 .devinit = { 0x00000001, ga100_devinit_new }, 2693 .fault = { 0x00000001, tu102_fault_new }, 2694 .fb = { 0x00000001, ga102_fb_new }, 2695 .gpio = { 0x00000001, ga102_gpio_new }, 2696 .gsp = { 0x00000001, ga102_gsp_new }, 2697 .i2c = { 0x00000001, gm200_i2c_new }, 2698 .imem = { 0x00000001, nv50_instmem_new }, 2699 .ltc = { 0x00000001, ga102_ltc_new }, 2700 .mc = { 0x00000001, ga100_mc_new }, 2701 .mmu = { 0x00000001, tu102_mmu_new }, 2702 .pci = { 0x00000001, gp100_pci_new }, 2703 .privring = { 0x00000001, gm200_privring_new }, 2704 .timer = { 0x00000001, gk20a_timer_new }, 2705 .top = { 0x00000001, ga100_top_new }, 2706 .vfn = { 0x00000001, ga100_vfn_new }, 2707 .ce = { 0x0000001f, ga102_ce_new }, 2708 .disp = { 0x00000001, ga102_disp_new }, 2709 .dma = { 0x00000001, gv100_dma_new }, 2710 .fifo = { 0x00000001, ga102_fifo_new }, 2711 .gr = { 0x00000001, ga102_gr_new }, 2712 .nvdec = { 0x00000001, ga102_nvdec_new }, 2713 .sec2 = { 0x00000001, ga102_sec2_new }, 2714 }; 2715 2716 static const struct nvkm_device_chip 2717 nv177_chipset = { 2718 .name = "GA107", 2719 .acr = { 0x00000001, ga102_acr_new }, 2720 .bar = { 0x00000001, tu102_bar_new }, 2721 .bios = { 0x00000001, nvkm_bios_new }, 2722 .devinit = { 0x00000001, ga100_devinit_new }, 2723 .fault = { 0x00000001, tu102_fault_new }, 2724 .fb = { 0x00000001, ga102_fb_new }, 2725 .gpio = { 0x00000001, ga102_gpio_new }, 2726 .gsp = { 0x00000001, ga102_gsp_new }, 2727 .i2c = { 0x00000001, gm200_i2c_new }, 2728 .imem = { 0x00000001, nv50_instmem_new }, 2729 .ltc = { 0x00000001, ga102_ltc_new }, 2730 .mc = { 0x00000001, ga100_mc_new }, 2731 .mmu = { 0x00000001, tu102_mmu_new }, 2732 .pci = { 0x00000001, gp100_pci_new }, 2733 .privring = { 0x00000001, gm200_privring_new }, 2734 .timer = { 0x00000001, gk20a_timer_new }, 2735 .top = { 0x00000001, ga100_top_new }, 2736 .vfn = { 0x00000001, ga100_vfn_new }, 2737 .ce = { 0x0000001f, ga102_ce_new }, 2738 .disp = { 0x00000001, ga102_disp_new }, 2739 .dma = { 0x00000001, gv100_dma_new }, 2740 .fifo = { 0x00000001, ga102_fifo_new }, 2741 .gr = { 0x00000001, ga102_gr_new }, 2742 .nvdec = { 0x00000001, ga102_nvdec_new }, 2743 .sec2 = { 0x00000001, ga102_sec2_new }, 2744 }; 2745 2746 struct nvkm_subdev * 2747 nvkm_device_subdev(struct nvkm_device *device, int type, int inst) 2748 { 2749 struct nvkm_subdev *subdev; 2750 2751 list_for_each_entry(subdev, &device->subdev, head) { 2752 if (subdev->type == type && subdev->inst == inst) 2753 return subdev; 2754 } 2755 2756 return NULL; 2757 } 2758 2759 struct nvkm_engine * 2760 nvkm_device_engine(struct nvkm_device *device, int type, int inst) 2761 { 2762 struct nvkm_subdev *subdev = nvkm_device_subdev(device, type, inst); 2763 if (subdev && subdev->func == &nvkm_engine) 2764 return container_of(subdev, struct nvkm_engine, subdev); 2765 return NULL; 2766 } 2767 2768 int 2769 nvkm_device_fini(struct nvkm_device *device, bool suspend) 2770 { 2771 const char *action = suspend ? "suspend" : "fini"; 2772 struct nvkm_subdev *subdev; 2773 int ret; 2774 s64 time; 2775 2776 nvdev_trace(device, "%s running...\n", action); 2777 time = ktime_to_us(ktime_get()); 2778 2779 nvkm_acpi_fini(device); 2780 2781 list_for_each_entry_reverse(subdev, &device->subdev, head) { 2782 ret = nvkm_subdev_fini(subdev, suspend); 2783 if (ret && suspend) 2784 goto fail; 2785 } 2786 2787 nvkm_therm_clkgate_fini(device->therm, suspend); 2788 2789 if (device->func->fini) 2790 device->func->fini(device, suspend); 2791 2792 nvkm_intr_unarm(device); 2793 2794 time = ktime_to_us(ktime_get()) - time; 2795 nvdev_trace(device, "%s completed in %lldus...\n", action, time); 2796 return 0; 2797 2798 fail: 2799 list_for_each_entry_from(subdev, &device->subdev, head) { 2800 int rret = nvkm_subdev_init(subdev); 2801 if (rret) 2802 nvkm_fatal(subdev, "failed restart, %d\n", ret); 2803 } 2804 2805 nvdev_trace(device, "%s failed with %d\n", action, ret); 2806 return ret; 2807 } 2808 2809 static int 2810 nvkm_device_preinit(struct nvkm_device *device) 2811 { 2812 struct nvkm_subdev *subdev; 2813 int ret; 2814 s64 time; 2815 2816 nvdev_trace(device, "preinit running...\n"); 2817 time = ktime_to_us(ktime_get()); 2818 2819 nvkm_intr_unarm(device); 2820 2821 if (device->func->preinit) { 2822 ret = device->func->preinit(device); 2823 if (ret) 2824 goto fail; 2825 } 2826 2827 list_for_each_entry(subdev, &device->subdev, head) { 2828 ret = nvkm_subdev_preinit(subdev); 2829 if (ret) 2830 goto fail; 2831 } 2832 2833 ret = nvkm_devinit_post(device->devinit); 2834 if (ret) 2835 goto fail; 2836 2837 ret = nvkm_top_parse(device); 2838 if (ret) 2839 goto fail; 2840 2841 ret = nvkm_fb_mem_unlock(device->fb); 2842 if (ret) 2843 goto fail; 2844 2845 time = ktime_to_us(ktime_get()) - time; 2846 nvdev_trace(device, "preinit completed in %lldus\n", time); 2847 return 0; 2848 2849 fail: 2850 nvdev_error(device, "preinit failed with %d\n", ret); 2851 return ret; 2852 } 2853 2854 int 2855 nvkm_device_init(struct nvkm_device *device) 2856 { 2857 struct nvkm_subdev *subdev; 2858 int ret; 2859 s64 time; 2860 2861 ret = nvkm_device_preinit(device); 2862 if (ret) 2863 return ret; 2864 2865 nvkm_device_fini(device, false); 2866 2867 nvdev_trace(device, "init running...\n"); 2868 time = ktime_to_us(ktime_get()); 2869 2870 nvkm_intr_rearm(device); 2871 2872 if (device->func->init) { 2873 ret = device->func->init(device); 2874 if (ret) 2875 goto fail; 2876 } 2877 2878 list_for_each_entry(subdev, &device->subdev, head) { 2879 ret = nvkm_subdev_init(subdev); 2880 if (ret) 2881 goto fail_subdev; 2882 } 2883 2884 nvkm_acpi_init(device); 2885 nvkm_therm_clkgate_enable(device->therm); 2886 2887 time = ktime_to_us(ktime_get()) - time; 2888 nvdev_trace(device, "init completed in %lldus\n", time); 2889 return 0; 2890 2891 fail_subdev: 2892 list_for_each_entry_from(subdev, &device->subdev, head) 2893 nvkm_subdev_fini(subdev, false); 2894 fail: 2895 nvkm_device_fini(device, false); 2896 2897 nvdev_error(device, "init failed with %d\n", ret); 2898 return ret; 2899 } 2900 2901 void 2902 nvkm_device_del(struct nvkm_device **pdevice) 2903 { 2904 struct nvkm_device *device = *pdevice; 2905 struct nvkm_subdev *subdev, *subtmp; 2906 if (device) { 2907 mutex_lock(&nv_devices_mutex); 2908 2909 nvkm_intr_dtor(device); 2910 2911 list_for_each_entry_safe_reverse(subdev, subtmp, &device->subdev, head) 2912 nvkm_subdev_del(&subdev); 2913 2914 if (device->pri) 2915 iounmap(device->pri); 2916 list_del(&device->head); 2917 2918 if (device->func->dtor) 2919 *pdevice = device->func->dtor(device); 2920 mutex_unlock(&nv_devices_mutex); 2921 2922 kfree(*pdevice); 2923 *pdevice = NULL; 2924 } 2925 } 2926 2927 /* returns true if the GPU is in the CPU native byte order */ 2928 static inline bool 2929 nvkm_device_endianness(struct nvkm_device *device) 2930 { 2931 #ifdef __BIG_ENDIAN 2932 const bool big_endian = true; 2933 #else 2934 const bool big_endian = false; 2935 #endif 2936 2937 /* Read NV_PMC_BOOT_1, and assume non-functional endian switch if it 2938 * doesn't contain the expected values. 2939 */ 2940 u32 pmc_boot_1 = nvkm_rd32(device, 0x000004); 2941 if (pmc_boot_1 && pmc_boot_1 != 0x01000001) 2942 return !big_endian; /* Assume GPU is LE in this case. */ 2943 2944 /* 0 means LE and 0x01000001 means BE GPU. Condition is true when 2945 * GPU/CPU endianness don't match. 2946 */ 2947 if (big_endian == !pmc_boot_1) { 2948 nvkm_wr32(device, 0x000004, 0x01000001); 2949 nvkm_rd32(device, 0x000000); 2950 if (nvkm_rd32(device, 0x000004) != (big_endian ? 0x01000001 : 0x00000000)) 2951 return !big_endian; /* Assume GPU is LE on any unexpected read-back. */ 2952 } 2953 2954 /* CPU/GPU endianness should (hopefully) match. */ 2955 return true; 2956 } 2957 2958 int 2959 nvkm_device_ctor(const struct nvkm_device_func *func, 2960 const struct nvkm_device_quirk *quirk, 2961 struct device *dev, enum nvkm_device_type type, u64 handle, 2962 const char *name, const char *cfg, const char *dbg, 2963 bool detect, bool mmio, u64 subdev_mask, 2964 struct nvkm_device *device) 2965 { 2966 struct nvkm_subdev *subdev; 2967 u64 mmio_base, mmio_size; 2968 u32 boot0, boot1, strap; 2969 int ret = -EEXIST, j; 2970 unsigned chipset; 2971 2972 mutex_lock(&nv_devices_mutex); 2973 if (nvkm_device_find_locked(handle)) 2974 goto done; 2975 2976 device->func = func; 2977 device->quirk = quirk; 2978 device->dev = dev; 2979 device->type = type; 2980 device->handle = handle; 2981 device->cfgopt = cfg; 2982 device->dbgopt = dbg; 2983 device->name = name; 2984 list_add_tail(&device->head, &nv_devices); 2985 device->debug = nvkm_dbgopt(device->dbgopt, "device"); 2986 INIT_LIST_HEAD(&device->subdev); 2987 2988 mmio_base = device->func->resource_addr(device, 0); 2989 mmio_size = device->func->resource_size(device, 0); 2990 2991 if (detect || mmio) { 2992 device->pri = ioremap(mmio_base, mmio_size); 2993 if (device->pri == NULL) { 2994 nvdev_error(device, "unable to map PRI\n"); 2995 ret = -ENOMEM; 2996 goto done; 2997 } 2998 } 2999 3000 /* identify the chipset, and determine classes of subdev/engines */ 3001 if (detect) { 3002 /* switch mmio to cpu's native endianness */ 3003 if (!nvkm_device_endianness(device)) { 3004 nvdev_error(device, 3005 "Couldn't switch GPU to CPUs endianness\n"); 3006 ret = -ENOSYS; 3007 goto done; 3008 } 3009 3010 boot0 = nvkm_rd32(device, 0x000000); 3011 3012 /* chipset can be overridden for devel/testing purposes */ 3013 chipset = nvkm_longopt(device->cfgopt, "NvChipset", 0); 3014 if (chipset) { 3015 u32 override_boot0; 3016 3017 if (chipset >= 0x10) { 3018 override_boot0 = ((chipset & 0x1ff) << 20); 3019 override_boot0 |= 0x000000a1; 3020 } else { 3021 if (chipset != 0x04) 3022 override_boot0 = 0x20104000; 3023 else 3024 override_boot0 = 0x20004000; 3025 } 3026 3027 nvdev_warn(device, "CHIPSET OVERRIDE: %08x -> %08x\n", 3028 boot0, override_boot0); 3029 boot0 = override_boot0; 3030 } 3031 3032 /* determine chipset and derive architecture from it */ 3033 if ((boot0 & 0x1f000000) > 0) { 3034 device->chipset = (boot0 & 0x1ff00000) >> 20; 3035 device->chiprev = (boot0 & 0x000000ff); 3036 switch (device->chipset & 0x1f0) { 3037 case 0x010: { 3038 if (0x461 & (1 << (device->chipset & 0xf))) 3039 device->card_type = NV_10; 3040 else 3041 device->card_type = NV_11; 3042 device->chiprev = 0x00; 3043 break; 3044 } 3045 case 0x020: device->card_type = NV_20; break; 3046 case 0x030: device->card_type = NV_30; break; 3047 case 0x040: 3048 case 0x060: device->card_type = NV_40; break; 3049 case 0x050: 3050 case 0x080: 3051 case 0x090: 3052 case 0x0a0: device->card_type = NV_50; break; 3053 case 0x0c0: 3054 case 0x0d0: device->card_type = NV_C0; break; 3055 case 0x0e0: 3056 case 0x0f0: 3057 case 0x100: device->card_type = NV_E0; break; 3058 case 0x110: 3059 case 0x120: device->card_type = GM100; break; 3060 case 0x130: device->card_type = GP100; break; 3061 case 0x140: device->card_type = GV100; break; 3062 case 0x160: device->card_type = TU100; break; 3063 case 0x170: device->card_type = GA100; break; 3064 default: 3065 break; 3066 } 3067 } else 3068 if ((boot0 & 0xff00fff0) == 0x20004000) { 3069 if (boot0 & 0x00f00000) 3070 device->chipset = 0x05; 3071 else 3072 device->chipset = 0x04; 3073 device->card_type = NV_04; 3074 } 3075 3076 switch (device->chipset) { 3077 case 0x004: device->chip = &nv4_chipset; break; 3078 case 0x005: device->chip = &nv5_chipset; break; 3079 case 0x010: device->chip = &nv10_chipset; break; 3080 case 0x011: device->chip = &nv11_chipset; break; 3081 case 0x015: device->chip = &nv15_chipset; break; 3082 case 0x017: device->chip = &nv17_chipset; break; 3083 case 0x018: device->chip = &nv18_chipset; break; 3084 case 0x01a: device->chip = &nv1a_chipset; break; 3085 case 0x01f: device->chip = &nv1f_chipset; break; 3086 case 0x020: device->chip = &nv20_chipset; break; 3087 case 0x025: device->chip = &nv25_chipset; break; 3088 case 0x028: device->chip = &nv28_chipset; break; 3089 case 0x02a: device->chip = &nv2a_chipset; break; 3090 case 0x030: device->chip = &nv30_chipset; break; 3091 case 0x031: device->chip = &nv31_chipset; break; 3092 case 0x034: device->chip = &nv34_chipset; break; 3093 case 0x035: device->chip = &nv35_chipset; break; 3094 case 0x036: device->chip = &nv36_chipset; break; 3095 case 0x040: device->chip = &nv40_chipset; break; 3096 case 0x041: device->chip = &nv41_chipset; break; 3097 case 0x042: device->chip = &nv42_chipset; break; 3098 case 0x043: device->chip = &nv43_chipset; break; 3099 case 0x044: device->chip = &nv44_chipset; break; 3100 case 0x045: device->chip = &nv45_chipset; break; 3101 case 0x046: device->chip = &nv46_chipset; break; 3102 case 0x047: device->chip = &nv47_chipset; break; 3103 case 0x049: device->chip = &nv49_chipset; break; 3104 case 0x04a: device->chip = &nv4a_chipset; break; 3105 case 0x04b: device->chip = &nv4b_chipset; break; 3106 case 0x04c: device->chip = &nv4c_chipset; break; 3107 case 0x04e: device->chip = &nv4e_chipset; break; 3108 case 0x050: device->chip = &nv50_chipset; break; 3109 case 0x063: device->chip = &nv63_chipset; break; 3110 case 0x067: device->chip = &nv67_chipset; break; 3111 case 0x068: device->chip = &nv68_chipset; break; 3112 case 0x084: device->chip = &nv84_chipset; break; 3113 case 0x086: device->chip = &nv86_chipset; break; 3114 case 0x092: device->chip = &nv92_chipset; break; 3115 case 0x094: device->chip = &nv94_chipset; break; 3116 case 0x096: device->chip = &nv96_chipset; break; 3117 case 0x098: device->chip = &nv98_chipset; break; 3118 case 0x0a0: device->chip = &nva0_chipset; break; 3119 case 0x0a3: device->chip = &nva3_chipset; break; 3120 case 0x0a5: device->chip = &nva5_chipset; break; 3121 case 0x0a8: device->chip = &nva8_chipset; break; 3122 case 0x0aa: device->chip = &nvaa_chipset; break; 3123 case 0x0ac: device->chip = &nvac_chipset; break; 3124 case 0x0af: device->chip = &nvaf_chipset; break; 3125 case 0x0c0: device->chip = &nvc0_chipset; break; 3126 case 0x0c1: device->chip = &nvc1_chipset; break; 3127 case 0x0c3: device->chip = &nvc3_chipset; break; 3128 case 0x0c4: device->chip = &nvc4_chipset; break; 3129 case 0x0c8: device->chip = &nvc8_chipset; break; 3130 case 0x0ce: device->chip = &nvce_chipset; break; 3131 case 0x0cf: device->chip = &nvcf_chipset; break; 3132 case 0x0d7: device->chip = &nvd7_chipset; break; 3133 case 0x0d9: device->chip = &nvd9_chipset; break; 3134 case 0x0e4: device->chip = &nve4_chipset; break; 3135 case 0x0e6: device->chip = &nve6_chipset; break; 3136 case 0x0e7: device->chip = &nve7_chipset; break; 3137 case 0x0ea: device->chip = &nvea_chipset; break; 3138 case 0x0f0: device->chip = &nvf0_chipset; break; 3139 case 0x0f1: device->chip = &nvf1_chipset; break; 3140 case 0x106: device->chip = &nv106_chipset; break; 3141 case 0x108: device->chip = &nv108_chipset; break; 3142 case 0x117: device->chip = &nv117_chipset; break; 3143 case 0x118: device->chip = &nv118_chipset; break; 3144 case 0x120: device->chip = &nv120_chipset; break; 3145 case 0x124: device->chip = &nv124_chipset; break; 3146 case 0x126: device->chip = &nv126_chipset; break; 3147 case 0x12b: device->chip = &nv12b_chipset; break; 3148 case 0x130: device->chip = &nv130_chipset; break; 3149 case 0x132: device->chip = &nv132_chipset; break; 3150 case 0x134: device->chip = &nv134_chipset; break; 3151 case 0x136: device->chip = &nv136_chipset; break; 3152 case 0x137: device->chip = &nv137_chipset; break; 3153 case 0x138: device->chip = &nv138_chipset; break; 3154 case 0x13b: device->chip = &nv13b_chipset; break; 3155 case 0x140: device->chip = &nv140_chipset; break; 3156 case 0x162: device->chip = &nv162_chipset; break; 3157 case 0x164: device->chip = &nv164_chipset; break; 3158 case 0x166: device->chip = &nv166_chipset; break; 3159 case 0x167: device->chip = &nv167_chipset; break; 3160 case 0x168: device->chip = &nv168_chipset; break; 3161 case 0x172: device->chip = &nv172_chipset; break; 3162 case 0x173: device->chip = &nv173_chipset; break; 3163 case 0x174: device->chip = &nv174_chipset; break; 3164 case 0x176: device->chip = &nv176_chipset; break; 3165 case 0x177: device->chip = &nv177_chipset; break; 3166 default: 3167 if (nvkm_boolopt(device->cfgopt, "NvEnableUnsupportedChipsets", false)) { 3168 switch (device->chipset) { 3169 case 0x170: device->chip = &nv170_chipset; break; 3170 default: 3171 break; 3172 } 3173 } 3174 3175 if (!device->chip) { 3176 nvdev_error(device, "unknown chipset (%08x)\n", boot0); 3177 ret = -ENODEV; 3178 goto done; 3179 } 3180 break; 3181 } 3182 3183 nvdev_info(device, "NVIDIA %s (%08x)\n", 3184 device->chip->name, boot0); 3185 3186 /* vGPU detection */ 3187 boot1 = nvkm_rd32(device, 0x0000004); 3188 if (device->card_type >= TU100 && (boot1 & 0x00030000)) { 3189 nvdev_info(device, "vGPUs are not supported\n"); 3190 ret = -ENODEV; 3191 goto done; 3192 } 3193 3194 /* read strapping information */ 3195 strap = nvkm_rd32(device, 0x101000); 3196 3197 /* determine frequency of timing crystal */ 3198 if ( device->card_type <= NV_10 || device->chipset < 0x17 || 3199 (device->chipset >= 0x20 && device->chipset < 0x25)) 3200 strap &= 0x00000040; 3201 else 3202 strap &= 0x00400040; 3203 3204 switch (strap) { 3205 case 0x00000000: device->crystal = 13500; break; 3206 case 0x00000040: device->crystal = 14318; break; 3207 case 0x00400000: device->crystal = 27000; break; 3208 case 0x00400040: device->crystal = 25000; break; 3209 } 3210 } else { 3211 device->chip = &null_chipset; 3212 } 3213 3214 if (!device->name) 3215 device->name = device->chip->name; 3216 3217 mutex_init(&device->mutex); 3218 nvkm_intr_ctor(device); 3219 3220 #define NVKM_LAYOUT_ONCE(type,data,ptr) \ 3221 if (device->chip->ptr.inst && (subdev_mask & (BIT_ULL(type)))) { \ 3222 WARN_ON(device->chip->ptr.inst != 0x00000001); \ 3223 ret = device->chip->ptr.ctor(device, (type), -1, &device->ptr); \ 3224 subdev = nvkm_device_subdev(device, (type), 0); \ 3225 if (ret) { \ 3226 nvkm_subdev_del(&subdev); \ 3227 device->ptr = NULL; \ 3228 if (ret != -ENODEV) { \ 3229 nvdev_error(device, "%s ctor failed: %d\n", \ 3230 nvkm_subdev_type[(type)], ret); \ 3231 goto done; \ 3232 } \ 3233 } else { \ 3234 subdev->pself = (void **)&device->ptr; \ 3235 } \ 3236 } 3237 #define NVKM_LAYOUT_INST(type,data,ptr,cnt) \ 3238 WARN_ON(device->chip->ptr.inst & ~((1 << ARRAY_SIZE(device->ptr)) - 1)); \ 3239 for (j = 0; device->chip->ptr.inst && j < ARRAY_SIZE(device->ptr); j++) { \ 3240 if ((device->chip->ptr.inst & BIT(j)) && (subdev_mask & BIT_ULL(type))) { \ 3241 ret = device->chip->ptr.ctor(device, (type), (j), &device->ptr[j]); \ 3242 subdev = nvkm_device_subdev(device, (type), (j)); \ 3243 if (ret) { \ 3244 nvkm_subdev_del(&subdev); \ 3245 device->ptr[j] = NULL; \ 3246 if (ret != -ENODEV) { \ 3247 nvdev_error(device, "%s%d ctor failed: %d\n", \ 3248 nvkm_subdev_type[(type)], (j), ret); \ 3249 goto done; \ 3250 } \ 3251 } else { \ 3252 subdev->pself = (void **)&device->ptr[j]; \ 3253 } \ 3254 } \ 3255 } 3256 #include <core/layout.h> 3257 #undef NVKM_LAYOUT_INST 3258 #undef NVKM_LAYOUT_ONCE 3259 3260 ret = nvkm_intr_install(device); 3261 done: 3262 if (device->pri && (!mmio || ret)) { 3263 iounmap(device->pri); 3264 device->pri = NULL; 3265 } 3266 mutex_unlock(&nv_devices_mutex); 3267 return ret; 3268 } 3269