1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "priv.h"
25 #include "acpi.h"
26 
27 #include <core/notify.h>
28 #include <core/option.h>
29 
30 #include <subdev/bios.h>
31 
32 static DEFINE_MUTEX(nv_devices_mutex);
33 static LIST_HEAD(nv_devices);
34 
35 static struct nvkm_device *
36 nvkm_device_find_locked(u64 handle)
37 {
38 	struct nvkm_device *device;
39 	list_for_each_entry(device, &nv_devices, head) {
40 		if (device->handle == handle)
41 			return device;
42 	}
43 	return NULL;
44 }
45 
46 struct nvkm_device *
47 nvkm_device_find(u64 handle)
48 {
49 	struct nvkm_device *device;
50 	mutex_lock(&nv_devices_mutex);
51 	device = nvkm_device_find_locked(handle);
52 	mutex_unlock(&nv_devices_mutex);
53 	return device;
54 }
55 
56 int
57 nvkm_device_list(u64 *name, int size)
58 {
59 	struct nvkm_device *device;
60 	int nr = 0;
61 	mutex_lock(&nv_devices_mutex);
62 	list_for_each_entry(device, &nv_devices, head) {
63 		if (nr++ < size)
64 			name[nr - 1] = device->handle;
65 	}
66 	mutex_unlock(&nv_devices_mutex);
67 	return nr;
68 }
69 
70 static const struct nvkm_device_chip
71 null_chipset = {
72 	.name = "NULL",
73 	.bios = nvkm_bios_new,
74 };
75 
76 static const struct nvkm_device_chip
77 nv4_chipset = {
78 	.name = "NV04",
79 	.bios = nvkm_bios_new,
80 	.bus = nv04_bus_new,
81 	.clk = nv04_clk_new,
82 	.devinit = nv04_devinit_new,
83 	.fb = nv04_fb_new,
84 	.i2c = nv04_i2c_new,
85 	.imem = nv04_instmem_new,
86 	.mc = nv04_mc_new,
87 	.mmu = nv04_mmu_new,
88 	.pci = nv04_pci_new,
89 	.timer = nv04_timer_new,
90 	.disp = nv04_disp_new,
91 	.dma = nv04_dma_new,
92 	.fifo = nv04_fifo_new,
93 	.gr = nv04_gr_new,
94 	.sw = nv04_sw_new,
95 };
96 
97 static const struct nvkm_device_chip
98 nv5_chipset = {
99 	.name = "NV05",
100 	.bios = nvkm_bios_new,
101 	.bus = nv04_bus_new,
102 	.clk = nv04_clk_new,
103 	.devinit = nv05_devinit_new,
104 	.fb = nv04_fb_new,
105 	.i2c = nv04_i2c_new,
106 	.imem = nv04_instmem_new,
107 	.mc = nv04_mc_new,
108 	.mmu = nv04_mmu_new,
109 	.pci = nv04_pci_new,
110 	.timer = nv04_timer_new,
111 	.disp = nv04_disp_new,
112 	.dma = nv04_dma_new,
113 	.fifo = nv04_fifo_new,
114 	.gr = nv04_gr_new,
115 	.sw = nv04_sw_new,
116 };
117 
118 static const struct nvkm_device_chip
119 nv10_chipset = {
120 	.name = "NV10",
121 	.bios = nvkm_bios_new,
122 	.bus = nv04_bus_new,
123 	.clk = nv04_clk_new,
124 	.devinit = nv10_devinit_new,
125 	.fb = nv10_fb_new,
126 	.gpio = nv10_gpio_new,
127 	.i2c = nv04_i2c_new,
128 	.imem = nv04_instmem_new,
129 	.mc = nv04_mc_new,
130 	.mmu = nv04_mmu_new,
131 	.pci = nv04_pci_new,
132 	.timer = nv04_timer_new,
133 	.disp = nv04_disp_new,
134 	.dma = nv04_dma_new,
135 	.gr = nv10_gr_new,
136 };
137 
138 static const struct nvkm_device_chip
139 nv11_chipset = {
140 	.name = "NV11",
141 	.bios = nvkm_bios_new,
142 	.bus = nv04_bus_new,
143 	.clk = nv04_clk_new,
144 	.devinit = nv10_devinit_new,
145 	.fb = nv10_fb_new,
146 	.gpio = nv10_gpio_new,
147 	.i2c = nv04_i2c_new,
148 	.imem = nv04_instmem_new,
149 	.mc = nv11_mc_new,
150 	.mmu = nv04_mmu_new,
151 	.pci = nv04_pci_new,
152 	.timer = nv04_timer_new,
153 	.disp = nv04_disp_new,
154 	.dma = nv04_dma_new,
155 	.fifo = nv10_fifo_new,
156 	.gr = nv15_gr_new,
157 	.sw = nv10_sw_new,
158 };
159 
160 static const struct nvkm_device_chip
161 nv15_chipset = {
162 	.name = "NV15",
163 	.bios = nvkm_bios_new,
164 	.bus = nv04_bus_new,
165 	.clk = nv04_clk_new,
166 	.devinit = nv10_devinit_new,
167 	.fb = nv10_fb_new,
168 	.gpio = nv10_gpio_new,
169 	.i2c = nv04_i2c_new,
170 	.imem = nv04_instmem_new,
171 	.mc = nv04_mc_new,
172 	.mmu = nv04_mmu_new,
173 	.pci = nv04_pci_new,
174 	.timer = nv04_timer_new,
175 	.disp = nv04_disp_new,
176 	.dma = nv04_dma_new,
177 	.fifo = nv10_fifo_new,
178 	.gr = nv15_gr_new,
179 	.sw = nv10_sw_new,
180 };
181 
182 static const struct nvkm_device_chip
183 nv17_chipset = {
184 	.name = "NV17",
185 	.bios = nvkm_bios_new,
186 	.bus = nv04_bus_new,
187 	.clk = nv04_clk_new,
188 	.devinit = nv10_devinit_new,
189 	.fb = nv10_fb_new,
190 	.gpio = nv10_gpio_new,
191 	.i2c = nv04_i2c_new,
192 	.imem = nv04_instmem_new,
193 	.mc = nv17_mc_new,
194 	.mmu = nv04_mmu_new,
195 	.pci = nv04_pci_new,
196 	.timer = nv04_timer_new,
197 	.disp = nv04_disp_new,
198 	.dma = nv04_dma_new,
199 	.fifo = nv17_fifo_new,
200 	.gr = nv17_gr_new,
201 	.sw = nv10_sw_new,
202 };
203 
204 static const struct nvkm_device_chip
205 nv18_chipset = {
206 	.name = "NV18",
207 	.bios = nvkm_bios_new,
208 	.bus = nv04_bus_new,
209 	.clk = nv04_clk_new,
210 	.devinit = nv10_devinit_new,
211 	.fb = nv10_fb_new,
212 	.gpio = nv10_gpio_new,
213 	.i2c = nv04_i2c_new,
214 	.imem = nv04_instmem_new,
215 	.mc = nv17_mc_new,
216 	.mmu = nv04_mmu_new,
217 	.pci = nv04_pci_new,
218 	.timer = nv04_timer_new,
219 	.disp = nv04_disp_new,
220 	.dma = nv04_dma_new,
221 	.fifo = nv17_fifo_new,
222 	.gr = nv17_gr_new,
223 	.sw = nv10_sw_new,
224 };
225 
226 static const struct nvkm_device_chip
227 nv1a_chipset = {
228 	.name = "nForce",
229 	.bios = nvkm_bios_new,
230 	.bus = nv04_bus_new,
231 	.clk = nv04_clk_new,
232 	.devinit = nv1a_devinit_new,
233 	.fb = nv1a_fb_new,
234 	.gpio = nv10_gpio_new,
235 	.i2c = nv04_i2c_new,
236 	.imem = nv04_instmem_new,
237 	.mc = nv04_mc_new,
238 	.mmu = nv04_mmu_new,
239 	.pci = nv04_pci_new,
240 	.timer = nv04_timer_new,
241 	.disp = nv04_disp_new,
242 	.dma = nv04_dma_new,
243 	.fifo = nv10_fifo_new,
244 	.gr = nv15_gr_new,
245 	.sw = nv10_sw_new,
246 };
247 
248 static const struct nvkm_device_chip
249 nv1f_chipset = {
250 	.name = "nForce2",
251 	.bios = nvkm_bios_new,
252 	.bus = nv04_bus_new,
253 	.clk = nv04_clk_new,
254 	.devinit = nv1a_devinit_new,
255 	.fb = nv1a_fb_new,
256 	.gpio = nv10_gpio_new,
257 	.i2c = nv04_i2c_new,
258 	.imem = nv04_instmem_new,
259 	.mc = nv17_mc_new,
260 	.mmu = nv04_mmu_new,
261 	.pci = nv04_pci_new,
262 	.timer = nv04_timer_new,
263 	.disp = nv04_disp_new,
264 	.dma = nv04_dma_new,
265 	.fifo = nv17_fifo_new,
266 	.gr = nv17_gr_new,
267 	.sw = nv10_sw_new,
268 };
269 
270 static const struct nvkm_device_chip
271 nv20_chipset = {
272 	.name = "NV20",
273 	.bios = nvkm_bios_new,
274 	.bus = nv04_bus_new,
275 	.clk = nv04_clk_new,
276 	.devinit = nv20_devinit_new,
277 	.fb = nv20_fb_new,
278 	.gpio = nv10_gpio_new,
279 	.i2c = nv04_i2c_new,
280 	.imem = nv04_instmem_new,
281 	.mc = nv17_mc_new,
282 	.mmu = nv04_mmu_new,
283 	.pci = nv04_pci_new,
284 	.timer = nv04_timer_new,
285 	.disp = nv04_disp_new,
286 	.dma = nv04_dma_new,
287 	.fifo = nv17_fifo_new,
288 	.gr = nv20_gr_new,
289 	.sw = nv10_sw_new,
290 };
291 
292 static const struct nvkm_device_chip
293 nv25_chipset = {
294 	.name = "NV25",
295 	.bios = nvkm_bios_new,
296 	.bus = nv04_bus_new,
297 	.clk = nv04_clk_new,
298 	.devinit = nv20_devinit_new,
299 	.fb = nv25_fb_new,
300 	.gpio = nv10_gpio_new,
301 	.i2c = nv04_i2c_new,
302 	.imem = nv04_instmem_new,
303 	.mc = nv17_mc_new,
304 	.mmu = nv04_mmu_new,
305 	.pci = nv04_pci_new,
306 	.timer = nv04_timer_new,
307 	.disp = nv04_disp_new,
308 	.dma = nv04_dma_new,
309 	.fifo = nv17_fifo_new,
310 	.gr = nv25_gr_new,
311 	.sw = nv10_sw_new,
312 };
313 
314 static const struct nvkm_device_chip
315 nv28_chipset = {
316 	.name = "NV28",
317 	.bios = nvkm_bios_new,
318 	.bus = nv04_bus_new,
319 	.clk = nv04_clk_new,
320 	.devinit = nv20_devinit_new,
321 	.fb = nv25_fb_new,
322 	.gpio = nv10_gpio_new,
323 	.i2c = nv04_i2c_new,
324 	.imem = nv04_instmem_new,
325 	.mc = nv17_mc_new,
326 	.mmu = nv04_mmu_new,
327 	.pci = nv04_pci_new,
328 	.timer = nv04_timer_new,
329 	.disp = nv04_disp_new,
330 	.dma = nv04_dma_new,
331 	.fifo = nv17_fifo_new,
332 	.gr = nv25_gr_new,
333 	.sw = nv10_sw_new,
334 };
335 
336 static const struct nvkm_device_chip
337 nv2a_chipset = {
338 	.name = "NV2A",
339 	.bios = nvkm_bios_new,
340 	.bus = nv04_bus_new,
341 	.clk = nv04_clk_new,
342 	.devinit = nv20_devinit_new,
343 	.fb = nv25_fb_new,
344 	.gpio = nv10_gpio_new,
345 	.i2c = nv04_i2c_new,
346 	.imem = nv04_instmem_new,
347 	.mc = nv17_mc_new,
348 	.mmu = nv04_mmu_new,
349 	.pci = nv04_pci_new,
350 	.timer = nv04_timer_new,
351 	.disp = nv04_disp_new,
352 	.dma = nv04_dma_new,
353 	.fifo = nv17_fifo_new,
354 	.gr = nv2a_gr_new,
355 	.sw = nv10_sw_new,
356 };
357 
358 static const struct nvkm_device_chip
359 nv30_chipset = {
360 	.name = "NV30",
361 	.bios = nvkm_bios_new,
362 	.bus = nv04_bus_new,
363 	.clk = nv04_clk_new,
364 	.devinit = nv20_devinit_new,
365 	.fb = nv30_fb_new,
366 	.gpio = nv10_gpio_new,
367 	.i2c = nv04_i2c_new,
368 	.imem = nv04_instmem_new,
369 	.mc = nv17_mc_new,
370 	.mmu = nv04_mmu_new,
371 	.pci = nv04_pci_new,
372 	.timer = nv04_timer_new,
373 	.disp = nv04_disp_new,
374 	.dma = nv04_dma_new,
375 	.fifo = nv17_fifo_new,
376 	.gr = nv30_gr_new,
377 	.sw = nv10_sw_new,
378 };
379 
380 static const struct nvkm_device_chip
381 nv31_chipset = {
382 	.name = "NV31",
383 	.bios = nvkm_bios_new,
384 	.bus = nv31_bus_new,
385 	.clk = nv04_clk_new,
386 	.devinit = nv20_devinit_new,
387 	.fb = nv30_fb_new,
388 	.gpio = nv10_gpio_new,
389 	.i2c = nv04_i2c_new,
390 	.imem = nv04_instmem_new,
391 	.mc = nv17_mc_new,
392 	.mmu = nv04_mmu_new,
393 	.pci = nv04_pci_new,
394 	.timer = nv04_timer_new,
395 	.disp = nv04_disp_new,
396 	.dma = nv04_dma_new,
397 	.fifo = nv17_fifo_new,
398 	.gr = nv30_gr_new,
399 	.mpeg = nv31_mpeg_new,
400 	.sw = nv10_sw_new,
401 };
402 
403 static const struct nvkm_device_chip
404 nv34_chipset = {
405 	.name = "NV34",
406 	.bios = nvkm_bios_new,
407 	.bus = nv31_bus_new,
408 	.clk = nv04_clk_new,
409 	.devinit = nv10_devinit_new,
410 	.fb = nv10_fb_new,
411 	.gpio = nv10_gpio_new,
412 	.i2c = nv04_i2c_new,
413 	.imem = nv04_instmem_new,
414 	.mc = nv17_mc_new,
415 	.mmu = nv04_mmu_new,
416 	.pci = nv04_pci_new,
417 	.timer = nv04_timer_new,
418 	.disp = nv04_disp_new,
419 	.dma = nv04_dma_new,
420 	.fifo = nv17_fifo_new,
421 	.gr = nv34_gr_new,
422 	.mpeg = nv31_mpeg_new,
423 	.sw = nv10_sw_new,
424 };
425 
426 static const struct nvkm_device_chip
427 nv35_chipset = {
428 	.name = "NV35",
429 	.bios = nvkm_bios_new,
430 	.bus = nv04_bus_new,
431 	.clk = nv04_clk_new,
432 	.devinit = nv20_devinit_new,
433 	.fb = nv35_fb_new,
434 	.gpio = nv10_gpio_new,
435 	.i2c = nv04_i2c_new,
436 	.imem = nv04_instmem_new,
437 	.mc = nv17_mc_new,
438 	.mmu = nv04_mmu_new,
439 	.pci = nv04_pci_new,
440 	.timer = nv04_timer_new,
441 	.disp = nv04_disp_new,
442 	.dma = nv04_dma_new,
443 	.fifo = nv17_fifo_new,
444 	.gr = nv35_gr_new,
445 	.sw = nv10_sw_new,
446 };
447 
448 static const struct nvkm_device_chip
449 nv36_chipset = {
450 	.name = "NV36",
451 	.bios = nvkm_bios_new,
452 	.bus = nv31_bus_new,
453 	.clk = nv04_clk_new,
454 	.devinit = nv20_devinit_new,
455 	.fb = nv36_fb_new,
456 	.gpio = nv10_gpio_new,
457 	.i2c = nv04_i2c_new,
458 	.imem = nv04_instmem_new,
459 	.mc = nv17_mc_new,
460 	.mmu = nv04_mmu_new,
461 	.pci = nv04_pci_new,
462 	.timer = nv04_timer_new,
463 	.disp = nv04_disp_new,
464 	.dma = nv04_dma_new,
465 	.fifo = nv17_fifo_new,
466 	.gr = nv35_gr_new,
467 	.mpeg = nv31_mpeg_new,
468 	.sw = nv10_sw_new,
469 };
470 
471 static const struct nvkm_device_chip
472 nv40_chipset = {
473 	.name = "NV40",
474 	.bios = nvkm_bios_new,
475 	.bus = nv31_bus_new,
476 	.clk = nv40_clk_new,
477 	.devinit = nv1a_devinit_new,
478 	.fb = nv40_fb_new,
479 	.gpio = nv10_gpio_new,
480 	.i2c = nv04_i2c_new,
481 	.imem = nv40_instmem_new,
482 	.mc = nv17_mc_new,
483 	.mmu = nv04_mmu_new,
484 	.pci = nv40_pci_new,
485 	.therm = nv40_therm_new,
486 	.timer = nv40_timer_new,
487 	.volt = nv40_volt_new,
488 	.disp = nv04_disp_new,
489 	.dma = nv04_dma_new,
490 	.fifo = nv40_fifo_new,
491 	.gr = nv40_gr_new,
492 	.mpeg = nv40_mpeg_new,
493 	.pm = nv40_pm_new,
494 	.sw = nv10_sw_new,
495 };
496 
497 static const struct nvkm_device_chip
498 nv41_chipset = {
499 	.name = "NV41",
500 	.bios = nvkm_bios_new,
501 	.bus = nv31_bus_new,
502 	.clk = nv40_clk_new,
503 	.devinit = nv1a_devinit_new,
504 	.fb = nv41_fb_new,
505 	.gpio = nv10_gpio_new,
506 	.i2c = nv04_i2c_new,
507 	.imem = nv40_instmem_new,
508 	.mc = nv17_mc_new,
509 	.mmu = nv41_mmu_new,
510 	.pci = nv40_pci_new,
511 	.therm = nv40_therm_new,
512 	.timer = nv41_timer_new,
513 	.volt = nv40_volt_new,
514 	.disp = nv04_disp_new,
515 	.dma = nv04_dma_new,
516 	.fifo = nv40_fifo_new,
517 	.gr = nv40_gr_new,
518 	.mpeg = nv40_mpeg_new,
519 	.pm = nv40_pm_new,
520 	.sw = nv10_sw_new,
521 };
522 
523 static const struct nvkm_device_chip
524 nv42_chipset = {
525 	.name = "NV42",
526 	.bios = nvkm_bios_new,
527 	.bus = nv31_bus_new,
528 	.clk = nv40_clk_new,
529 	.devinit = nv1a_devinit_new,
530 	.fb = nv41_fb_new,
531 	.gpio = nv10_gpio_new,
532 	.i2c = nv04_i2c_new,
533 	.imem = nv40_instmem_new,
534 	.mc = nv17_mc_new,
535 	.mmu = nv41_mmu_new,
536 	.pci = nv40_pci_new,
537 	.therm = nv40_therm_new,
538 	.timer = nv41_timer_new,
539 	.volt = nv40_volt_new,
540 	.disp = nv04_disp_new,
541 	.dma = nv04_dma_new,
542 	.fifo = nv40_fifo_new,
543 	.gr = nv40_gr_new,
544 	.mpeg = nv40_mpeg_new,
545 	.pm = nv40_pm_new,
546 	.sw = nv10_sw_new,
547 };
548 
549 static const struct nvkm_device_chip
550 nv43_chipset = {
551 	.name = "NV43",
552 	.bios = nvkm_bios_new,
553 	.bus = nv31_bus_new,
554 	.clk = nv40_clk_new,
555 	.devinit = nv1a_devinit_new,
556 	.fb = nv41_fb_new,
557 	.gpio = nv10_gpio_new,
558 	.i2c = nv04_i2c_new,
559 	.imem = nv40_instmem_new,
560 	.mc = nv17_mc_new,
561 	.mmu = nv41_mmu_new,
562 	.pci = nv40_pci_new,
563 	.therm = nv40_therm_new,
564 	.timer = nv41_timer_new,
565 	.volt = nv40_volt_new,
566 	.disp = nv04_disp_new,
567 	.dma = nv04_dma_new,
568 	.fifo = nv40_fifo_new,
569 	.gr = nv40_gr_new,
570 	.mpeg = nv40_mpeg_new,
571 	.pm = nv40_pm_new,
572 	.sw = nv10_sw_new,
573 };
574 
575 static const struct nvkm_device_chip
576 nv44_chipset = {
577 	.name = "NV44",
578 	.bios = nvkm_bios_new,
579 	.bus = nv31_bus_new,
580 	.clk = nv40_clk_new,
581 	.devinit = nv1a_devinit_new,
582 	.fb = nv44_fb_new,
583 	.gpio = nv10_gpio_new,
584 	.i2c = nv04_i2c_new,
585 	.imem = nv40_instmem_new,
586 	.mc = nv44_mc_new,
587 	.mmu = nv44_mmu_new,
588 	.pci = nv40_pci_new,
589 	.therm = nv40_therm_new,
590 	.timer = nv41_timer_new,
591 	.volt = nv40_volt_new,
592 	.disp = nv04_disp_new,
593 	.dma = nv04_dma_new,
594 	.fifo = nv40_fifo_new,
595 	.gr = nv44_gr_new,
596 	.mpeg = nv44_mpeg_new,
597 	.pm = nv40_pm_new,
598 	.sw = nv10_sw_new,
599 };
600 
601 static const struct nvkm_device_chip
602 nv45_chipset = {
603 	.name = "NV45",
604 	.bios = nvkm_bios_new,
605 	.bus = nv31_bus_new,
606 	.clk = nv40_clk_new,
607 	.devinit = nv1a_devinit_new,
608 	.fb = nv40_fb_new,
609 	.gpio = nv10_gpio_new,
610 	.i2c = nv04_i2c_new,
611 	.imem = nv40_instmem_new,
612 	.mc = nv17_mc_new,
613 	.mmu = nv04_mmu_new,
614 	.pci = nv40_pci_new,
615 	.therm = nv40_therm_new,
616 	.timer = nv41_timer_new,
617 	.volt = nv40_volt_new,
618 	.disp = nv04_disp_new,
619 	.dma = nv04_dma_new,
620 	.fifo = nv40_fifo_new,
621 	.gr = nv40_gr_new,
622 	.mpeg = nv44_mpeg_new,
623 	.pm = nv40_pm_new,
624 	.sw = nv10_sw_new,
625 };
626 
627 static const struct nvkm_device_chip
628 nv46_chipset = {
629 	.name = "G72",
630 	.bios = nvkm_bios_new,
631 	.bus = nv31_bus_new,
632 	.clk = nv40_clk_new,
633 	.devinit = nv1a_devinit_new,
634 	.fb = nv46_fb_new,
635 	.gpio = nv10_gpio_new,
636 	.i2c = nv04_i2c_new,
637 	.imem = nv40_instmem_new,
638 	.mc = nv44_mc_new,
639 	.mmu = nv44_mmu_new,
640 	.pci = nv46_pci_new,
641 	.therm = nv40_therm_new,
642 	.timer = nv41_timer_new,
643 	.volt = nv40_volt_new,
644 	.disp = nv04_disp_new,
645 	.dma = nv04_dma_new,
646 	.fifo = nv40_fifo_new,
647 	.gr = nv44_gr_new,
648 	.mpeg = nv44_mpeg_new,
649 	.pm = nv40_pm_new,
650 	.sw = nv10_sw_new,
651 };
652 
653 static const struct nvkm_device_chip
654 nv47_chipset = {
655 	.name = "G70",
656 	.bios = nvkm_bios_new,
657 	.bus = nv31_bus_new,
658 	.clk = nv40_clk_new,
659 	.devinit = nv1a_devinit_new,
660 	.fb = nv47_fb_new,
661 	.gpio = nv10_gpio_new,
662 	.i2c = nv04_i2c_new,
663 	.imem = nv40_instmem_new,
664 	.mc = nv17_mc_new,
665 	.mmu = nv41_mmu_new,
666 	.pci = nv40_pci_new,
667 	.therm = nv40_therm_new,
668 	.timer = nv41_timer_new,
669 	.volt = nv40_volt_new,
670 	.disp = nv04_disp_new,
671 	.dma = nv04_dma_new,
672 	.fifo = nv40_fifo_new,
673 	.gr = nv40_gr_new,
674 	.mpeg = nv44_mpeg_new,
675 	.pm = nv40_pm_new,
676 	.sw = nv10_sw_new,
677 };
678 
679 static const struct nvkm_device_chip
680 nv49_chipset = {
681 	.name = "G71",
682 	.bios = nvkm_bios_new,
683 	.bus = nv31_bus_new,
684 	.clk = nv40_clk_new,
685 	.devinit = nv1a_devinit_new,
686 	.fb = nv49_fb_new,
687 	.gpio = nv10_gpio_new,
688 	.i2c = nv04_i2c_new,
689 	.imem = nv40_instmem_new,
690 	.mc = nv17_mc_new,
691 	.mmu = nv41_mmu_new,
692 	.pci = nv40_pci_new,
693 	.therm = nv40_therm_new,
694 	.timer = nv41_timer_new,
695 	.volt = nv40_volt_new,
696 	.disp = nv04_disp_new,
697 	.dma = nv04_dma_new,
698 	.fifo = nv40_fifo_new,
699 	.gr = nv40_gr_new,
700 	.mpeg = nv44_mpeg_new,
701 	.pm = nv40_pm_new,
702 	.sw = nv10_sw_new,
703 };
704 
705 static const struct nvkm_device_chip
706 nv4a_chipset = {
707 	.name = "NV44A",
708 	.bios = nvkm_bios_new,
709 	.bus = nv31_bus_new,
710 	.clk = nv40_clk_new,
711 	.devinit = nv1a_devinit_new,
712 	.fb = nv44_fb_new,
713 	.gpio = nv10_gpio_new,
714 	.i2c = nv04_i2c_new,
715 	.imem = nv40_instmem_new,
716 	.mc = nv44_mc_new,
717 	.mmu = nv44_mmu_new,
718 	.pci = nv40_pci_new,
719 	.therm = nv40_therm_new,
720 	.timer = nv41_timer_new,
721 	.volt = nv40_volt_new,
722 	.disp = nv04_disp_new,
723 	.dma = nv04_dma_new,
724 	.fifo = nv40_fifo_new,
725 	.gr = nv44_gr_new,
726 	.mpeg = nv44_mpeg_new,
727 	.pm = nv40_pm_new,
728 	.sw = nv10_sw_new,
729 };
730 
731 static const struct nvkm_device_chip
732 nv4b_chipset = {
733 	.name = "G73",
734 	.bios = nvkm_bios_new,
735 	.bus = nv31_bus_new,
736 	.clk = nv40_clk_new,
737 	.devinit = nv1a_devinit_new,
738 	.fb = nv49_fb_new,
739 	.gpio = nv10_gpio_new,
740 	.i2c = nv04_i2c_new,
741 	.imem = nv40_instmem_new,
742 	.mc = nv17_mc_new,
743 	.mmu = nv41_mmu_new,
744 	.pci = nv40_pci_new,
745 	.therm = nv40_therm_new,
746 	.timer = nv41_timer_new,
747 	.volt = nv40_volt_new,
748 	.disp = nv04_disp_new,
749 	.dma = nv04_dma_new,
750 	.fifo = nv40_fifo_new,
751 	.gr = nv40_gr_new,
752 	.mpeg = nv44_mpeg_new,
753 	.pm = nv40_pm_new,
754 	.sw = nv10_sw_new,
755 };
756 
757 static const struct nvkm_device_chip
758 nv4c_chipset = {
759 	.name = "C61",
760 	.bios = nvkm_bios_new,
761 	.bus = nv31_bus_new,
762 	.clk = nv40_clk_new,
763 	.devinit = nv1a_devinit_new,
764 	.fb = nv46_fb_new,
765 	.gpio = nv10_gpio_new,
766 	.i2c = nv04_i2c_new,
767 	.imem = nv40_instmem_new,
768 	.mc = nv44_mc_new,
769 	.mmu = nv44_mmu_new,
770 	.pci = nv4c_pci_new,
771 	.therm = nv40_therm_new,
772 	.timer = nv41_timer_new,
773 	.volt = nv40_volt_new,
774 	.disp = nv04_disp_new,
775 	.dma = nv04_dma_new,
776 	.fifo = nv40_fifo_new,
777 	.gr = nv44_gr_new,
778 	.mpeg = nv44_mpeg_new,
779 	.pm = nv40_pm_new,
780 	.sw = nv10_sw_new,
781 };
782 
783 static const struct nvkm_device_chip
784 nv4e_chipset = {
785 	.name = "C51",
786 	.bios = nvkm_bios_new,
787 	.bus = nv31_bus_new,
788 	.clk = nv40_clk_new,
789 	.devinit = nv1a_devinit_new,
790 	.fb = nv4e_fb_new,
791 	.gpio = nv10_gpio_new,
792 	.i2c = nv4e_i2c_new,
793 	.imem = nv40_instmem_new,
794 	.mc = nv44_mc_new,
795 	.mmu = nv44_mmu_new,
796 	.pci = nv4c_pci_new,
797 	.therm = nv40_therm_new,
798 	.timer = nv41_timer_new,
799 	.volt = nv40_volt_new,
800 	.disp = nv04_disp_new,
801 	.dma = nv04_dma_new,
802 	.fifo = nv40_fifo_new,
803 	.gr = nv44_gr_new,
804 	.mpeg = nv44_mpeg_new,
805 	.pm = nv40_pm_new,
806 	.sw = nv10_sw_new,
807 };
808 
809 static const struct nvkm_device_chip
810 nv50_chipset = {
811 	.name = "G80",
812 	.bar = nv50_bar_new,
813 	.bios = nvkm_bios_new,
814 	.bus = nv50_bus_new,
815 	.clk = nv50_clk_new,
816 	.devinit = nv50_devinit_new,
817 	.fb = nv50_fb_new,
818 	.fuse = nv50_fuse_new,
819 	.gpio = nv50_gpio_new,
820 	.i2c = nv50_i2c_new,
821 	.imem = nv50_instmem_new,
822 	.mc = nv50_mc_new,
823 	.mmu = nv50_mmu_new,
824 	.mxm = nv50_mxm_new,
825 	.pci = nv46_pci_new,
826 	.therm = nv50_therm_new,
827 	.timer = nv41_timer_new,
828 	.volt = nv40_volt_new,
829 	.disp = nv50_disp_new,
830 	.dma = nv50_dma_new,
831 	.fifo = nv50_fifo_new,
832 	.gr = nv50_gr_new,
833 	.mpeg = nv50_mpeg_new,
834 	.pm = nv50_pm_new,
835 	.sw = nv50_sw_new,
836 };
837 
838 static const struct nvkm_device_chip
839 nv63_chipset = {
840 	.name = "C73",
841 	.bios = nvkm_bios_new,
842 	.bus = nv31_bus_new,
843 	.clk = nv40_clk_new,
844 	.devinit = nv1a_devinit_new,
845 	.fb = nv46_fb_new,
846 	.gpio = nv10_gpio_new,
847 	.i2c = nv04_i2c_new,
848 	.imem = nv40_instmem_new,
849 	.mc = nv44_mc_new,
850 	.mmu = nv44_mmu_new,
851 	.pci = nv4c_pci_new,
852 	.therm = nv40_therm_new,
853 	.timer = nv41_timer_new,
854 	.volt = nv40_volt_new,
855 	.disp = nv04_disp_new,
856 	.dma = nv04_dma_new,
857 	.fifo = nv40_fifo_new,
858 	.gr = nv44_gr_new,
859 	.mpeg = nv44_mpeg_new,
860 	.pm = nv40_pm_new,
861 	.sw = nv10_sw_new,
862 };
863 
864 static const struct nvkm_device_chip
865 nv67_chipset = {
866 	.name = "C67",
867 	.bios = nvkm_bios_new,
868 	.bus = nv31_bus_new,
869 	.clk = nv40_clk_new,
870 	.devinit = nv1a_devinit_new,
871 	.fb = nv46_fb_new,
872 	.gpio = nv10_gpio_new,
873 	.i2c = nv04_i2c_new,
874 	.imem = nv40_instmem_new,
875 	.mc = nv44_mc_new,
876 	.mmu = nv44_mmu_new,
877 	.pci = nv4c_pci_new,
878 	.therm = nv40_therm_new,
879 	.timer = nv41_timer_new,
880 	.volt = nv40_volt_new,
881 	.disp = nv04_disp_new,
882 	.dma = nv04_dma_new,
883 	.fifo = nv40_fifo_new,
884 	.gr = nv44_gr_new,
885 	.mpeg = nv44_mpeg_new,
886 	.pm = nv40_pm_new,
887 	.sw = nv10_sw_new,
888 };
889 
890 static const struct nvkm_device_chip
891 nv68_chipset = {
892 	.name = "C68",
893 	.bios = nvkm_bios_new,
894 	.bus = nv31_bus_new,
895 	.clk = nv40_clk_new,
896 	.devinit = nv1a_devinit_new,
897 	.fb = nv46_fb_new,
898 	.gpio = nv10_gpio_new,
899 	.i2c = nv04_i2c_new,
900 	.imem = nv40_instmem_new,
901 	.mc = nv44_mc_new,
902 	.mmu = nv44_mmu_new,
903 	.pci = nv4c_pci_new,
904 	.therm = nv40_therm_new,
905 	.timer = nv41_timer_new,
906 	.volt = nv40_volt_new,
907 	.disp = nv04_disp_new,
908 	.dma = nv04_dma_new,
909 	.fifo = nv40_fifo_new,
910 	.gr = nv44_gr_new,
911 	.mpeg = nv44_mpeg_new,
912 	.pm = nv40_pm_new,
913 	.sw = nv10_sw_new,
914 };
915 
916 static const struct nvkm_device_chip
917 nv84_chipset = {
918 	.name = "G84",
919 	.bar = g84_bar_new,
920 	.bios = nvkm_bios_new,
921 	.bus = nv50_bus_new,
922 	.clk = g84_clk_new,
923 	.devinit = g84_devinit_new,
924 	.fb = g84_fb_new,
925 	.fuse = nv50_fuse_new,
926 	.gpio = nv50_gpio_new,
927 	.i2c = nv50_i2c_new,
928 	.imem = nv50_instmem_new,
929 	.mc = g84_mc_new,
930 	.mmu = nv50_mmu_new,
931 	.mxm = nv50_mxm_new,
932 	.pci = g84_pci_new,
933 	.therm = g84_therm_new,
934 	.timer = nv41_timer_new,
935 	.volt = nv40_volt_new,
936 	.bsp = g84_bsp_new,
937 	.cipher = g84_cipher_new,
938 	.disp = g84_disp_new,
939 	.dma = nv50_dma_new,
940 	.fifo = g84_fifo_new,
941 	.gr = g84_gr_new,
942 	.mpeg = g84_mpeg_new,
943 	.pm = g84_pm_new,
944 	.sw = nv50_sw_new,
945 	.vp = g84_vp_new,
946 };
947 
948 static const struct nvkm_device_chip
949 nv86_chipset = {
950 	.name = "G86",
951 	.bar = g84_bar_new,
952 	.bios = nvkm_bios_new,
953 	.bus = nv50_bus_new,
954 	.clk = g84_clk_new,
955 	.devinit = g84_devinit_new,
956 	.fb = g84_fb_new,
957 	.fuse = nv50_fuse_new,
958 	.gpio = nv50_gpio_new,
959 	.i2c = nv50_i2c_new,
960 	.imem = nv50_instmem_new,
961 	.mc = g84_mc_new,
962 	.mmu = nv50_mmu_new,
963 	.mxm = nv50_mxm_new,
964 	.pci = g84_pci_new,
965 	.therm = g84_therm_new,
966 	.timer = nv41_timer_new,
967 	.volt = nv40_volt_new,
968 	.bsp = g84_bsp_new,
969 	.cipher = g84_cipher_new,
970 	.disp = g84_disp_new,
971 	.dma = nv50_dma_new,
972 	.fifo = g84_fifo_new,
973 	.gr = g84_gr_new,
974 	.mpeg = g84_mpeg_new,
975 	.pm = g84_pm_new,
976 	.sw = nv50_sw_new,
977 	.vp = g84_vp_new,
978 };
979 
980 static const struct nvkm_device_chip
981 nv92_chipset = {
982 	.name = "G92",
983 	.bar = g84_bar_new,
984 	.bios = nvkm_bios_new,
985 	.bus = nv50_bus_new,
986 	.clk = g84_clk_new,
987 	.devinit = g84_devinit_new,
988 	.fb = g84_fb_new,
989 	.fuse = nv50_fuse_new,
990 	.gpio = nv50_gpio_new,
991 	.i2c = nv50_i2c_new,
992 	.imem = nv50_instmem_new,
993 	.mc = g84_mc_new,
994 	.mmu = nv50_mmu_new,
995 	.mxm = nv50_mxm_new,
996 	.pci = g84_pci_new,
997 	.therm = g84_therm_new,
998 	.timer = nv41_timer_new,
999 	.volt = nv40_volt_new,
1000 	.bsp = g84_bsp_new,
1001 	.cipher = g84_cipher_new,
1002 	.disp = g84_disp_new,
1003 	.dma = nv50_dma_new,
1004 	.fifo = g84_fifo_new,
1005 	.gr = g84_gr_new,
1006 	.mpeg = g84_mpeg_new,
1007 	.pm = g84_pm_new,
1008 	.sw = nv50_sw_new,
1009 	.vp = g84_vp_new,
1010 };
1011 
1012 static const struct nvkm_device_chip
1013 nv94_chipset = {
1014 	.name = "G94",
1015 	.bar = g84_bar_new,
1016 	.bios = nvkm_bios_new,
1017 	.bus = g94_bus_new,
1018 	.clk = g84_clk_new,
1019 	.devinit = g84_devinit_new,
1020 	.fb = g84_fb_new,
1021 	.fuse = nv50_fuse_new,
1022 	.gpio = g94_gpio_new,
1023 	.i2c = g94_i2c_new,
1024 	.imem = nv50_instmem_new,
1025 	.mc = g84_mc_new,
1026 	.mmu = nv50_mmu_new,
1027 	.mxm = nv50_mxm_new,
1028 	.pci = g94_pci_new,
1029 	.therm = g84_therm_new,
1030 	.timer = nv41_timer_new,
1031 	.volt = nv40_volt_new,
1032 	.bsp = g84_bsp_new,
1033 	.cipher = g84_cipher_new,
1034 	.disp = g94_disp_new,
1035 	.dma = nv50_dma_new,
1036 	.fifo = g84_fifo_new,
1037 	.gr = g84_gr_new,
1038 	.mpeg = g84_mpeg_new,
1039 	.pm = g84_pm_new,
1040 	.sw = nv50_sw_new,
1041 	.vp = g84_vp_new,
1042 };
1043 
1044 static const struct nvkm_device_chip
1045 nv96_chipset = {
1046 	.name = "G96",
1047 	.bar = g84_bar_new,
1048 	.bios = nvkm_bios_new,
1049 	.bus = g94_bus_new,
1050 	.clk = g84_clk_new,
1051 	.devinit = g84_devinit_new,
1052 	.fb = g84_fb_new,
1053 	.fuse = nv50_fuse_new,
1054 	.gpio = g94_gpio_new,
1055 	.i2c = g94_i2c_new,
1056 	.imem = nv50_instmem_new,
1057 	.mc = g84_mc_new,
1058 	.mmu = nv50_mmu_new,
1059 	.mxm = nv50_mxm_new,
1060 	.pci = g94_pci_new,
1061 	.therm = g84_therm_new,
1062 	.timer = nv41_timer_new,
1063 	.volt = nv40_volt_new,
1064 	.bsp = g84_bsp_new,
1065 	.cipher = g84_cipher_new,
1066 	.disp = g94_disp_new,
1067 	.dma = nv50_dma_new,
1068 	.fifo = g84_fifo_new,
1069 	.gr = g84_gr_new,
1070 	.mpeg = g84_mpeg_new,
1071 	.pm = g84_pm_new,
1072 	.sw = nv50_sw_new,
1073 	.vp = g84_vp_new,
1074 };
1075 
1076 static const struct nvkm_device_chip
1077 nv98_chipset = {
1078 	.name = "G98",
1079 	.bar = g84_bar_new,
1080 	.bios = nvkm_bios_new,
1081 	.bus = g94_bus_new,
1082 	.clk = g84_clk_new,
1083 	.devinit = g98_devinit_new,
1084 	.fb = g84_fb_new,
1085 	.fuse = nv50_fuse_new,
1086 	.gpio = g94_gpio_new,
1087 	.i2c = g94_i2c_new,
1088 	.imem = nv50_instmem_new,
1089 	.mc = g98_mc_new,
1090 	.mmu = nv50_mmu_new,
1091 	.mxm = nv50_mxm_new,
1092 	.pci = g94_pci_new,
1093 	.therm = g84_therm_new,
1094 	.timer = nv41_timer_new,
1095 	.volt = nv40_volt_new,
1096 	.disp = g94_disp_new,
1097 	.dma = nv50_dma_new,
1098 	.fifo = g84_fifo_new,
1099 	.gr = g84_gr_new,
1100 	.mspdec = g98_mspdec_new,
1101 	.msppp = g98_msppp_new,
1102 	.msvld = g98_msvld_new,
1103 	.pm = g84_pm_new,
1104 	.sec = g98_sec_new,
1105 	.sw = nv50_sw_new,
1106 };
1107 
1108 static const struct nvkm_device_chip
1109 nva0_chipset = {
1110 	.name = "GT200",
1111 	.bar = g84_bar_new,
1112 	.bios = nvkm_bios_new,
1113 	.bus = g94_bus_new,
1114 	.clk = g84_clk_new,
1115 	.devinit = g84_devinit_new,
1116 	.fb = g84_fb_new,
1117 	.fuse = nv50_fuse_new,
1118 	.gpio = g94_gpio_new,
1119 	.i2c = nv50_i2c_new,
1120 	.imem = nv50_instmem_new,
1121 	.mc = g84_mc_new,
1122 	.mmu = nv50_mmu_new,
1123 	.mxm = nv50_mxm_new,
1124 	.pci = g94_pci_new,
1125 	.therm = g84_therm_new,
1126 	.timer = nv41_timer_new,
1127 	.volt = nv40_volt_new,
1128 	.bsp = g84_bsp_new,
1129 	.cipher = g84_cipher_new,
1130 	.disp = gt200_disp_new,
1131 	.dma = nv50_dma_new,
1132 	.fifo = g84_fifo_new,
1133 	.gr = gt200_gr_new,
1134 	.mpeg = g84_mpeg_new,
1135 	.pm = gt200_pm_new,
1136 	.sw = nv50_sw_new,
1137 	.vp = g84_vp_new,
1138 };
1139 
1140 static const struct nvkm_device_chip
1141 nva3_chipset = {
1142 	.name = "GT215",
1143 	.bar = g84_bar_new,
1144 	.bios = nvkm_bios_new,
1145 	.bus = g94_bus_new,
1146 	.clk = gt215_clk_new,
1147 	.devinit = gt215_devinit_new,
1148 	.fb = gt215_fb_new,
1149 	.fuse = nv50_fuse_new,
1150 	.gpio = g94_gpio_new,
1151 	.i2c = g94_i2c_new,
1152 	.imem = nv50_instmem_new,
1153 	.mc = gt215_mc_new,
1154 	.mmu = nv50_mmu_new,
1155 	.mxm = nv50_mxm_new,
1156 	.pci = g94_pci_new,
1157 	.pmu = gt215_pmu_new,
1158 	.therm = gt215_therm_new,
1159 	.timer = nv41_timer_new,
1160 	.volt = nv40_volt_new,
1161 	.ce[0] = gt215_ce_new,
1162 	.disp = gt215_disp_new,
1163 	.dma = nv50_dma_new,
1164 	.fifo = g84_fifo_new,
1165 	.gr = gt215_gr_new,
1166 	.mpeg = g84_mpeg_new,
1167 	.mspdec = gt215_mspdec_new,
1168 	.msppp = gt215_msppp_new,
1169 	.msvld = gt215_msvld_new,
1170 	.pm = gt215_pm_new,
1171 	.sw = nv50_sw_new,
1172 };
1173 
1174 static const struct nvkm_device_chip
1175 nva5_chipset = {
1176 	.name = "GT216",
1177 	.bar = g84_bar_new,
1178 	.bios = nvkm_bios_new,
1179 	.bus = g94_bus_new,
1180 	.clk = gt215_clk_new,
1181 	.devinit = gt215_devinit_new,
1182 	.fb = gt215_fb_new,
1183 	.fuse = nv50_fuse_new,
1184 	.gpio = g94_gpio_new,
1185 	.i2c = g94_i2c_new,
1186 	.imem = nv50_instmem_new,
1187 	.mc = gt215_mc_new,
1188 	.mmu = nv50_mmu_new,
1189 	.mxm = nv50_mxm_new,
1190 	.pci = g94_pci_new,
1191 	.pmu = gt215_pmu_new,
1192 	.therm = gt215_therm_new,
1193 	.timer = nv41_timer_new,
1194 	.volt = nv40_volt_new,
1195 	.ce[0] = gt215_ce_new,
1196 	.disp = gt215_disp_new,
1197 	.dma = nv50_dma_new,
1198 	.fifo = g84_fifo_new,
1199 	.gr = gt215_gr_new,
1200 	.mspdec = gt215_mspdec_new,
1201 	.msppp = gt215_msppp_new,
1202 	.msvld = gt215_msvld_new,
1203 	.pm = gt215_pm_new,
1204 	.sw = nv50_sw_new,
1205 };
1206 
1207 static const struct nvkm_device_chip
1208 nva8_chipset = {
1209 	.name = "GT218",
1210 	.bar = g84_bar_new,
1211 	.bios = nvkm_bios_new,
1212 	.bus = g94_bus_new,
1213 	.clk = gt215_clk_new,
1214 	.devinit = gt215_devinit_new,
1215 	.fb = gt215_fb_new,
1216 	.fuse = nv50_fuse_new,
1217 	.gpio = g94_gpio_new,
1218 	.i2c = g94_i2c_new,
1219 	.imem = nv50_instmem_new,
1220 	.mc = gt215_mc_new,
1221 	.mmu = nv50_mmu_new,
1222 	.mxm = nv50_mxm_new,
1223 	.pci = g94_pci_new,
1224 	.pmu = gt215_pmu_new,
1225 	.therm = gt215_therm_new,
1226 	.timer = nv41_timer_new,
1227 	.volt = nv40_volt_new,
1228 	.ce[0] = gt215_ce_new,
1229 	.disp = gt215_disp_new,
1230 	.dma = nv50_dma_new,
1231 	.fifo = g84_fifo_new,
1232 	.gr = gt215_gr_new,
1233 	.mspdec = gt215_mspdec_new,
1234 	.msppp = gt215_msppp_new,
1235 	.msvld = gt215_msvld_new,
1236 	.pm = gt215_pm_new,
1237 	.sw = nv50_sw_new,
1238 };
1239 
1240 static const struct nvkm_device_chip
1241 nvaa_chipset = {
1242 	.name = "MCP77/MCP78",
1243 	.bar = g84_bar_new,
1244 	.bios = nvkm_bios_new,
1245 	.bus = g94_bus_new,
1246 	.clk = mcp77_clk_new,
1247 	.devinit = g98_devinit_new,
1248 	.fb = mcp77_fb_new,
1249 	.fuse = nv50_fuse_new,
1250 	.gpio = g94_gpio_new,
1251 	.i2c = g94_i2c_new,
1252 	.imem = nv50_instmem_new,
1253 	.mc = g98_mc_new,
1254 	.mmu = nv50_mmu_new,
1255 	.mxm = nv50_mxm_new,
1256 	.pci = g94_pci_new,
1257 	.therm = g84_therm_new,
1258 	.timer = nv41_timer_new,
1259 	.volt = nv40_volt_new,
1260 	.disp = g94_disp_new,
1261 	.dma = nv50_dma_new,
1262 	.fifo = g84_fifo_new,
1263 	.gr = gt200_gr_new,
1264 	.mspdec = g98_mspdec_new,
1265 	.msppp = g98_msppp_new,
1266 	.msvld = g98_msvld_new,
1267 	.pm = g84_pm_new,
1268 	.sec = g98_sec_new,
1269 	.sw = nv50_sw_new,
1270 };
1271 
1272 static const struct nvkm_device_chip
1273 nvac_chipset = {
1274 	.name = "MCP79/MCP7A",
1275 	.bar = g84_bar_new,
1276 	.bios = nvkm_bios_new,
1277 	.bus = g94_bus_new,
1278 	.clk = mcp77_clk_new,
1279 	.devinit = g98_devinit_new,
1280 	.fb = mcp77_fb_new,
1281 	.fuse = nv50_fuse_new,
1282 	.gpio = g94_gpio_new,
1283 	.i2c = g94_i2c_new,
1284 	.imem = nv50_instmem_new,
1285 	.mc = g98_mc_new,
1286 	.mmu = nv50_mmu_new,
1287 	.mxm = nv50_mxm_new,
1288 	.pci = g94_pci_new,
1289 	.therm = g84_therm_new,
1290 	.timer = nv41_timer_new,
1291 	.volt = nv40_volt_new,
1292 	.disp = g94_disp_new,
1293 	.dma = nv50_dma_new,
1294 	.fifo = g84_fifo_new,
1295 	.gr = mcp79_gr_new,
1296 	.mspdec = g98_mspdec_new,
1297 	.msppp = g98_msppp_new,
1298 	.msvld = g98_msvld_new,
1299 	.pm = g84_pm_new,
1300 	.sec = g98_sec_new,
1301 	.sw = nv50_sw_new,
1302 };
1303 
1304 static const struct nvkm_device_chip
1305 nvaf_chipset = {
1306 	.name = "MCP89",
1307 	.bar = g84_bar_new,
1308 	.bios = nvkm_bios_new,
1309 	.bus = g94_bus_new,
1310 	.clk = gt215_clk_new,
1311 	.devinit = mcp89_devinit_new,
1312 	.fb = mcp89_fb_new,
1313 	.fuse = nv50_fuse_new,
1314 	.gpio = g94_gpio_new,
1315 	.i2c = g94_i2c_new,
1316 	.imem = nv50_instmem_new,
1317 	.mc = gt215_mc_new,
1318 	.mmu = nv50_mmu_new,
1319 	.mxm = nv50_mxm_new,
1320 	.pci = g94_pci_new,
1321 	.pmu = gt215_pmu_new,
1322 	.therm = gt215_therm_new,
1323 	.timer = nv41_timer_new,
1324 	.volt = nv40_volt_new,
1325 	.ce[0] = gt215_ce_new,
1326 	.disp = gt215_disp_new,
1327 	.dma = nv50_dma_new,
1328 	.fifo = g84_fifo_new,
1329 	.gr = mcp89_gr_new,
1330 	.mspdec = gt215_mspdec_new,
1331 	.msppp = gt215_msppp_new,
1332 	.msvld = mcp89_msvld_new,
1333 	.pm = gt215_pm_new,
1334 	.sw = nv50_sw_new,
1335 };
1336 
1337 static const struct nvkm_device_chip
1338 nvc0_chipset = {
1339 	.name = "GF100",
1340 	.bar = gf100_bar_new,
1341 	.bios = nvkm_bios_new,
1342 	.bus = gf100_bus_new,
1343 	.clk = gf100_clk_new,
1344 	.devinit = gf100_devinit_new,
1345 	.fb = gf100_fb_new,
1346 	.fuse = gf100_fuse_new,
1347 	.gpio = g94_gpio_new,
1348 	.i2c = g94_i2c_new,
1349 	.ibus = gf100_ibus_new,
1350 	.iccsense = gf100_iccsense_new,
1351 	.imem = nv50_instmem_new,
1352 	.ltc = gf100_ltc_new,
1353 	.mc = gf100_mc_new,
1354 	.mmu = gf100_mmu_new,
1355 	.mxm = nv50_mxm_new,
1356 	.pci = gf100_pci_new,
1357 	.pmu = gf100_pmu_new,
1358 	.therm = gt215_therm_new,
1359 	.timer = nv41_timer_new,
1360 	.volt = nv40_volt_new,
1361 	.ce[0] = gf100_ce_new,
1362 	.ce[1] = gf100_ce_new,
1363 	.disp = gt215_disp_new,
1364 	.dma = gf100_dma_new,
1365 	.fifo = gf100_fifo_new,
1366 	.gr = gf100_gr_new,
1367 	.mspdec = gf100_mspdec_new,
1368 	.msppp = gf100_msppp_new,
1369 	.msvld = gf100_msvld_new,
1370 	.pm = gf100_pm_new,
1371 	.sw = gf100_sw_new,
1372 };
1373 
1374 static const struct nvkm_device_chip
1375 nvc1_chipset = {
1376 	.name = "GF108",
1377 	.bar = gf100_bar_new,
1378 	.bios = nvkm_bios_new,
1379 	.bus = gf100_bus_new,
1380 	.clk = gf100_clk_new,
1381 	.devinit = gf100_devinit_new,
1382 	.fb = gf100_fb_new,
1383 	.fuse = gf100_fuse_new,
1384 	.gpio = g94_gpio_new,
1385 	.i2c = g94_i2c_new,
1386 	.ibus = gf100_ibus_new,
1387 	.iccsense = gf100_iccsense_new,
1388 	.imem = nv50_instmem_new,
1389 	.ltc = gf100_ltc_new,
1390 	.mc = gf100_mc_new,
1391 	.mmu = gf100_mmu_new,
1392 	.mxm = nv50_mxm_new,
1393 	.pci = gf106_pci_new,
1394 	.pmu = gf100_pmu_new,
1395 	.therm = gt215_therm_new,
1396 	.timer = nv41_timer_new,
1397 	.volt = nv40_volt_new,
1398 	.ce[0] = gf100_ce_new,
1399 	.disp = gt215_disp_new,
1400 	.dma = gf100_dma_new,
1401 	.fifo = gf100_fifo_new,
1402 	.gr = gf108_gr_new,
1403 	.mspdec = gf100_mspdec_new,
1404 	.msppp = gf100_msppp_new,
1405 	.msvld = gf100_msvld_new,
1406 	.pm = gf108_pm_new,
1407 	.sw = gf100_sw_new,
1408 };
1409 
1410 static const struct nvkm_device_chip
1411 nvc3_chipset = {
1412 	.name = "GF106",
1413 	.bar = gf100_bar_new,
1414 	.bios = nvkm_bios_new,
1415 	.bus = gf100_bus_new,
1416 	.clk = gf100_clk_new,
1417 	.devinit = gf100_devinit_new,
1418 	.fb = gf100_fb_new,
1419 	.fuse = gf100_fuse_new,
1420 	.gpio = g94_gpio_new,
1421 	.i2c = g94_i2c_new,
1422 	.ibus = gf100_ibus_new,
1423 	.iccsense = gf100_iccsense_new,
1424 	.imem = nv50_instmem_new,
1425 	.ltc = gf100_ltc_new,
1426 	.mc = gf100_mc_new,
1427 	.mmu = gf100_mmu_new,
1428 	.mxm = nv50_mxm_new,
1429 	.pci = gf106_pci_new,
1430 	.pmu = gf100_pmu_new,
1431 	.therm = gt215_therm_new,
1432 	.timer = nv41_timer_new,
1433 	.volt = nv40_volt_new,
1434 	.ce[0] = gf100_ce_new,
1435 	.disp = gt215_disp_new,
1436 	.dma = gf100_dma_new,
1437 	.fifo = gf100_fifo_new,
1438 	.gr = gf104_gr_new,
1439 	.mspdec = gf100_mspdec_new,
1440 	.msppp = gf100_msppp_new,
1441 	.msvld = gf100_msvld_new,
1442 	.pm = gf100_pm_new,
1443 	.sw = gf100_sw_new,
1444 };
1445 
1446 static const struct nvkm_device_chip
1447 nvc4_chipset = {
1448 	.name = "GF104",
1449 	.bar = gf100_bar_new,
1450 	.bios = nvkm_bios_new,
1451 	.bus = gf100_bus_new,
1452 	.clk = gf100_clk_new,
1453 	.devinit = gf100_devinit_new,
1454 	.fb = gf100_fb_new,
1455 	.fuse = gf100_fuse_new,
1456 	.gpio = g94_gpio_new,
1457 	.i2c = g94_i2c_new,
1458 	.ibus = gf100_ibus_new,
1459 	.iccsense = gf100_iccsense_new,
1460 	.imem = nv50_instmem_new,
1461 	.ltc = gf100_ltc_new,
1462 	.mc = gf100_mc_new,
1463 	.mmu = gf100_mmu_new,
1464 	.mxm = nv50_mxm_new,
1465 	.pci = gf100_pci_new,
1466 	.pmu = gf100_pmu_new,
1467 	.therm = gt215_therm_new,
1468 	.timer = nv41_timer_new,
1469 	.volt = nv40_volt_new,
1470 	.ce[0] = gf100_ce_new,
1471 	.ce[1] = gf100_ce_new,
1472 	.disp = gt215_disp_new,
1473 	.dma = gf100_dma_new,
1474 	.fifo = gf100_fifo_new,
1475 	.gr = gf104_gr_new,
1476 	.mspdec = gf100_mspdec_new,
1477 	.msppp = gf100_msppp_new,
1478 	.msvld = gf100_msvld_new,
1479 	.pm = gf100_pm_new,
1480 	.sw = gf100_sw_new,
1481 };
1482 
1483 static const struct nvkm_device_chip
1484 nvc8_chipset = {
1485 	.name = "GF110",
1486 	.bar = gf100_bar_new,
1487 	.bios = nvkm_bios_new,
1488 	.bus = gf100_bus_new,
1489 	.clk = gf100_clk_new,
1490 	.devinit = gf100_devinit_new,
1491 	.fb = gf100_fb_new,
1492 	.fuse = gf100_fuse_new,
1493 	.gpio = g94_gpio_new,
1494 	.i2c = g94_i2c_new,
1495 	.ibus = gf100_ibus_new,
1496 	.iccsense = gf100_iccsense_new,
1497 	.imem = nv50_instmem_new,
1498 	.ltc = gf100_ltc_new,
1499 	.mc = gf100_mc_new,
1500 	.mmu = gf100_mmu_new,
1501 	.mxm = nv50_mxm_new,
1502 	.pci = gf100_pci_new,
1503 	.pmu = gf100_pmu_new,
1504 	.therm = gt215_therm_new,
1505 	.timer = nv41_timer_new,
1506 	.volt = nv40_volt_new,
1507 	.ce[0] = gf100_ce_new,
1508 	.ce[1] = gf100_ce_new,
1509 	.disp = gt215_disp_new,
1510 	.dma = gf100_dma_new,
1511 	.fifo = gf100_fifo_new,
1512 	.gr = gf110_gr_new,
1513 	.mspdec = gf100_mspdec_new,
1514 	.msppp = gf100_msppp_new,
1515 	.msvld = gf100_msvld_new,
1516 	.pm = gf100_pm_new,
1517 	.sw = gf100_sw_new,
1518 };
1519 
1520 static const struct nvkm_device_chip
1521 nvce_chipset = {
1522 	.name = "GF114",
1523 	.bar = gf100_bar_new,
1524 	.bios = nvkm_bios_new,
1525 	.bus = gf100_bus_new,
1526 	.clk = gf100_clk_new,
1527 	.devinit = gf100_devinit_new,
1528 	.fb = gf100_fb_new,
1529 	.fuse = gf100_fuse_new,
1530 	.gpio = g94_gpio_new,
1531 	.i2c = g94_i2c_new,
1532 	.ibus = gf100_ibus_new,
1533 	.iccsense = gf100_iccsense_new,
1534 	.imem = nv50_instmem_new,
1535 	.ltc = gf100_ltc_new,
1536 	.mc = gf100_mc_new,
1537 	.mmu = gf100_mmu_new,
1538 	.mxm = nv50_mxm_new,
1539 	.pci = gf100_pci_new,
1540 	.pmu = gf100_pmu_new,
1541 	.therm = gt215_therm_new,
1542 	.timer = nv41_timer_new,
1543 	.volt = nv40_volt_new,
1544 	.ce[0] = gf100_ce_new,
1545 	.ce[1] = gf100_ce_new,
1546 	.disp = gt215_disp_new,
1547 	.dma = gf100_dma_new,
1548 	.fifo = gf100_fifo_new,
1549 	.gr = gf104_gr_new,
1550 	.mspdec = gf100_mspdec_new,
1551 	.msppp = gf100_msppp_new,
1552 	.msvld = gf100_msvld_new,
1553 	.pm = gf100_pm_new,
1554 	.sw = gf100_sw_new,
1555 };
1556 
1557 static const struct nvkm_device_chip
1558 nvcf_chipset = {
1559 	.name = "GF116",
1560 	.bar = gf100_bar_new,
1561 	.bios = nvkm_bios_new,
1562 	.bus = gf100_bus_new,
1563 	.clk = gf100_clk_new,
1564 	.devinit = gf100_devinit_new,
1565 	.fb = gf100_fb_new,
1566 	.fuse = gf100_fuse_new,
1567 	.gpio = g94_gpio_new,
1568 	.i2c = g94_i2c_new,
1569 	.ibus = gf100_ibus_new,
1570 	.iccsense = gf100_iccsense_new,
1571 	.imem = nv50_instmem_new,
1572 	.ltc = gf100_ltc_new,
1573 	.mc = gf100_mc_new,
1574 	.mmu = gf100_mmu_new,
1575 	.mxm = nv50_mxm_new,
1576 	.pci = gf106_pci_new,
1577 	.pmu = gf100_pmu_new,
1578 	.therm = gt215_therm_new,
1579 	.timer = nv41_timer_new,
1580 	.volt = nv40_volt_new,
1581 	.ce[0] = gf100_ce_new,
1582 	.disp = gt215_disp_new,
1583 	.dma = gf100_dma_new,
1584 	.fifo = gf100_fifo_new,
1585 	.gr = gf104_gr_new,
1586 	.mspdec = gf100_mspdec_new,
1587 	.msppp = gf100_msppp_new,
1588 	.msvld = gf100_msvld_new,
1589 	.pm = gf100_pm_new,
1590 	.sw = gf100_sw_new,
1591 };
1592 
1593 static const struct nvkm_device_chip
1594 nvd7_chipset = {
1595 	.name = "GF117",
1596 	.bar = gf100_bar_new,
1597 	.bios = nvkm_bios_new,
1598 	.bus = gf100_bus_new,
1599 	.clk = gf100_clk_new,
1600 	.devinit = gf100_devinit_new,
1601 	.fb = gf100_fb_new,
1602 	.fuse = gf100_fuse_new,
1603 	.gpio = gf119_gpio_new,
1604 	.i2c = gf117_i2c_new,
1605 	.ibus = gf117_ibus_new,
1606 	.iccsense = gf100_iccsense_new,
1607 	.imem = nv50_instmem_new,
1608 	.ltc = gf100_ltc_new,
1609 	.mc = gf100_mc_new,
1610 	.mmu = gf100_mmu_new,
1611 	.mxm = nv50_mxm_new,
1612 	.pci = gf106_pci_new,
1613 	.therm = gf119_therm_new,
1614 	.timer = nv41_timer_new,
1615 	.ce[0] = gf100_ce_new,
1616 	.disp = gf119_disp_new,
1617 	.dma = gf119_dma_new,
1618 	.fifo = gf100_fifo_new,
1619 	.gr = gf117_gr_new,
1620 	.mspdec = gf100_mspdec_new,
1621 	.msppp = gf100_msppp_new,
1622 	.msvld = gf100_msvld_new,
1623 	.pm = gf117_pm_new,
1624 	.sw = gf100_sw_new,
1625 };
1626 
1627 static const struct nvkm_device_chip
1628 nvd9_chipset = {
1629 	.name = "GF119",
1630 	.bar = gf100_bar_new,
1631 	.bios = nvkm_bios_new,
1632 	.bus = gf100_bus_new,
1633 	.clk = gf100_clk_new,
1634 	.devinit = gf100_devinit_new,
1635 	.fb = gf100_fb_new,
1636 	.fuse = gf100_fuse_new,
1637 	.gpio = gf119_gpio_new,
1638 	.i2c = gf119_i2c_new,
1639 	.ibus = gf117_ibus_new,
1640 	.iccsense = gf100_iccsense_new,
1641 	.imem = nv50_instmem_new,
1642 	.ltc = gf100_ltc_new,
1643 	.mc = gf100_mc_new,
1644 	.mmu = gf100_mmu_new,
1645 	.mxm = nv50_mxm_new,
1646 	.pci = gf106_pci_new,
1647 	.pmu = gf119_pmu_new,
1648 	.therm = gf119_therm_new,
1649 	.timer = nv41_timer_new,
1650 	.volt = nv40_volt_new,
1651 	.ce[0] = gf100_ce_new,
1652 	.disp = gf119_disp_new,
1653 	.dma = gf119_dma_new,
1654 	.fifo = gf100_fifo_new,
1655 	.gr = gf119_gr_new,
1656 	.mspdec = gf100_mspdec_new,
1657 	.msppp = gf100_msppp_new,
1658 	.msvld = gf100_msvld_new,
1659 	.pm = gf117_pm_new,
1660 	.sw = gf100_sw_new,
1661 };
1662 
1663 static const struct nvkm_device_chip
1664 nve4_chipset = {
1665 	.name = "GK104",
1666 	.bar = gf100_bar_new,
1667 	.bios = nvkm_bios_new,
1668 	.bus = gf100_bus_new,
1669 	.clk = gk104_clk_new,
1670 	.devinit = gf100_devinit_new,
1671 	.fb = gk104_fb_new,
1672 	.fuse = gf100_fuse_new,
1673 	.gpio = gk104_gpio_new,
1674 	.i2c = gk104_i2c_new,
1675 	.ibus = gk104_ibus_new,
1676 	.iccsense = gf100_iccsense_new,
1677 	.imem = nv50_instmem_new,
1678 	.ltc = gk104_ltc_new,
1679 	.mc = gk104_mc_new,
1680 	.mmu = gf100_mmu_new,
1681 	.mxm = nv50_mxm_new,
1682 	.pci = gk104_pci_new,
1683 	.pmu = gk104_pmu_new,
1684 	.therm = gf119_therm_new,
1685 	.timer = nv41_timer_new,
1686 	.top = gk104_top_new,
1687 	.volt = gk104_volt_new,
1688 	.ce[0] = gk104_ce_new,
1689 	.ce[1] = gk104_ce_new,
1690 	.ce[2] = gk104_ce_new,
1691 	.disp = gk104_disp_new,
1692 	.dma = gf119_dma_new,
1693 	.fifo = gk104_fifo_new,
1694 	.gr = gk104_gr_new,
1695 	.mspdec = gk104_mspdec_new,
1696 	.msppp = gf100_msppp_new,
1697 	.msvld = gk104_msvld_new,
1698 	.pm = gk104_pm_new,
1699 	.sw = gf100_sw_new,
1700 };
1701 
1702 static const struct nvkm_device_chip
1703 nve6_chipset = {
1704 	.name = "GK106",
1705 	.bar = gf100_bar_new,
1706 	.bios = nvkm_bios_new,
1707 	.bus = gf100_bus_new,
1708 	.clk = gk104_clk_new,
1709 	.devinit = gf100_devinit_new,
1710 	.fb = gk104_fb_new,
1711 	.fuse = gf100_fuse_new,
1712 	.gpio = gk104_gpio_new,
1713 	.i2c = gk104_i2c_new,
1714 	.ibus = gk104_ibus_new,
1715 	.iccsense = gf100_iccsense_new,
1716 	.imem = nv50_instmem_new,
1717 	.ltc = gk104_ltc_new,
1718 	.mc = gk104_mc_new,
1719 	.mmu = gf100_mmu_new,
1720 	.mxm = nv50_mxm_new,
1721 	.pci = gk104_pci_new,
1722 	.pmu = gk104_pmu_new,
1723 	.therm = gf119_therm_new,
1724 	.timer = nv41_timer_new,
1725 	.top = gk104_top_new,
1726 	.volt = gk104_volt_new,
1727 	.ce[0] = gk104_ce_new,
1728 	.ce[1] = gk104_ce_new,
1729 	.ce[2] = gk104_ce_new,
1730 	.disp = gk104_disp_new,
1731 	.dma = gf119_dma_new,
1732 	.fifo = gk104_fifo_new,
1733 	.gr = gk104_gr_new,
1734 	.mspdec = gk104_mspdec_new,
1735 	.msppp = gf100_msppp_new,
1736 	.msvld = gk104_msvld_new,
1737 	.pm = gk104_pm_new,
1738 	.sw = gf100_sw_new,
1739 };
1740 
1741 static const struct nvkm_device_chip
1742 nve7_chipset = {
1743 	.name = "GK107",
1744 	.bar = gf100_bar_new,
1745 	.bios = nvkm_bios_new,
1746 	.bus = gf100_bus_new,
1747 	.clk = gk104_clk_new,
1748 	.devinit = gf100_devinit_new,
1749 	.fb = gk104_fb_new,
1750 	.fuse = gf100_fuse_new,
1751 	.gpio = gk104_gpio_new,
1752 	.i2c = gk104_i2c_new,
1753 	.ibus = gk104_ibus_new,
1754 	.iccsense = gf100_iccsense_new,
1755 	.imem = nv50_instmem_new,
1756 	.ltc = gk104_ltc_new,
1757 	.mc = gk104_mc_new,
1758 	.mmu = gf100_mmu_new,
1759 	.mxm = nv50_mxm_new,
1760 	.pci = gk104_pci_new,
1761 	.pmu = gk104_pmu_new,
1762 	.therm = gf119_therm_new,
1763 	.timer = nv41_timer_new,
1764 	.top = gk104_top_new,
1765 	.volt = gk104_volt_new,
1766 	.ce[0] = gk104_ce_new,
1767 	.ce[1] = gk104_ce_new,
1768 	.ce[2] = gk104_ce_new,
1769 	.disp = gk104_disp_new,
1770 	.dma = gf119_dma_new,
1771 	.fifo = gk104_fifo_new,
1772 	.gr = gk104_gr_new,
1773 	.mspdec = gk104_mspdec_new,
1774 	.msppp = gf100_msppp_new,
1775 	.msvld = gk104_msvld_new,
1776 	.pm = gk104_pm_new,
1777 	.sw = gf100_sw_new,
1778 };
1779 
1780 static const struct nvkm_device_chip
1781 nvea_chipset = {
1782 	.name = "GK20A",
1783 	.bar = gk20a_bar_new,
1784 	.bus = gf100_bus_new,
1785 	.clk = gk20a_clk_new,
1786 	.fb = gk20a_fb_new,
1787 	.fuse = gf100_fuse_new,
1788 	.ibus = gk20a_ibus_new,
1789 	.imem = gk20a_instmem_new,
1790 	.ltc = gk104_ltc_new,
1791 	.mc = gk20a_mc_new,
1792 	.mmu = gf100_mmu_new,
1793 	.pmu = gk20a_pmu_new,
1794 	.timer = gk20a_timer_new,
1795 	.top = gk104_top_new,
1796 	.volt = gk20a_volt_new,
1797 	.ce[2] = gk104_ce_new,
1798 	.dma = gf119_dma_new,
1799 	.fifo = gk20a_fifo_new,
1800 	.gr = gk20a_gr_new,
1801 	.pm = gk104_pm_new,
1802 	.sw = gf100_sw_new,
1803 };
1804 
1805 static const struct nvkm_device_chip
1806 nvf0_chipset = {
1807 	.name = "GK110",
1808 	.bar = gf100_bar_new,
1809 	.bios = nvkm_bios_new,
1810 	.bus = gf100_bus_new,
1811 	.clk = gk104_clk_new,
1812 	.devinit = gf100_devinit_new,
1813 	.fb = gk104_fb_new,
1814 	.fuse = gf100_fuse_new,
1815 	.gpio = gk104_gpio_new,
1816 	.i2c = gk104_i2c_new,
1817 	.ibus = gk104_ibus_new,
1818 	.iccsense = gf100_iccsense_new,
1819 	.imem = nv50_instmem_new,
1820 	.ltc = gk104_ltc_new,
1821 	.mc = gk104_mc_new,
1822 	.mmu = gf100_mmu_new,
1823 	.mxm = nv50_mxm_new,
1824 	.pci = gk104_pci_new,
1825 	.pmu = gk110_pmu_new,
1826 	.therm = gf119_therm_new,
1827 	.timer = nv41_timer_new,
1828 	.top = gk104_top_new,
1829 	.volt = gk104_volt_new,
1830 	.ce[0] = gk104_ce_new,
1831 	.ce[1] = gk104_ce_new,
1832 	.ce[2] = gk104_ce_new,
1833 	.disp = gk110_disp_new,
1834 	.dma = gf119_dma_new,
1835 	.fifo = gk110_fifo_new,
1836 	.gr = gk110_gr_new,
1837 	.mspdec = gk104_mspdec_new,
1838 	.msppp = gf100_msppp_new,
1839 	.msvld = gk104_msvld_new,
1840 	.sw = gf100_sw_new,
1841 };
1842 
1843 static const struct nvkm_device_chip
1844 nvf1_chipset = {
1845 	.name = "GK110B",
1846 	.bar = gf100_bar_new,
1847 	.bios = nvkm_bios_new,
1848 	.bus = gf100_bus_new,
1849 	.clk = gk104_clk_new,
1850 	.devinit = gf100_devinit_new,
1851 	.fb = gk104_fb_new,
1852 	.fuse = gf100_fuse_new,
1853 	.gpio = gk104_gpio_new,
1854 	.i2c = gf119_i2c_new,
1855 	.ibus = gk104_ibus_new,
1856 	.iccsense = gf100_iccsense_new,
1857 	.imem = nv50_instmem_new,
1858 	.ltc = gk104_ltc_new,
1859 	.mc = gk104_mc_new,
1860 	.mmu = gf100_mmu_new,
1861 	.mxm = nv50_mxm_new,
1862 	.pci = gk104_pci_new,
1863 	.pmu = gk110_pmu_new,
1864 	.therm = gf119_therm_new,
1865 	.timer = nv41_timer_new,
1866 	.top = gk104_top_new,
1867 	.volt = gk104_volt_new,
1868 	.ce[0] = gk104_ce_new,
1869 	.ce[1] = gk104_ce_new,
1870 	.ce[2] = gk104_ce_new,
1871 	.disp = gk110_disp_new,
1872 	.dma = gf119_dma_new,
1873 	.fifo = gk110_fifo_new,
1874 	.gr = gk110b_gr_new,
1875 	.mspdec = gk104_mspdec_new,
1876 	.msppp = gf100_msppp_new,
1877 	.msvld = gk104_msvld_new,
1878 	.sw = gf100_sw_new,
1879 };
1880 
1881 static const struct nvkm_device_chip
1882 nv106_chipset = {
1883 	.name = "GK208B",
1884 	.bar = gf100_bar_new,
1885 	.bios = nvkm_bios_new,
1886 	.bus = gf100_bus_new,
1887 	.clk = gk104_clk_new,
1888 	.devinit = gf100_devinit_new,
1889 	.fb = gk104_fb_new,
1890 	.fuse = gf100_fuse_new,
1891 	.gpio = gk104_gpio_new,
1892 	.i2c = gk104_i2c_new,
1893 	.ibus = gk104_ibus_new,
1894 	.iccsense = gf100_iccsense_new,
1895 	.imem = nv50_instmem_new,
1896 	.ltc = gk104_ltc_new,
1897 	.mc = gk20a_mc_new,
1898 	.mmu = gf100_mmu_new,
1899 	.mxm = nv50_mxm_new,
1900 	.pci = gk104_pci_new,
1901 	.pmu = gk208_pmu_new,
1902 	.therm = gf119_therm_new,
1903 	.timer = nv41_timer_new,
1904 	.top = gk104_top_new,
1905 	.volt = gk104_volt_new,
1906 	.ce[0] = gk104_ce_new,
1907 	.ce[1] = gk104_ce_new,
1908 	.ce[2] = gk104_ce_new,
1909 	.disp = gk110_disp_new,
1910 	.dma = gf119_dma_new,
1911 	.fifo = gk208_fifo_new,
1912 	.gr = gk208_gr_new,
1913 	.mspdec = gk104_mspdec_new,
1914 	.msppp = gf100_msppp_new,
1915 	.msvld = gk104_msvld_new,
1916 	.sw = gf100_sw_new,
1917 };
1918 
1919 static const struct nvkm_device_chip
1920 nv108_chipset = {
1921 	.name = "GK208",
1922 	.bar = gf100_bar_new,
1923 	.bios = nvkm_bios_new,
1924 	.bus = gf100_bus_new,
1925 	.clk = gk104_clk_new,
1926 	.devinit = gf100_devinit_new,
1927 	.fb = gk104_fb_new,
1928 	.fuse = gf100_fuse_new,
1929 	.gpio = gk104_gpio_new,
1930 	.i2c = gk104_i2c_new,
1931 	.ibus = gk104_ibus_new,
1932 	.iccsense = gf100_iccsense_new,
1933 	.imem = nv50_instmem_new,
1934 	.ltc = gk104_ltc_new,
1935 	.mc = gk20a_mc_new,
1936 	.mmu = gf100_mmu_new,
1937 	.mxm = nv50_mxm_new,
1938 	.pci = gk104_pci_new,
1939 	.pmu = gk208_pmu_new,
1940 	.therm = gf119_therm_new,
1941 	.timer = nv41_timer_new,
1942 	.top = gk104_top_new,
1943 	.volt = gk104_volt_new,
1944 	.ce[0] = gk104_ce_new,
1945 	.ce[1] = gk104_ce_new,
1946 	.ce[2] = gk104_ce_new,
1947 	.disp = gk110_disp_new,
1948 	.dma = gf119_dma_new,
1949 	.fifo = gk208_fifo_new,
1950 	.gr = gk208_gr_new,
1951 	.mspdec = gk104_mspdec_new,
1952 	.msppp = gf100_msppp_new,
1953 	.msvld = gk104_msvld_new,
1954 	.sw = gf100_sw_new,
1955 };
1956 
1957 static const struct nvkm_device_chip
1958 nv117_chipset = {
1959 	.name = "GM107",
1960 	.bar = gf100_bar_new,
1961 	.bios = nvkm_bios_new,
1962 	.bus = gf100_bus_new,
1963 	.clk = gk104_clk_new,
1964 	.devinit = gm107_devinit_new,
1965 	.fb = gm107_fb_new,
1966 	.fuse = gm107_fuse_new,
1967 	.gpio = gk104_gpio_new,
1968 	.i2c = gf119_i2c_new,
1969 	.ibus = gk104_ibus_new,
1970 	.iccsense = gf100_iccsense_new,
1971 	.imem = nv50_instmem_new,
1972 	.ltc = gm107_ltc_new,
1973 	.mc = gk20a_mc_new,
1974 	.mmu = gf100_mmu_new,
1975 	.mxm = nv50_mxm_new,
1976 	.pci = gk104_pci_new,
1977 	.pmu = gm107_pmu_new,
1978 	.therm = gm107_therm_new,
1979 	.timer = gk20a_timer_new,
1980 	.top = gk104_top_new,
1981 	.volt = gk104_volt_new,
1982 	.ce[0] = gm107_ce_new,
1983 	.ce[2] = gm107_ce_new,
1984 	.disp = gm107_disp_new,
1985 	.dma = gf119_dma_new,
1986 	.fifo = gm107_fifo_new,
1987 	.gr = gm107_gr_new,
1988 	.sw = gf100_sw_new,
1989 };
1990 
1991 static const struct nvkm_device_chip
1992 nv118_chipset = {
1993 	.name = "GM108",
1994 	.bar = gf100_bar_new,
1995 	.bios = nvkm_bios_new,
1996 	.bus = gf100_bus_new,
1997 	.clk = gk104_clk_new,
1998 	.devinit = gm107_devinit_new,
1999 	.fb = gm107_fb_new,
2000 	.fuse = gm107_fuse_new,
2001 	.gpio = gk104_gpio_new,
2002 	.i2c = gf119_i2c_new,
2003 	.ibus = gk104_ibus_new,
2004 	.iccsense = gf100_iccsense_new,
2005 	.imem = nv50_instmem_new,
2006 	.ltc = gm107_ltc_new,
2007 	.mc = gk20a_mc_new,
2008 	.mmu = gf100_mmu_new,
2009 	.mxm = nv50_mxm_new,
2010 	.pci = gk104_pci_new,
2011 	.pmu = gm107_pmu_new,
2012 	.therm = gm107_therm_new,
2013 	.timer = gk20a_timer_new,
2014 	.top = gk104_top_new,
2015 	.volt = gk104_volt_new,
2016 	.ce[0] = gm107_ce_new,
2017 	.ce[2] = gm107_ce_new,
2018 	.disp = gm107_disp_new,
2019 	.dma = gf119_dma_new,
2020 	.fifo = gm107_fifo_new,
2021 	.gr = gm107_gr_new,
2022 	.sw = gf100_sw_new,
2023 };
2024 
2025 static const struct nvkm_device_chip
2026 nv120_chipset = {
2027 	.name = "GM200",
2028 	.bar = gf100_bar_new,
2029 	.bios = nvkm_bios_new,
2030 	.bus = gf100_bus_new,
2031 	.devinit = gm200_devinit_new,
2032 	.fb = gm200_fb_new,
2033 	.fuse = gm107_fuse_new,
2034 	.gpio = gk104_gpio_new,
2035 	.i2c = gm200_i2c_new,
2036 	.ibus = gm200_ibus_new,
2037 	.iccsense = gf100_iccsense_new,
2038 	.imem = nv50_instmem_new,
2039 	.ltc = gm200_ltc_new,
2040 	.mc = gk20a_mc_new,
2041 	.mmu = gf100_mmu_new,
2042 	.mxm = nv50_mxm_new,
2043 	.pci = gk104_pci_new,
2044 	.pmu = gm107_pmu_new,
2045 	.secboot = gm200_secboot_new,
2046 	.timer = gk20a_timer_new,
2047 	.top = gk104_top_new,
2048 	.volt = gk104_volt_new,
2049 	.ce[0] = gm200_ce_new,
2050 	.ce[1] = gm200_ce_new,
2051 	.ce[2] = gm200_ce_new,
2052 	.disp = gm200_disp_new,
2053 	.dma = gf119_dma_new,
2054 	.fifo = gm200_fifo_new,
2055 	.gr = gm200_gr_new,
2056 	.sw = gf100_sw_new,
2057 };
2058 
2059 static const struct nvkm_device_chip
2060 nv124_chipset = {
2061 	.name = "GM204",
2062 	.bar = gf100_bar_new,
2063 	.bios = nvkm_bios_new,
2064 	.bus = gf100_bus_new,
2065 	.devinit = gm200_devinit_new,
2066 	.fb = gm200_fb_new,
2067 	.fuse = gm107_fuse_new,
2068 	.gpio = gk104_gpio_new,
2069 	.i2c = gm200_i2c_new,
2070 	.ibus = gm200_ibus_new,
2071 	.iccsense = gf100_iccsense_new,
2072 	.imem = nv50_instmem_new,
2073 	.ltc = gm200_ltc_new,
2074 	.mc = gk20a_mc_new,
2075 	.mmu = gf100_mmu_new,
2076 	.mxm = nv50_mxm_new,
2077 	.pci = gk104_pci_new,
2078 	.pmu = gm107_pmu_new,
2079 	.secboot = gm200_secboot_new,
2080 	.timer = gk20a_timer_new,
2081 	.top = gk104_top_new,
2082 	.volt = gk104_volt_new,
2083 	.ce[0] = gm200_ce_new,
2084 	.ce[1] = gm200_ce_new,
2085 	.ce[2] = gm200_ce_new,
2086 	.disp = gm200_disp_new,
2087 	.dma = gf119_dma_new,
2088 	.fifo = gm200_fifo_new,
2089 	.gr = gm200_gr_new,
2090 	.sw = gf100_sw_new,
2091 };
2092 
2093 static const struct nvkm_device_chip
2094 nv126_chipset = {
2095 	.name = "GM206",
2096 	.bar = gf100_bar_new,
2097 	.bios = nvkm_bios_new,
2098 	.bus = gf100_bus_new,
2099 	.devinit = gm200_devinit_new,
2100 	.fb = gm200_fb_new,
2101 	.fuse = gm107_fuse_new,
2102 	.gpio = gk104_gpio_new,
2103 	.i2c = gm200_i2c_new,
2104 	.ibus = gm200_ibus_new,
2105 	.iccsense = gf100_iccsense_new,
2106 	.imem = nv50_instmem_new,
2107 	.ltc = gm200_ltc_new,
2108 	.mc = gk20a_mc_new,
2109 	.mmu = gf100_mmu_new,
2110 	.mxm = nv50_mxm_new,
2111 	.pci = gk104_pci_new,
2112 	.pmu = gm107_pmu_new,
2113 	.secboot = gm200_secboot_new,
2114 	.timer = gk20a_timer_new,
2115 	.top = gk104_top_new,
2116 	.volt = gk104_volt_new,
2117 	.ce[0] = gm200_ce_new,
2118 	.ce[1] = gm200_ce_new,
2119 	.ce[2] = gm200_ce_new,
2120 	.disp = gm200_disp_new,
2121 	.dma = gf119_dma_new,
2122 	.fifo = gm200_fifo_new,
2123 	.gr = gm200_gr_new,
2124 	.sw = gf100_sw_new,
2125 };
2126 
2127 static const struct nvkm_device_chip
2128 nv12b_chipset = {
2129 	.name = "GM20B",
2130 	.bar = gk20a_bar_new,
2131 	.bus = gf100_bus_new,
2132 	.clk = gm20b_clk_new,
2133 	.fb = gk20a_fb_new,
2134 	.fuse = gm107_fuse_new,
2135 	.ibus = gk20a_ibus_new,
2136 	.imem = gk20a_instmem_new,
2137 	.ltc = gm200_ltc_new,
2138 	.mc = gk20a_mc_new,
2139 	.mmu = gf100_mmu_new,
2140 	.secboot = gm20b_secboot_new,
2141 	.timer = gk20a_timer_new,
2142 	.top = gk104_top_new,
2143 	.ce[2] = gm200_ce_new,
2144 	.volt = gm20b_volt_new,
2145 	.dma = gf119_dma_new,
2146 	.fifo = gm20b_fifo_new,
2147 	.gr = gm20b_gr_new,
2148 	.sw = gf100_sw_new,
2149 };
2150 
2151 static const struct nvkm_device_chip
2152 nv130_chipset = {
2153 	.name = "GP100",
2154 	.bar = gf100_bar_new,
2155 	.bios = nvkm_bios_new,
2156 	.bus = gf100_bus_new,
2157 	.devinit = gm200_devinit_new,
2158 	.fb = gp100_fb_new,
2159 	.fuse = gm107_fuse_new,
2160 	.gpio = gk104_gpio_new,
2161 	.i2c = gm200_i2c_new,
2162 	.ibus = gm200_ibus_new,
2163 	.imem = nv50_instmem_new,
2164 	.ltc = gp100_ltc_new,
2165 	.mc = gp100_mc_new,
2166 	.mmu = gf100_mmu_new,
2167 	.secboot = gm200_secboot_new,
2168 	.pci = gp100_pci_new,
2169 	.timer = gk20a_timer_new,
2170 	.top = gk104_top_new,
2171 	.ce[0] = gp100_ce_new,
2172 	.ce[1] = gp100_ce_new,
2173 	.ce[2] = gp100_ce_new,
2174 	.ce[3] = gp100_ce_new,
2175 	.ce[4] = gp100_ce_new,
2176 	.ce[5] = gp100_ce_new,
2177 	.dma = gf119_dma_new,
2178 	.disp = gp100_disp_new,
2179 	.fifo = gp100_fifo_new,
2180 	.gr = gp100_gr_new,
2181 	.sw = gf100_sw_new,
2182 };
2183 
2184 static const struct nvkm_device_chip
2185 nv134_chipset = {
2186 	.name = "GP104",
2187 	.bar = gf100_bar_new,
2188 	.bios = nvkm_bios_new,
2189 	.bus = gf100_bus_new,
2190 	.devinit = gm200_devinit_new,
2191 	.fb = gp104_fb_new,
2192 	.fuse = gm107_fuse_new,
2193 	.gpio = gk104_gpio_new,
2194 	.i2c = gm200_i2c_new,
2195 	.ibus = gm200_ibus_new,
2196 	.imem = nv50_instmem_new,
2197 	.ltc = gp100_ltc_new,
2198 	.mc = gp100_mc_new,
2199 	.mmu = gf100_mmu_new,
2200 	.pci = gp100_pci_new,
2201 	.timer = gk20a_timer_new,
2202 	.top = gk104_top_new,
2203 	.ce[0] = gp104_ce_new,
2204 	.ce[1] = gp104_ce_new,
2205 	.ce[2] = gp104_ce_new,
2206 	.ce[3] = gp104_ce_new,
2207 	.disp = gp104_disp_new,
2208 	.dma = gf119_dma_new,
2209 	.fifo = gp100_fifo_new,
2210 };
2211 
2212 static int
2213 nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size,
2214 		       struct nvkm_notify *notify)
2215 {
2216 	if (!WARN_ON(size != 0)) {
2217 		notify->size  = 0;
2218 		notify->types = 1;
2219 		notify->index = 0;
2220 		return 0;
2221 	}
2222 	return -EINVAL;
2223 }
2224 
2225 static const struct nvkm_event_func
2226 nvkm_device_event_func = {
2227 	.ctor = nvkm_device_event_ctor,
2228 };
2229 
2230 struct nvkm_subdev *
2231 nvkm_device_subdev(struct nvkm_device *device, int index)
2232 {
2233 	struct nvkm_engine *engine;
2234 
2235 	if (device->disable_mask & (1ULL << index))
2236 		return NULL;
2237 
2238 	switch (index) {
2239 #define _(n,p,m) case NVKM_SUBDEV_##n: if (p) return (m); break
2240 	_(BAR     , device->bar     , &device->bar->subdev);
2241 	_(VBIOS   , device->bios    , &device->bios->subdev);
2242 	_(BUS     , device->bus     , &device->bus->subdev);
2243 	_(CLK     , device->clk     , &device->clk->subdev);
2244 	_(DEVINIT , device->devinit , &device->devinit->subdev);
2245 	_(FB      , device->fb      , &device->fb->subdev);
2246 	_(FUSE    , device->fuse    , &device->fuse->subdev);
2247 	_(GPIO    , device->gpio    , &device->gpio->subdev);
2248 	_(I2C     , device->i2c     , &device->i2c->subdev);
2249 	_(IBUS    , device->ibus    ,  device->ibus);
2250 	_(ICCSENSE, device->iccsense, &device->iccsense->subdev);
2251 	_(INSTMEM , device->imem    , &device->imem->subdev);
2252 	_(LTC     , device->ltc     , &device->ltc->subdev);
2253 	_(MC      , device->mc      , &device->mc->subdev);
2254 	_(MMU     , device->mmu     , &device->mmu->subdev);
2255 	_(MXM     , device->mxm     ,  device->mxm);
2256 	_(PCI     , device->pci     , &device->pci->subdev);
2257 	_(PMU     , device->pmu     , &device->pmu->subdev);
2258 	_(SECBOOT , device->secboot , &device->secboot->subdev);
2259 	_(THERM   , device->therm   , &device->therm->subdev);
2260 	_(TIMER   , device->timer   , &device->timer->subdev);
2261 	_(TOP     , device->top     , &device->top->subdev);
2262 	_(VOLT    , device->volt    , &device->volt->subdev);
2263 #undef _
2264 	default:
2265 		engine = nvkm_device_engine(device, index);
2266 		if (engine)
2267 			return &engine->subdev;
2268 		break;
2269 	}
2270 	return NULL;
2271 }
2272 
2273 struct nvkm_engine *
2274 nvkm_device_engine(struct nvkm_device *device, int index)
2275 {
2276 	if (device->disable_mask & (1ULL << index))
2277 		return NULL;
2278 
2279 	switch (index) {
2280 #define _(n,p,m) case NVKM_ENGINE_##n: if (p) return (m); break
2281 	_(BSP    , device->bsp     ,  device->bsp);
2282 	_(CE0    , device->ce[0]   ,  device->ce[0]);
2283 	_(CE1    , device->ce[1]   ,  device->ce[1]);
2284 	_(CE2    , device->ce[2]   ,  device->ce[2]);
2285 	_(CE3    , device->ce[3]   ,  device->ce[3]);
2286 	_(CE4    , device->ce[4]   ,  device->ce[4]);
2287 	_(CE5    , device->ce[5]   ,  device->ce[5]);
2288 	_(CIPHER , device->cipher  ,  device->cipher);
2289 	_(DISP   , device->disp    , &device->disp->engine);
2290 	_(DMAOBJ , device->dma     , &device->dma->engine);
2291 	_(FIFO   , device->fifo    , &device->fifo->engine);
2292 	_(GR     , device->gr      , &device->gr->engine);
2293 	_(IFB    , device->ifb     ,  device->ifb);
2294 	_(ME     , device->me      ,  device->me);
2295 	_(MPEG   , device->mpeg    ,  device->mpeg);
2296 	_(MSENC  , device->msenc   ,  device->msenc);
2297 	_(MSPDEC , device->mspdec  ,  device->mspdec);
2298 	_(MSPPP  , device->msppp   ,  device->msppp);
2299 	_(MSVLD  , device->msvld   ,  device->msvld);
2300 	_(NVENC0 , device->nvenc[0],  device->nvenc[0]);
2301 	_(NVENC1 , device->nvenc[1],  device->nvenc[1]);
2302 	_(NVENC2 , device->nvenc[2],  device->nvenc[2]);
2303 	_(NVDEC  , device->nvdec   ,  device->nvdec);
2304 	_(PM     , device->pm      , &device->pm->engine);
2305 	_(SEC    , device->sec     ,  device->sec);
2306 	_(SW     , device->sw      , &device->sw->engine);
2307 	_(VIC    , device->vic     ,  device->vic);
2308 	_(VP     , device->vp      ,  device->vp);
2309 #undef _
2310 	default:
2311 		WARN_ON(1);
2312 		break;
2313 	}
2314 	return NULL;
2315 }
2316 
2317 int
2318 nvkm_device_fini(struct nvkm_device *device, bool suspend)
2319 {
2320 	const char *action = suspend ? "suspend" : "fini";
2321 	struct nvkm_subdev *subdev;
2322 	int ret, i;
2323 	s64 time;
2324 
2325 	nvdev_trace(device, "%s running...\n", action);
2326 	time = ktime_to_us(ktime_get());
2327 
2328 	nvkm_acpi_fini(device);
2329 
2330 	for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) {
2331 		if ((subdev = nvkm_device_subdev(device, i))) {
2332 			ret = nvkm_subdev_fini(subdev, suspend);
2333 			if (ret && suspend)
2334 				goto fail;
2335 		}
2336 	}
2337 
2338 
2339 	if (device->func->fini)
2340 		device->func->fini(device, suspend);
2341 
2342 	time = ktime_to_us(ktime_get()) - time;
2343 	nvdev_trace(device, "%s completed in %lldus...\n", action, time);
2344 	return 0;
2345 
2346 fail:
2347 	do {
2348 		if ((subdev = nvkm_device_subdev(device, i))) {
2349 			int rret = nvkm_subdev_init(subdev);
2350 			if (rret)
2351 				nvkm_fatal(subdev, "failed restart, %d\n", ret);
2352 		}
2353 	} while (++i < NVKM_SUBDEV_NR);
2354 
2355 	nvdev_trace(device, "%s failed with %d\n", action, ret);
2356 	return ret;
2357 }
2358 
2359 static int
2360 nvkm_device_preinit(struct nvkm_device *device)
2361 {
2362 	struct nvkm_subdev *subdev;
2363 	int ret, i;
2364 	s64 time;
2365 
2366 	nvdev_trace(device, "preinit running...\n");
2367 	time = ktime_to_us(ktime_get());
2368 
2369 	if (device->func->preinit) {
2370 		ret = device->func->preinit(device);
2371 		if (ret)
2372 			goto fail;
2373 	}
2374 
2375 	for (i = 0; i < NVKM_SUBDEV_NR; i++) {
2376 		if ((subdev = nvkm_device_subdev(device, i))) {
2377 			ret = nvkm_subdev_preinit(subdev);
2378 			if (ret)
2379 				goto fail;
2380 		}
2381 	}
2382 
2383 	ret = nvkm_devinit_post(device->devinit, &device->disable_mask);
2384 	if (ret)
2385 		goto fail;
2386 
2387 	time = ktime_to_us(ktime_get()) - time;
2388 	nvdev_trace(device, "preinit completed in %lldus\n", time);
2389 	return 0;
2390 
2391 fail:
2392 	nvdev_error(device, "preinit failed with %d\n", ret);
2393 	return ret;
2394 }
2395 
2396 int
2397 nvkm_device_init(struct nvkm_device *device)
2398 {
2399 	struct nvkm_subdev *subdev;
2400 	int ret, i;
2401 	s64 time;
2402 
2403 	ret = nvkm_device_preinit(device);
2404 	if (ret)
2405 		return ret;
2406 
2407 	nvkm_device_fini(device, false);
2408 
2409 	nvdev_trace(device, "init running...\n");
2410 	time = ktime_to_us(ktime_get());
2411 
2412 	if (device->func->init) {
2413 		ret = device->func->init(device);
2414 		if (ret)
2415 			goto fail;
2416 	}
2417 
2418 	for (i = 0; i < NVKM_SUBDEV_NR; i++) {
2419 		if ((subdev = nvkm_device_subdev(device, i))) {
2420 			ret = nvkm_subdev_init(subdev);
2421 			if (ret)
2422 				goto fail_subdev;
2423 		}
2424 	}
2425 
2426 	nvkm_acpi_init(device);
2427 
2428 	time = ktime_to_us(ktime_get()) - time;
2429 	nvdev_trace(device, "init completed in %lldus\n", time);
2430 	return 0;
2431 
2432 fail_subdev:
2433 	do {
2434 		if ((subdev = nvkm_device_subdev(device, i)))
2435 			nvkm_subdev_fini(subdev, false);
2436 	} while (--i >= 0);
2437 
2438 fail:
2439 	nvkm_device_fini(device, false);
2440 
2441 	nvdev_error(device, "init failed with %d\n", ret);
2442 	return ret;
2443 }
2444 
2445 void
2446 nvkm_device_del(struct nvkm_device **pdevice)
2447 {
2448 	struct nvkm_device *device = *pdevice;
2449 	int i;
2450 	if (device) {
2451 		mutex_lock(&nv_devices_mutex);
2452 		device->disable_mask = 0;
2453 		for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) {
2454 			struct nvkm_subdev *subdev =
2455 				nvkm_device_subdev(device, i);
2456 			nvkm_subdev_del(&subdev);
2457 		}
2458 
2459 		nvkm_event_fini(&device->event);
2460 
2461 		if (device->pri)
2462 			iounmap(device->pri);
2463 		list_del(&device->head);
2464 
2465 		if (device->func->dtor)
2466 			*pdevice = device->func->dtor(device);
2467 		mutex_unlock(&nv_devices_mutex);
2468 
2469 		kfree(*pdevice);
2470 		*pdevice = NULL;
2471 	}
2472 }
2473 
2474 int
2475 nvkm_device_ctor(const struct nvkm_device_func *func,
2476 		 const struct nvkm_device_quirk *quirk,
2477 		 struct device *dev, enum nvkm_device_type type, u64 handle,
2478 		 const char *name, const char *cfg, const char *dbg,
2479 		 bool detect, bool mmio, u64 subdev_mask,
2480 		 struct nvkm_device *device)
2481 {
2482 	struct nvkm_subdev *subdev;
2483 	u64 mmio_base, mmio_size;
2484 	u32 boot0, strap;
2485 	void __iomem *map;
2486 	int ret = -EEXIST;
2487 	int i;
2488 
2489 	mutex_lock(&nv_devices_mutex);
2490 	if (nvkm_device_find_locked(handle))
2491 		goto done;
2492 
2493 	device->func = func;
2494 	device->quirk = quirk;
2495 	device->dev = dev;
2496 	device->type = type;
2497 	device->handle = handle;
2498 	device->cfgopt = cfg;
2499 	device->dbgopt = dbg;
2500 	device->name = name;
2501 	list_add_tail(&device->head, &nv_devices);
2502 	device->debug = nvkm_dbgopt(device->dbgopt, "device");
2503 
2504 	ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event);
2505 	if (ret)
2506 		goto done;
2507 
2508 	mmio_base = device->func->resource_addr(device, 0);
2509 	mmio_size = device->func->resource_size(device, 0);
2510 
2511 	/* identify the chipset, and determine classes of subdev/engines */
2512 	if (detect) {
2513 		map = ioremap(mmio_base, 0x102000);
2514 		if (ret = -ENOMEM, map == NULL)
2515 			goto done;
2516 
2517 		/* switch mmio to cpu's native endianness */
2518 #ifndef __BIG_ENDIAN
2519 		if (ioread32_native(map + 0x000004) != 0x00000000) {
2520 #else
2521 		if (ioread32_native(map + 0x000004) == 0x00000000) {
2522 #endif
2523 			iowrite32_native(0x01000001, map + 0x000004);
2524 			ioread32_native(map);
2525 		}
2526 
2527 		/* read boot0 and strapping information */
2528 		boot0 = ioread32_native(map + 0x000000);
2529 		strap = ioread32_native(map + 0x101000);
2530 		iounmap(map);
2531 
2532 		/* determine chipset and derive architecture from it */
2533 		if ((boot0 & 0x1f000000) > 0) {
2534 			device->chipset = (boot0 & 0x1ff00000) >> 20;
2535 			device->chiprev = (boot0 & 0x000000ff);
2536 			switch (device->chipset & 0x1f0) {
2537 			case 0x010: {
2538 				if (0x461 & (1 << (device->chipset & 0xf)))
2539 					device->card_type = NV_10;
2540 				else
2541 					device->card_type = NV_11;
2542 				device->chiprev = 0x00;
2543 				break;
2544 			}
2545 			case 0x020: device->card_type = NV_20; break;
2546 			case 0x030: device->card_type = NV_30; break;
2547 			case 0x040:
2548 			case 0x060: device->card_type = NV_40; break;
2549 			case 0x050:
2550 			case 0x080:
2551 			case 0x090:
2552 			case 0x0a0: device->card_type = NV_50; break;
2553 			case 0x0c0:
2554 			case 0x0d0: device->card_type = NV_C0; break;
2555 			case 0x0e0:
2556 			case 0x0f0:
2557 			case 0x100: device->card_type = NV_E0; break;
2558 			case 0x110:
2559 			case 0x120: device->card_type = GM100; break;
2560 			case 0x130: device->card_type = GP100; break;
2561 			default:
2562 				break;
2563 			}
2564 		} else
2565 		if ((boot0 & 0xff00fff0) == 0x20004000) {
2566 			if (boot0 & 0x00f00000)
2567 				device->chipset = 0x05;
2568 			else
2569 				device->chipset = 0x04;
2570 			device->card_type = NV_04;
2571 		}
2572 
2573 		switch (device->chipset) {
2574 		case 0x004: device->chip = &nv4_chipset; break;
2575 		case 0x005: device->chip = &nv5_chipset; break;
2576 		case 0x010: device->chip = &nv10_chipset; break;
2577 		case 0x011: device->chip = &nv11_chipset; break;
2578 		case 0x015: device->chip = &nv15_chipset; break;
2579 		case 0x017: device->chip = &nv17_chipset; break;
2580 		case 0x018: device->chip = &nv18_chipset; break;
2581 		case 0x01a: device->chip = &nv1a_chipset; break;
2582 		case 0x01f: device->chip = &nv1f_chipset; break;
2583 		case 0x020: device->chip = &nv20_chipset; break;
2584 		case 0x025: device->chip = &nv25_chipset; break;
2585 		case 0x028: device->chip = &nv28_chipset; break;
2586 		case 0x02a: device->chip = &nv2a_chipset; break;
2587 		case 0x030: device->chip = &nv30_chipset; break;
2588 		case 0x031: device->chip = &nv31_chipset; break;
2589 		case 0x034: device->chip = &nv34_chipset; break;
2590 		case 0x035: device->chip = &nv35_chipset; break;
2591 		case 0x036: device->chip = &nv36_chipset; break;
2592 		case 0x040: device->chip = &nv40_chipset; break;
2593 		case 0x041: device->chip = &nv41_chipset; break;
2594 		case 0x042: device->chip = &nv42_chipset; break;
2595 		case 0x043: device->chip = &nv43_chipset; break;
2596 		case 0x044: device->chip = &nv44_chipset; break;
2597 		case 0x045: device->chip = &nv45_chipset; break;
2598 		case 0x046: device->chip = &nv46_chipset; break;
2599 		case 0x047: device->chip = &nv47_chipset; break;
2600 		case 0x049: device->chip = &nv49_chipset; break;
2601 		case 0x04a: device->chip = &nv4a_chipset; break;
2602 		case 0x04b: device->chip = &nv4b_chipset; break;
2603 		case 0x04c: device->chip = &nv4c_chipset; break;
2604 		case 0x04e: device->chip = &nv4e_chipset; break;
2605 		case 0x050: device->chip = &nv50_chipset; break;
2606 		case 0x063: device->chip = &nv63_chipset; break;
2607 		case 0x067: device->chip = &nv67_chipset; break;
2608 		case 0x068: device->chip = &nv68_chipset; break;
2609 		case 0x084: device->chip = &nv84_chipset; break;
2610 		case 0x086: device->chip = &nv86_chipset; break;
2611 		case 0x092: device->chip = &nv92_chipset; break;
2612 		case 0x094: device->chip = &nv94_chipset; break;
2613 		case 0x096: device->chip = &nv96_chipset; break;
2614 		case 0x098: device->chip = &nv98_chipset; break;
2615 		case 0x0a0: device->chip = &nva0_chipset; break;
2616 		case 0x0a3: device->chip = &nva3_chipset; break;
2617 		case 0x0a5: device->chip = &nva5_chipset; break;
2618 		case 0x0a8: device->chip = &nva8_chipset; break;
2619 		case 0x0aa: device->chip = &nvaa_chipset; break;
2620 		case 0x0ac: device->chip = &nvac_chipset; break;
2621 		case 0x0af: device->chip = &nvaf_chipset; break;
2622 		case 0x0c0: device->chip = &nvc0_chipset; break;
2623 		case 0x0c1: device->chip = &nvc1_chipset; break;
2624 		case 0x0c3: device->chip = &nvc3_chipset; break;
2625 		case 0x0c4: device->chip = &nvc4_chipset; break;
2626 		case 0x0c8: device->chip = &nvc8_chipset; break;
2627 		case 0x0ce: device->chip = &nvce_chipset; break;
2628 		case 0x0cf: device->chip = &nvcf_chipset; break;
2629 		case 0x0d7: device->chip = &nvd7_chipset; break;
2630 		case 0x0d9: device->chip = &nvd9_chipset; break;
2631 		case 0x0e4: device->chip = &nve4_chipset; break;
2632 		case 0x0e6: device->chip = &nve6_chipset; break;
2633 		case 0x0e7: device->chip = &nve7_chipset; break;
2634 		case 0x0ea: device->chip = &nvea_chipset; break;
2635 		case 0x0f0: device->chip = &nvf0_chipset; break;
2636 		case 0x0f1: device->chip = &nvf1_chipset; break;
2637 		case 0x106: device->chip = &nv106_chipset; break;
2638 		case 0x108: device->chip = &nv108_chipset; break;
2639 		case 0x117: device->chip = &nv117_chipset; break;
2640 		case 0x118: device->chip = &nv118_chipset; break;
2641 		case 0x120: device->chip = &nv120_chipset; break;
2642 		case 0x124: device->chip = &nv124_chipset; break;
2643 		case 0x126: device->chip = &nv126_chipset; break;
2644 		case 0x12b: device->chip = &nv12b_chipset; break;
2645 		case 0x130: device->chip = &nv130_chipset; break;
2646 		case 0x134: device->chip = &nv134_chipset; break;
2647 		default:
2648 			nvdev_error(device, "unknown chipset (%08x)\n", boot0);
2649 			goto done;
2650 		}
2651 
2652 		nvdev_info(device, "NVIDIA %s (%08x)\n",
2653 			   device->chip->name, boot0);
2654 
2655 		/* determine frequency of timing crystal */
2656 		if ( device->card_type <= NV_10 || device->chipset < 0x17 ||
2657 		    (device->chipset >= 0x20 && device->chipset < 0x25))
2658 			strap &= 0x00000040;
2659 		else
2660 			strap &= 0x00400040;
2661 
2662 		switch (strap) {
2663 		case 0x00000000: device->crystal = 13500; break;
2664 		case 0x00000040: device->crystal = 14318; break;
2665 		case 0x00400000: device->crystal = 27000; break;
2666 		case 0x00400040: device->crystal = 25000; break;
2667 		}
2668 	} else {
2669 		device->chip = &null_chipset;
2670 	}
2671 
2672 	if (!device->name)
2673 		device->name = device->chip->name;
2674 
2675 	if (mmio) {
2676 		device->pri = ioremap(mmio_base, mmio_size);
2677 		if (!device->pri) {
2678 			nvdev_error(device, "unable to map PRI\n");
2679 			ret = -ENOMEM;
2680 			goto done;
2681 		}
2682 	}
2683 
2684 	mutex_init(&device->mutex);
2685 
2686 	for (i = 0; i < NVKM_SUBDEV_NR; i++) {
2687 #define _(s,m) case s:                                                         \
2688 	if (device->chip->m && (subdev_mask & (1ULL << (s)))) {                \
2689 		ret = device->chip->m(device, (s), &device->m);                \
2690 		if (ret) {                                                     \
2691 			subdev = nvkm_device_subdev(device, (s));              \
2692 			nvkm_subdev_del(&subdev);                              \
2693 			device->m = NULL;                                      \
2694 			if (ret != -ENODEV) {                                  \
2695 				nvdev_error(device, "%s ctor failed, %d\n",    \
2696 					    nvkm_subdev_name[s], ret);         \
2697 				goto done;                                     \
2698 			}                                                      \
2699 		}                                                              \
2700 	}                                                                      \
2701 	break
2702 		switch (i) {
2703 		_(NVKM_SUBDEV_BAR     ,      bar);
2704 		_(NVKM_SUBDEV_VBIOS   ,     bios);
2705 		_(NVKM_SUBDEV_BUS     ,      bus);
2706 		_(NVKM_SUBDEV_CLK     ,      clk);
2707 		_(NVKM_SUBDEV_DEVINIT ,  devinit);
2708 		_(NVKM_SUBDEV_FB      ,       fb);
2709 		_(NVKM_SUBDEV_FUSE    ,     fuse);
2710 		_(NVKM_SUBDEV_GPIO    ,     gpio);
2711 		_(NVKM_SUBDEV_I2C     ,      i2c);
2712 		_(NVKM_SUBDEV_IBUS    ,     ibus);
2713 		_(NVKM_SUBDEV_ICCSENSE, iccsense);
2714 		_(NVKM_SUBDEV_INSTMEM ,     imem);
2715 		_(NVKM_SUBDEV_LTC     ,      ltc);
2716 		_(NVKM_SUBDEV_MC      ,       mc);
2717 		_(NVKM_SUBDEV_MMU     ,      mmu);
2718 		_(NVKM_SUBDEV_MXM     ,      mxm);
2719 		_(NVKM_SUBDEV_PCI     ,      pci);
2720 		_(NVKM_SUBDEV_PMU     ,      pmu);
2721 		_(NVKM_SUBDEV_SECBOOT ,  secboot);
2722 		_(NVKM_SUBDEV_THERM   ,    therm);
2723 		_(NVKM_SUBDEV_TIMER   ,    timer);
2724 		_(NVKM_SUBDEV_TOP     ,      top);
2725 		_(NVKM_SUBDEV_VOLT    ,     volt);
2726 		_(NVKM_ENGINE_BSP     ,      bsp);
2727 		_(NVKM_ENGINE_CE0     ,    ce[0]);
2728 		_(NVKM_ENGINE_CE1     ,    ce[1]);
2729 		_(NVKM_ENGINE_CE2     ,    ce[2]);
2730 		_(NVKM_ENGINE_CE3     ,    ce[3]);
2731 		_(NVKM_ENGINE_CE4     ,    ce[4]);
2732 		_(NVKM_ENGINE_CE5     ,    ce[5]);
2733 		_(NVKM_ENGINE_CIPHER  ,   cipher);
2734 		_(NVKM_ENGINE_DISP    ,     disp);
2735 		_(NVKM_ENGINE_DMAOBJ  ,      dma);
2736 		_(NVKM_ENGINE_FIFO    ,     fifo);
2737 		_(NVKM_ENGINE_GR      ,       gr);
2738 		_(NVKM_ENGINE_IFB     ,      ifb);
2739 		_(NVKM_ENGINE_ME      ,       me);
2740 		_(NVKM_ENGINE_MPEG    ,     mpeg);
2741 		_(NVKM_ENGINE_MSENC   ,    msenc);
2742 		_(NVKM_ENGINE_MSPDEC  ,   mspdec);
2743 		_(NVKM_ENGINE_MSPPP   ,    msppp);
2744 		_(NVKM_ENGINE_MSVLD   ,    msvld);
2745 		_(NVKM_ENGINE_NVENC0  , nvenc[0]);
2746 		_(NVKM_ENGINE_NVENC1  , nvenc[1]);
2747 		_(NVKM_ENGINE_NVENC2  , nvenc[2]);
2748 		_(NVKM_ENGINE_NVDEC   ,    nvdec);
2749 		_(NVKM_ENGINE_PM      ,       pm);
2750 		_(NVKM_ENGINE_SEC     ,      sec);
2751 		_(NVKM_ENGINE_SW      ,       sw);
2752 		_(NVKM_ENGINE_VIC     ,      vic);
2753 		_(NVKM_ENGINE_VP      ,       vp);
2754 		default:
2755 			WARN_ON(1);
2756 			continue;
2757 		}
2758 #undef _
2759 	}
2760 
2761 	ret = 0;
2762 done:
2763 	mutex_unlock(&nv_devices_mutex);
2764 	return ret;
2765 }
2766