1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "priv.h" 25 #include "acpi.h" 26 27 #include <core/client.h> 28 #include <core/option.h> 29 #include <core/notify.h> 30 #include <core/parent.h> 31 #include <subdev/bios.h> 32 #include <subdev/fb.h> 33 #include <subdev/instmem.h> 34 35 #include <nvif/class.h> 36 #include <nvif/unpack.h> 37 38 static DEFINE_MUTEX(nv_devices_mutex); 39 static LIST_HEAD(nv_devices); 40 41 struct nvkm_device * 42 nvkm_device_find(u64 name) 43 { 44 struct nvkm_device *device, *match = NULL; 45 mutex_lock(&nv_devices_mutex); 46 list_for_each_entry(device, &nv_devices, head) { 47 if (device->handle == name) { 48 match = device; 49 break; 50 } 51 } 52 mutex_unlock(&nv_devices_mutex); 53 return match; 54 } 55 56 int 57 nvkm_device_list(u64 *name, int size) 58 { 59 struct nvkm_device *device; 60 int nr = 0; 61 mutex_lock(&nv_devices_mutex); 62 list_for_each_entry(device, &nv_devices, head) { 63 if (nr++ < size) 64 name[nr - 1] = device->handle; 65 } 66 mutex_unlock(&nv_devices_mutex); 67 return nr; 68 } 69 70 /****************************************************************************** 71 * nvkm_devobj (0x0080): class implementation 72 *****************************************************************************/ 73 74 struct nvkm_devobj { 75 struct nvkm_parent base; 76 struct nvkm_object *subdev[NVDEV_SUBDEV_NR]; 77 }; 78 79 static int 80 nvkm_devobj_info(struct nvkm_object *object, void *data, u32 size) 81 { 82 struct nvkm_device *device = nv_device(object); 83 struct nvkm_fb *fb = nvkm_fb(device); 84 struct nvkm_instmem *imem = nvkm_instmem(device); 85 union { 86 struct nv_device_info_v0 v0; 87 } *args = data; 88 int ret; 89 90 nv_ioctl(object, "device info size %d\n", size); 91 if (nvif_unpack(args->v0, 0, 0, false)) { 92 nv_ioctl(object, "device info vers %d\n", args->v0.version); 93 } else 94 return ret; 95 96 switch (device->chipset) { 97 case 0x01a: 98 case 0x01f: 99 case 0x04c: 100 case 0x04e: 101 case 0x063: 102 case 0x067: 103 case 0x068: 104 case 0x0aa: 105 case 0x0ac: 106 case 0x0af: 107 args->v0.platform = NV_DEVICE_INFO_V0_IGP; 108 break; 109 default: 110 if (device->pdev) { 111 if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP)) 112 args->v0.platform = NV_DEVICE_INFO_V0_AGP; 113 else 114 if (pci_is_pcie(device->pdev)) 115 args->v0.platform = NV_DEVICE_INFO_V0_PCIE; 116 else 117 args->v0.platform = NV_DEVICE_INFO_V0_PCI; 118 } else { 119 args->v0.platform = NV_DEVICE_INFO_V0_SOC; 120 } 121 break; 122 } 123 124 switch (device->card_type) { 125 case NV_04: args->v0.family = NV_DEVICE_INFO_V0_TNT; break; 126 case NV_10: 127 case NV_11: args->v0.family = NV_DEVICE_INFO_V0_CELSIUS; break; 128 case NV_20: args->v0.family = NV_DEVICE_INFO_V0_KELVIN; break; 129 case NV_30: args->v0.family = NV_DEVICE_INFO_V0_RANKINE; break; 130 case NV_40: args->v0.family = NV_DEVICE_INFO_V0_CURIE; break; 131 case NV_50: args->v0.family = NV_DEVICE_INFO_V0_TESLA; break; 132 case NV_C0: args->v0.family = NV_DEVICE_INFO_V0_FERMI; break; 133 case NV_E0: args->v0.family = NV_DEVICE_INFO_V0_KEPLER; break; 134 case GM100: args->v0.family = NV_DEVICE_INFO_V0_MAXWELL; break; 135 default: 136 args->v0.family = 0; 137 break; 138 } 139 140 args->v0.chipset = device->chipset; 141 args->v0.revision = device->chiprev; 142 if (fb && fb->ram) 143 args->v0.ram_size = args->v0.ram_user = fb->ram->size; 144 else 145 args->v0.ram_size = args->v0.ram_user = 0; 146 if (imem && args->v0.ram_size > 0) 147 args->v0.ram_user = args->v0.ram_user - imem->reserved; 148 149 return 0; 150 } 151 152 static int 153 nvkm_devobj_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) 154 { 155 switch (mthd) { 156 case NV_DEVICE_V0_INFO: 157 return nvkm_devobj_info(object, data, size); 158 default: 159 break; 160 } 161 return -EINVAL; 162 } 163 164 static u8 165 nvkm_devobj_rd08(struct nvkm_object *object, u64 addr) 166 { 167 return nvkm_rd08(object->engine->subdev.device, addr); 168 } 169 170 static u16 171 nvkm_devobj_rd16(struct nvkm_object *object, u64 addr) 172 { 173 return nvkm_rd16(object->engine->subdev.device, addr); 174 } 175 176 static u32 177 nvkm_devobj_rd32(struct nvkm_object *object, u64 addr) 178 { 179 return nvkm_rd32(object->engine->subdev.device, addr); 180 } 181 182 static void 183 nvkm_devobj_wr08(struct nvkm_object *object, u64 addr, u8 data) 184 { 185 nvkm_wr08(object->engine->subdev.device, addr, data); 186 } 187 188 static void 189 nvkm_devobj_wr16(struct nvkm_object *object, u64 addr, u16 data) 190 { 191 nvkm_wr16(object->engine->subdev.device, addr, data); 192 } 193 194 static void 195 nvkm_devobj_wr32(struct nvkm_object *object, u64 addr, u32 data) 196 { 197 nvkm_wr32(object->engine->subdev.device, addr, data); 198 } 199 200 static int 201 nvkm_devobj_map(struct nvkm_object *object, u64 *addr, u32 *size) 202 { 203 struct nvkm_device *device = nv_device(object); 204 *addr = nv_device_resource_start(device, 0); 205 *size = nv_device_resource_len(device, 0); 206 return 0; 207 } 208 209 static const u64 disable_map[] = { 210 [NVDEV_SUBDEV_VBIOS] = NV_DEVICE_V0_DISABLE_VBIOS, 211 [NVDEV_SUBDEV_DEVINIT] = NV_DEVICE_V0_DISABLE_CORE, 212 [NVDEV_SUBDEV_GPIO] = NV_DEVICE_V0_DISABLE_CORE, 213 [NVDEV_SUBDEV_I2C] = NV_DEVICE_V0_DISABLE_CORE, 214 [NVDEV_SUBDEV_CLK ] = NV_DEVICE_V0_DISABLE_CORE, 215 [NVDEV_SUBDEV_MXM] = NV_DEVICE_V0_DISABLE_CORE, 216 [NVDEV_SUBDEV_MC] = NV_DEVICE_V0_DISABLE_CORE, 217 [NVDEV_SUBDEV_BUS] = NV_DEVICE_V0_DISABLE_CORE, 218 [NVDEV_SUBDEV_TIMER] = NV_DEVICE_V0_DISABLE_CORE, 219 [NVDEV_SUBDEV_FB] = NV_DEVICE_V0_DISABLE_CORE, 220 [NVDEV_SUBDEV_LTC] = NV_DEVICE_V0_DISABLE_CORE, 221 [NVDEV_SUBDEV_IBUS] = NV_DEVICE_V0_DISABLE_CORE, 222 [NVDEV_SUBDEV_INSTMEM] = NV_DEVICE_V0_DISABLE_CORE, 223 [NVDEV_SUBDEV_MMU] = NV_DEVICE_V0_DISABLE_CORE, 224 [NVDEV_SUBDEV_BAR] = NV_DEVICE_V0_DISABLE_CORE, 225 [NVDEV_SUBDEV_VOLT] = NV_DEVICE_V0_DISABLE_CORE, 226 [NVDEV_SUBDEV_THERM] = NV_DEVICE_V0_DISABLE_CORE, 227 [NVDEV_SUBDEV_PMU] = NV_DEVICE_V0_DISABLE_CORE, 228 [NVDEV_SUBDEV_FUSE] = NV_DEVICE_V0_DISABLE_CORE, 229 [NVDEV_ENGINE_DMAOBJ] = NV_DEVICE_V0_DISABLE_CORE, 230 [NVDEV_ENGINE_PM ] = NV_DEVICE_V0_DISABLE_CORE, 231 [NVDEV_ENGINE_FIFO] = NV_DEVICE_V0_DISABLE_FIFO, 232 [NVDEV_ENGINE_SW] = NV_DEVICE_V0_DISABLE_FIFO, 233 [NVDEV_ENGINE_GR] = NV_DEVICE_V0_DISABLE_GR, 234 [NVDEV_ENGINE_MPEG] = NV_DEVICE_V0_DISABLE_MPEG, 235 [NVDEV_ENGINE_ME] = NV_DEVICE_V0_DISABLE_ME, 236 [NVDEV_ENGINE_VP] = NV_DEVICE_V0_DISABLE_VP, 237 [NVDEV_ENGINE_CIPHER] = NV_DEVICE_V0_DISABLE_CIPHER, 238 [NVDEV_ENGINE_BSP] = NV_DEVICE_V0_DISABLE_BSP, 239 [NVDEV_ENGINE_MSPPP] = NV_DEVICE_V0_DISABLE_MSPPP, 240 [NVDEV_ENGINE_CE0] = NV_DEVICE_V0_DISABLE_CE0, 241 [NVDEV_ENGINE_CE1] = NV_DEVICE_V0_DISABLE_CE1, 242 [NVDEV_ENGINE_CE2] = NV_DEVICE_V0_DISABLE_CE2, 243 [NVDEV_ENGINE_VIC] = NV_DEVICE_V0_DISABLE_VIC, 244 [NVDEV_ENGINE_MSENC] = NV_DEVICE_V0_DISABLE_MSENC, 245 [NVDEV_ENGINE_DISP] = NV_DEVICE_V0_DISABLE_DISP, 246 [NVDEV_ENGINE_MSVLD] = NV_DEVICE_V0_DISABLE_MSVLD, 247 [NVDEV_ENGINE_SEC] = NV_DEVICE_V0_DISABLE_SEC, 248 [NVDEV_SUBDEV_NR] = 0, 249 }; 250 251 static void 252 nvkm_devobj_dtor(struct nvkm_object *object) 253 { 254 struct nvkm_devobj *devobj = (void *)object; 255 int i; 256 257 for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) 258 nvkm_object_ref(NULL, &devobj->subdev[i]); 259 260 nvkm_parent_destroy(&devobj->base); 261 } 262 263 static struct nvkm_oclass 264 nvkm_devobj_oclass_super = { 265 .handle = NV_DEVICE, 266 .ofuncs = &(struct nvkm_ofuncs) { 267 .dtor = nvkm_devobj_dtor, 268 .init = _nvkm_parent_init, 269 .fini = _nvkm_parent_fini, 270 .mthd = nvkm_devobj_mthd, 271 .map = nvkm_devobj_map, 272 .rd08 = nvkm_devobj_rd08, 273 .rd16 = nvkm_devobj_rd16, 274 .rd32 = nvkm_devobj_rd32, 275 .wr08 = nvkm_devobj_wr08, 276 .wr16 = nvkm_devobj_wr16, 277 .wr32 = nvkm_devobj_wr32, 278 } 279 }; 280 281 static int 282 nvkm_devobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 283 struct nvkm_oclass *oclass, void *data, u32 size, 284 struct nvkm_object **pobject) 285 { 286 union { 287 struct nv_device_v0 v0; 288 } *args = data; 289 struct nvkm_client *client = nv_client(parent); 290 struct nvkm_device *device; 291 struct nvkm_devobj *devobj; 292 u32 boot0, strap; 293 u64 disable, mmio_base, mmio_size; 294 void __iomem *map; 295 int ret, i, c; 296 297 nv_ioctl(parent, "create device size %d\n", size); 298 if (nvif_unpack(args->v0, 0, 0, false)) { 299 nv_ioctl(parent, "create device v%d device %016llx " 300 "disable %016llx debug0 %016llx\n", 301 args->v0.version, args->v0.device, 302 args->v0.disable, args->v0.debug0); 303 } else 304 return ret; 305 306 /* give priviledged clients register access */ 307 if (client->super) 308 oclass = &nvkm_devobj_oclass_super; 309 310 /* find the device subdev that matches what the client requested */ 311 device = nv_device(client->device); 312 if (args->v0.device != ~0) { 313 device = nvkm_device_find(args->v0.device); 314 if (!device) 315 return -ENODEV; 316 } 317 318 ret = nvkm_parent_create(parent, nv_object(device), oclass, 0, 319 nvkm_control_oclass, 320 (1ULL << NVDEV_ENGINE_DMAOBJ) | 321 (1ULL << NVDEV_ENGINE_FIFO) | 322 (1ULL << NVDEV_ENGINE_DISP) | 323 (1ULL << NVDEV_ENGINE_PM), &devobj); 324 *pobject = nv_object(devobj); 325 if (ret) 326 return ret; 327 328 mmio_base = nv_device_resource_start(device, 0); 329 mmio_size = nv_device_resource_len(device, 0); 330 331 /* translate api disable mask into internal mapping */ 332 disable = args->v0.debug0; 333 for (i = 0; i < NVDEV_SUBDEV_NR; i++) { 334 if (args->v0.disable & disable_map[i]) 335 disable |= (1ULL << i); 336 } 337 338 /* identify the chipset, and determine classes of subdev/engines */ 339 if (!(args->v0.disable & NV_DEVICE_V0_DISABLE_IDENTIFY) && 340 !device->card_type) { 341 map = ioremap(mmio_base, 0x102000); 342 if (map == NULL) 343 return -ENOMEM; 344 345 /* switch mmio to cpu's native endianness */ 346 #ifndef __BIG_ENDIAN 347 if (ioread32_native(map + 0x000004) != 0x00000000) { 348 #else 349 if (ioread32_native(map + 0x000004) == 0x00000000) { 350 #endif 351 iowrite32_native(0x01000001, map + 0x000004); 352 ioread32_native(map); 353 } 354 355 /* read boot0 and strapping information */ 356 boot0 = ioread32_native(map + 0x000000); 357 strap = ioread32_native(map + 0x101000); 358 iounmap(map); 359 360 /* determine chipset and derive architecture from it */ 361 if ((boot0 & 0x1f000000) > 0) { 362 device->chipset = (boot0 & 0x1ff00000) >> 20; 363 device->chiprev = (boot0 & 0x000000ff); 364 switch (device->chipset & 0x1f0) { 365 case 0x010: { 366 if (0x461 & (1 << (device->chipset & 0xf))) 367 device->card_type = NV_10; 368 else 369 device->card_type = NV_11; 370 device->chiprev = 0x00; 371 break; 372 } 373 case 0x020: device->card_type = NV_20; break; 374 case 0x030: device->card_type = NV_30; break; 375 case 0x040: 376 case 0x060: device->card_type = NV_40; break; 377 case 0x050: 378 case 0x080: 379 case 0x090: 380 case 0x0a0: device->card_type = NV_50; break; 381 case 0x0c0: 382 case 0x0d0: device->card_type = NV_C0; break; 383 case 0x0e0: 384 case 0x0f0: 385 case 0x100: device->card_type = NV_E0; break; 386 case 0x110: 387 case 0x120: device->card_type = GM100; break; 388 default: 389 break; 390 } 391 } else 392 if ((boot0 & 0xff00fff0) == 0x20004000) { 393 if (boot0 & 0x00f00000) 394 device->chipset = 0x05; 395 else 396 device->chipset = 0x04; 397 device->card_type = NV_04; 398 } 399 400 switch (device->card_type) { 401 case NV_04: ret = nv04_identify(device); break; 402 case NV_10: 403 case NV_11: ret = nv10_identify(device); break; 404 case NV_20: ret = nv20_identify(device); break; 405 case NV_30: ret = nv30_identify(device); break; 406 case NV_40: ret = nv40_identify(device); break; 407 case NV_50: ret = nv50_identify(device); break; 408 case NV_C0: ret = gf100_identify(device); break; 409 case NV_E0: ret = gk104_identify(device); break; 410 case GM100: ret = gm100_identify(device); break; 411 default: 412 ret = -EINVAL; 413 break; 414 } 415 416 if (ret) { 417 nv_error(device, "unknown chipset, 0x%08x\n", boot0); 418 return ret; 419 } 420 421 nv_info(device, "BOOT0 : 0x%08x\n", boot0); 422 nv_info(device, "Chipset: %s (NV%02X)\n", 423 device->cname, device->chipset); 424 nv_info(device, "Family : NV%02X\n", device->card_type); 425 426 /* determine frequency of timing crystal */ 427 if ( device->card_type <= NV_10 || device->chipset < 0x17 || 428 (device->chipset >= 0x20 && device->chipset < 0x25)) 429 strap &= 0x00000040; 430 else 431 strap &= 0x00400040; 432 433 switch (strap) { 434 case 0x00000000: device->crystal = 13500; break; 435 case 0x00000040: device->crystal = 14318; break; 436 case 0x00400000: device->crystal = 27000; break; 437 case 0x00400040: device->crystal = 25000; break; 438 } 439 440 nv_debug(device, "crystal freq: %dKHz\n", device->crystal); 441 } else 442 if ( (args->v0.disable & NV_DEVICE_V0_DISABLE_IDENTIFY)) { 443 device->cname = "NULL"; 444 device->oclass[NVDEV_SUBDEV_VBIOS] = &nvkm_bios_oclass; 445 } 446 447 if (!(args->v0.disable & NV_DEVICE_V0_DISABLE_MMIO) && !device->pri) { 448 device->pri = ioremap(mmio_base, mmio_size); 449 if (!device->pri) { 450 nv_error(device, "unable to map device registers\n"); 451 return -ENOMEM; 452 } 453 } 454 455 /* ensure requested subsystems are available for use */ 456 for (i = 1, c = 1; i < NVDEV_SUBDEV_NR; i++) { 457 if (!(oclass = device->oclass[i]) || (disable & (1ULL << i))) 458 continue; 459 460 if (device->subdev[i]) { 461 nvkm_object_ref(device->subdev[i], &devobj->subdev[i]); 462 continue; 463 } 464 465 #define _(s,m) case s: \ 466 ret = nvkm_object_ctor(nv_object(device), NULL, oclass, NULL, \ 467 (s), (struct nvkm_object **)&device->m);\ 468 if (ret == -ENODEV) \ 469 continue; \ 470 if (ret) \ 471 return ret; \ 472 devobj->subdev[s] = (struct nvkm_object *)device->m; \ 473 device->subdev[s] = devobj->subdev[s]; \ 474 break 475 476 switch (i) { 477 _(NVDEV_SUBDEV_BAR , bar); 478 _(NVDEV_SUBDEV_VBIOS , bios); 479 _(NVDEV_SUBDEV_BUS , bus); 480 _(NVDEV_SUBDEV_CLK , clk); 481 _(NVDEV_SUBDEV_DEVINIT, devinit); 482 _(NVDEV_SUBDEV_FB , fb); 483 _(NVDEV_SUBDEV_FUSE , fuse); 484 _(NVDEV_SUBDEV_GPIO , gpio); 485 _(NVDEV_SUBDEV_I2C , i2c); 486 _(NVDEV_SUBDEV_IBUS , ibus); 487 _(NVDEV_SUBDEV_INSTMEM, imem); 488 _(NVDEV_SUBDEV_LTC , ltc); 489 _(NVDEV_SUBDEV_MC , mc); 490 _(NVDEV_SUBDEV_MMU , mmu); 491 _(NVDEV_SUBDEV_MXM , mxm); 492 _(NVDEV_SUBDEV_PMU , pmu); 493 _(NVDEV_SUBDEV_THERM , therm); 494 _(NVDEV_SUBDEV_TIMER , timer); 495 _(NVDEV_SUBDEV_VOLT , volt); 496 _(NVDEV_ENGINE_BSP , bsp); 497 _(NVDEV_ENGINE_CE0 , ce[0]); 498 _(NVDEV_ENGINE_CE1 , ce[1]); 499 _(NVDEV_ENGINE_CE2 , ce[2]); 500 _(NVDEV_ENGINE_CIPHER , cipher); 501 _(NVDEV_ENGINE_DISP , disp); 502 _(NVDEV_ENGINE_DMAOBJ , dma); 503 _(NVDEV_ENGINE_FIFO , fifo); 504 _(NVDEV_ENGINE_GR , gr); 505 _(NVDEV_ENGINE_IFB , ifb); 506 _(NVDEV_ENGINE_ME , me); 507 _(NVDEV_ENGINE_MPEG , mpeg); 508 _(NVDEV_ENGINE_MSENC , msenc); 509 _(NVDEV_ENGINE_MSPDEC , mspdec); 510 _(NVDEV_ENGINE_MSPPP , msppp); 511 _(NVDEV_ENGINE_MSVLD , msvld); 512 _(NVDEV_ENGINE_PM , pm); 513 _(NVDEV_ENGINE_SEC , sec); 514 _(NVDEV_ENGINE_SW , sw); 515 _(NVDEV_ENGINE_VIC , vic); 516 _(NVDEV_ENGINE_VP , vp); 517 default: 518 WARN_ON(1); 519 continue; 520 } 521 #undef _ 522 523 /* note: can't init *any* subdevs until devinit has been run 524 * due to not knowing exactly what the vbios init tables will 525 * mess with. devinit also can't be run until all of its 526 * dependencies have been created. 527 * 528 * this code delays init of any subdev until all of devinit's 529 * dependencies have been created, and then initialises each 530 * subdev in turn as they're created. 531 */ 532 while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) { 533 struct nvkm_object *subdev = devobj->subdev[c++]; 534 if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) { 535 ret = nvkm_object_inc(subdev); 536 if (ret) 537 return ret; 538 atomic_dec(&nv_object(device)->usecount); 539 } else 540 if (subdev) { 541 nvkm_subdev_reset(subdev); 542 } 543 } 544 } 545 546 return 0; 547 } 548 549 static struct nvkm_ofuncs 550 nvkm_devobj_ofuncs = { 551 .ctor = nvkm_devobj_ctor, 552 .dtor = nvkm_devobj_dtor, 553 .init = _nvkm_parent_init, 554 .fini = _nvkm_parent_fini, 555 .mthd = nvkm_devobj_mthd, 556 }; 557 558 /****************************************************************************** 559 * nvkm_device: engine functions 560 *****************************************************************************/ 561 562 struct nvkm_device * 563 nv_device(void *obj) 564 { 565 struct nvkm_object *device = nv_object(obj); 566 if (device->engine == NULL) { 567 while (device && device->parent) 568 device = device->parent; 569 } else { 570 device = &nv_object(obj)->engine->subdev.object; 571 if (device && device->parent) 572 device = device->parent; 573 } 574 #if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA 575 if (unlikely(!device)) 576 nv_assert("BAD CAST -> NvDevice, 0x%08x\n", nv_hclass(obj)); 577 #endif 578 return (void *)device; 579 } 580 581 static struct nvkm_oclass 582 nvkm_device_sclass[] = { 583 { 0x0080, &nvkm_devobj_ofuncs }, 584 {} 585 }; 586 587 static int 588 nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size, 589 struct nvkm_notify *notify) 590 { 591 if (!WARN_ON(size != 0)) { 592 notify->size = 0; 593 notify->types = 1; 594 notify->index = 0; 595 return 0; 596 } 597 return -EINVAL; 598 } 599 600 static const struct nvkm_event_func 601 nvkm_device_event_func = { 602 .ctor = nvkm_device_event_ctor, 603 }; 604 605 static int 606 nvkm_device_fini(struct nvkm_object *object, bool suspend) 607 { 608 struct nvkm_device *device = (void *)object; 609 struct nvkm_object *subdev; 610 int ret, i; 611 612 for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) { 613 if ((subdev = device->subdev[i])) { 614 if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { 615 ret = nvkm_object_dec(subdev, suspend); 616 if (ret && suspend) 617 goto fail; 618 } 619 } 620 } 621 622 ret = nvkm_acpi_fini(device, suspend); 623 fail: 624 for (; ret && i < NVDEV_SUBDEV_NR; i++) { 625 if ((subdev = device->subdev[i])) { 626 if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { 627 ret = nvkm_object_inc(subdev); 628 if (ret) { 629 /* XXX */ 630 } 631 } 632 } 633 } 634 635 return ret; 636 } 637 638 static int 639 nvkm_device_init(struct nvkm_object *object) 640 { 641 struct nvkm_device *device = (void *)object; 642 struct nvkm_object *subdev; 643 int ret, i = 0; 644 645 ret = nvkm_acpi_init(device); 646 if (ret) 647 goto fail; 648 649 for (i = 0; i < NVDEV_SUBDEV_NR; i++) { 650 if ((subdev = device->subdev[i])) { 651 if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { 652 ret = nvkm_object_inc(subdev); 653 if (ret) 654 goto fail; 655 } else { 656 nvkm_subdev_reset(subdev); 657 } 658 } 659 } 660 661 ret = 0; 662 fail: 663 for (--i; ret && i >= 0; i--) { 664 if ((subdev = device->subdev[i])) { 665 if (!nv_iclass(subdev, NV_ENGINE_CLASS)) 666 nvkm_object_dec(subdev, false); 667 } 668 } 669 670 if (ret) 671 nvkm_acpi_fini(device, false); 672 return ret; 673 } 674 675 static void 676 nvkm_device_dtor(struct nvkm_object *object) 677 { 678 struct nvkm_device *device = (void *)object; 679 680 nvkm_event_fini(&device->event); 681 682 mutex_lock(&nv_devices_mutex); 683 list_del(&device->head); 684 mutex_unlock(&nv_devices_mutex); 685 686 if (device->pri) 687 iounmap(device->pri); 688 689 nvkm_engine_destroy(&device->engine); 690 } 691 692 resource_size_t 693 nv_device_resource_start(struct nvkm_device *device, unsigned int bar) 694 { 695 if (nv_device_is_pci(device)) { 696 return pci_resource_start(device->pdev, bar); 697 } else { 698 struct resource *res; 699 res = platform_get_resource(device->platformdev, 700 IORESOURCE_MEM, bar); 701 if (!res) 702 return 0; 703 return res->start; 704 } 705 } 706 707 resource_size_t 708 nv_device_resource_len(struct nvkm_device *device, unsigned int bar) 709 { 710 if (nv_device_is_pci(device)) { 711 return pci_resource_len(device->pdev, bar); 712 } else { 713 struct resource *res; 714 res = platform_get_resource(device->platformdev, 715 IORESOURCE_MEM, bar); 716 if (!res) 717 return 0; 718 return resource_size(res); 719 } 720 } 721 722 int 723 nv_device_get_irq(struct nvkm_device *device, bool stall) 724 { 725 if (nv_device_is_pci(device)) { 726 return device->pdev->irq; 727 } else { 728 return platform_get_irq_byname(device->platformdev, 729 stall ? "stall" : "nonstall"); 730 } 731 } 732 733 static struct nvkm_oclass 734 nvkm_device_oclass = { 735 .handle = NV_ENGINE(DEVICE, 0x00), 736 .ofuncs = &(struct nvkm_ofuncs) { 737 .dtor = nvkm_device_dtor, 738 .init = nvkm_device_init, 739 .fini = nvkm_device_fini, 740 }, 741 }; 742 743 int 744 nvkm_device_create_(void *dev, enum nv_bus_type type, u64 name, 745 const char *sname, const char *cfg, const char *dbg, 746 int length, void **pobject) 747 { 748 struct nvkm_device *device; 749 int ret = -EEXIST; 750 751 mutex_lock(&nv_devices_mutex); 752 list_for_each_entry(device, &nv_devices, head) { 753 if (device->handle == name) 754 goto done; 755 } 756 757 ret = nvkm_engine_create_(NULL, NULL, &nvkm_device_oclass, true, 758 "DEVICE", "device", length, pobject); 759 device = *pobject; 760 if (ret) 761 goto done; 762 763 switch (type) { 764 case NVKM_BUS_PCI: 765 device->pdev = dev; 766 device->dev = &device->pdev->dev; 767 break; 768 case NVKM_BUS_PLATFORM: 769 device->platformdev = dev; 770 device->dev = &device->platformdev->dev; 771 break; 772 } 773 device->handle = name; 774 device->cfgopt = cfg; 775 device->dbgopt = dbg; 776 device->name = sname; 777 778 nv_subdev(device)->debug = nvkm_dbgopt(device->dbgopt, "DEVICE"); 779 nv_engine(device)->sclass = nvkm_device_sclass; 780 list_add_tail(&device->head, &nv_devices); 781 782 ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event); 783 done: 784 mutex_unlock(&nv_devices_mutex); 785 return ret; 786 } 787