1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "priv.h" 25 #include "acpi.h" 26 27 #include <core/notify.h> 28 #include <core/option.h> 29 30 #include <subdev/bios.h> 31 #include <subdev/therm.h> 32 33 static DEFINE_MUTEX(nv_devices_mutex); 34 static LIST_HEAD(nv_devices); 35 36 static struct nvkm_device * 37 nvkm_device_find_locked(u64 handle) 38 { 39 struct nvkm_device *device; 40 list_for_each_entry(device, &nv_devices, head) { 41 if (device->handle == handle) 42 return device; 43 } 44 return NULL; 45 } 46 47 struct nvkm_device * 48 nvkm_device_find(u64 handle) 49 { 50 struct nvkm_device *device; 51 mutex_lock(&nv_devices_mutex); 52 device = nvkm_device_find_locked(handle); 53 mutex_unlock(&nv_devices_mutex); 54 return device; 55 } 56 57 int 58 nvkm_device_list(u64 *name, int size) 59 { 60 struct nvkm_device *device; 61 int nr = 0; 62 mutex_lock(&nv_devices_mutex); 63 list_for_each_entry(device, &nv_devices, head) { 64 if (nr++ < size) 65 name[nr - 1] = device->handle; 66 } 67 mutex_unlock(&nv_devices_mutex); 68 return nr; 69 } 70 71 static const struct nvkm_device_chip 72 null_chipset = { 73 .name = "NULL", 74 .bios = nvkm_bios_new, 75 }; 76 77 static const struct nvkm_device_chip 78 nv4_chipset = { 79 .name = "NV04", 80 .bios = nvkm_bios_new, 81 .bus = nv04_bus_new, 82 .clk = nv04_clk_new, 83 .devinit = nv04_devinit_new, 84 .fb = nv04_fb_new, 85 .i2c = nv04_i2c_new, 86 .imem = nv04_instmem_new, 87 .mc = nv04_mc_new, 88 .mmu = nv04_mmu_new, 89 .pci = nv04_pci_new, 90 .timer = nv04_timer_new, 91 .disp = nv04_disp_new, 92 .dma = nv04_dma_new, 93 .fifo = nv04_fifo_new, 94 .gr = nv04_gr_new, 95 .sw = nv04_sw_new, 96 }; 97 98 static const struct nvkm_device_chip 99 nv5_chipset = { 100 .name = "NV05", 101 .bios = nvkm_bios_new, 102 .bus = nv04_bus_new, 103 .clk = nv04_clk_new, 104 .devinit = nv05_devinit_new, 105 .fb = nv04_fb_new, 106 .i2c = nv04_i2c_new, 107 .imem = nv04_instmem_new, 108 .mc = nv04_mc_new, 109 .mmu = nv04_mmu_new, 110 .pci = nv04_pci_new, 111 .timer = nv04_timer_new, 112 .disp = nv04_disp_new, 113 .dma = nv04_dma_new, 114 .fifo = nv04_fifo_new, 115 .gr = nv04_gr_new, 116 .sw = nv04_sw_new, 117 }; 118 119 static const struct nvkm_device_chip 120 nv10_chipset = { 121 .name = "NV10", 122 .bios = nvkm_bios_new, 123 .bus = nv04_bus_new, 124 .clk = nv04_clk_new, 125 .devinit = nv10_devinit_new, 126 .fb = nv10_fb_new, 127 .gpio = nv10_gpio_new, 128 .i2c = nv04_i2c_new, 129 .imem = nv04_instmem_new, 130 .mc = nv04_mc_new, 131 .mmu = nv04_mmu_new, 132 .pci = nv04_pci_new, 133 .timer = nv04_timer_new, 134 .disp = nv04_disp_new, 135 .dma = nv04_dma_new, 136 .gr = nv10_gr_new, 137 }; 138 139 static const struct nvkm_device_chip 140 nv11_chipset = { 141 .name = "NV11", 142 .bios = nvkm_bios_new, 143 .bus = nv04_bus_new, 144 .clk = nv04_clk_new, 145 .devinit = nv10_devinit_new, 146 .fb = nv10_fb_new, 147 .gpio = nv10_gpio_new, 148 .i2c = nv04_i2c_new, 149 .imem = nv04_instmem_new, 150 .mc = nv11_mc_new, 151 .mmu = nv04_mmu_new, 152 .pci = nv04_pci_new, 153 .timer = nv04_timer_new, 154 .disp = nv04_disp_new, 155 .dma = nv04_dma_new, 156 .fifo = nv10_fifo_new, 157 .gr = nv15_gr_new, 158 .sw = nv10_sw_new, 159 }; 160 161 static const struct nvkm_device_chip 162 nv15_chipset = { 163 .name = "NV15", 164 .bios = nvkm_bios_new, 165 .bus = nv04_bus_new, 166 .clk = nv04_clk_new, 167 .devinit = nv10_devinit_new, 168 .fb = nv10_fb_new, 169 .gpio = nv10_gpio_new, 170 .i2c = nv04_i2c_new, 171 .imem = nv04_instmem_new, 172 .mc = nv04_mc_new, 173 .mmu = nv04_mmu_new, 174 .pci = nv04_pci_new, 175 .timer = nv04_timer_new, 176 .disp = nv04_disp_new, 177 .dma = nv04_dma_new, 178 .fifo = nv10_fifo_new, 179 .gr = nv15_gr_new, 180 .sw = nv10_sw_new, 181 }; 182 183 static const struct nvkm_device_chip 184 nv17_chipset = { 185 .name = "NV17", 186 .bios = nvkm_bios_new, 187 .bus = nv04_bus_new, 188 .clk = nv04_clk_new, 189 .devinit = nv10_devinit_new, 190 .fb = nv10_fb_new, 191 .gpio = nv10_gpio_new, 192 .i2c = nv04_i2c_new, 193 .imem = nv04_instmem_new, 194 .mc = nv17_mc_new, 195 .mmu = nv04_mmu_new, 196 .pci = nv04_pci_new, 197 .timer = nv04_timer_new, 198 .disp = nv04_disp_new, 199 .dma = nv04_dma_new, 200 .fifo = nv17_fifo_new, 201 .gr = nv17_gr_new, 202 .sw = nv10_sw_new, 203 }; 204 205 static const struct nvkm_device_chip 206 nv18_chipset = { 207 .name = "NV18", 208 .bios = nvkm_bios_new, 209 .bus = nv04_bus_new, 210 .clk = nv04_clk_new, 211 .devinit = nv10_devinit_new, 212 .fb = nv10_fb_new, 213 .gpio = nv10_gpio_new, 214 .i2c = nv04_i2c_new, 215 .imem = nv04_instmem_new, 216 .mc = nv17_mc_new, 217 .mmu = nv04_mmu_new, 218 .pci = nv04_pci_new, 219 .timer = nv04_timer_new, 220 .disp = nv04_disp_new, 221 .dma = nv04_dma_new, 222 .fifo = nv17_fifo_new, 223 .gr = nv17_gr_new, 224 .sw = nv10_sw_new, 225 }; 226 227 static const struct nvkm_device_chip 228 nv1a_chipset = { 229 .name = "nForce", 230 .bios = nvkm_bios_new, 231 .bus = nv04_bus_new, 232 .clk = nv04_clk_new, 233 .devinit = nv1a_devinit_new, 234 .fb = nv1a_fb_new, 235 .gpio = nv10_gpio_new, 236 .i2c = nv04_i2c_new, 237 .imem = nv04_instmem_new, 238 .mc = nv04_mc_new, 239 .mmu = nv04_mmu_new, 240 .pci = nv04_pci_new, 241 .timer = nv04_timer_new, 242 .disp = nv04_disp_new, 243 .dma = nv04_dma_new, 244 .fifo = nv10_fifo_new, 245 .gr = nv15_gr_new, 246 .sw = nv10_sw_new, 247 }; 248 249 static const struct nvkm_device_chip 250 nv1f_chipset = { 251 .name = "nForce2", 252 .bios = nvkm_bios_new, 253 .bus = nv04_bus_new, 254 .clk = nv04_clk_new, 255 .devinit = nv1a_devinit_new, 256 .fb = nv1a_fb_new, 257 .gpio = nv10_gpio_new, 258 .i2c = nv04_i2c_new, 259 .imem = nv04_instmem_new, 260 .mc = nv17_mc_new, 261 .mmu = nv04_mmu_new, 262 .pci = nv04_pci_new, 263 .timer = nv04_timer_new, 264 .disp = nv04_disp_new, 265 .dma = nv04_dma_new, 266 .fifo = nv17_fifo_new, 267 .gr = nv17_gr_new, 268 .sw = nv10_sw_new, 269 }; 270 271 static const struct nvkm_device_chip 272 nv20_chipset = { 273 .name = "NV20", 274 .bios = nvkm_bios_new, 275 .bus = nv04_bus_new, 276 .clk = nv04_clk_new, 277 .devinit = nv20_devinit_new, 278 .fb = nv20_fb_new, 279 .gpio = nv10_gpio_new, 280 .i2c = nv04_i2c_new, 281 .imem = nv04_instmem_new, 282 .mc = nv17_mc_new, 283 .mmu = nv04_mmu_new, 284 .pci = nv04_pci_new, 285 .timer = nv04_timer_new, 286 .disp = nv04_disp_new, 287 .dma = nv04_dma_new, 288 .fifo = nv17_fifo_new, 289 .gr = nv20_gr_new, 290 .sw = nv10_sw_new, 291 }; 292 293 static const struct nvkm_device_chip 294 nv25_chipset = { 295 .name = "NV25", 296 .bios = nvkm_bios_new, 297 .bus = nv04_bus_new, 298 .clk = nv04_clk_new, 299 .devinit = nv20_devinit_new, 300 .fb = nv25_fb_new, 301 .gpio = nv10_gpio_new, 302 .i2c = nv04_i2c_new, 303 .imem = nv04_instmem_new, 304 .mc = nv17_mc_new, 305 .mmu = nv04_mmu_new, 306 .pci = nv04_pci_new, 307 .timer = nv04_timer_new, 308 .disp = nv04_disp_new, 309 .dma = nv04_dma_new, 310 .fifo = nv17_fifo_new, 311 .gr = nv25_gr_new, 312 .sw = nv10_sw_new, 313 }; 314 315 static const struct nvkm_device_chip 316 nv28_chipset = { 317 .name = "NV28", 318 .bios = nvkm_bios_new, 319 .bus = nv04_bus_new, 320 .clk = nv04_clk_new, 321 .devinit = nv20_devinit_new, 322 .fb = nv25_fb_new, 323 .gpio = nv10_gpio_new, 324 .i2c = nv04_i2c_new, 325 .imem = nv04_instmem_new, 326 .mc = nv17_mc_new, 327 .mmu = nv04_mmu_new, 328 .pci = nv04_pci_new, 329 .timer = nv04_timer_new, 330 .disp = nv04_disp_new, 331 .dma = nv04_dma_new, 332 .fifo = nv17_fifo_new, 333 .gr = nv25_gr_new, 334 .sw = nv10_sw_new, 335 }; 336 337 static const struct nvkm_device_chip 338 nv2a_chipset = { 339 .name = "NV2A", 340 .bios = nvkm_bios_new, 341 .bus = nv04_bus_new, 342 .clk = nv04_clk_new, 343 .devinit = nv20_devinit_new, 344 .fb = nv25_fb_new, 345 .gpio = nv10_gpio_new, 346 .i2c = nv04_i2c_new, 347 .imem = nv04_instmem_new, 348 .mc = nv17_mc_new, 349 .mmu = nv04_mmu_new, 350 .pci = nv04_pci_new, 351 .timer = nv04_timer_new, 352 .disp = nv04_disp_new, 353 .dma = nv04_dma_new, 354 .fifo = nv17_fifo_new, 355 .gr = nv2a_gr_new, 356 .sw = nv10_sw_new, 357 }; 358 359 static const struct nvkm_device_chip 360 nv30_chipset = { 361 .name = "NV30", 362 .bios = nvkm_bios_new, 363 .bus = nv04_bus_new, 364 .clk = nv04_clk_new, 365 .devinit = nv20_devinit_new, 366 .fb = nv30_fb_new, 367 .gpio = nv10_gpio_new, 368 .i2c = nv04_i2c_new, 369 .imem = nv04_instmem_new, 370 .mc = nv17_mc_new, 371 .mmu = nv04_mmu_new, 372 .pci = nv04_pci_new, 373 .timer = nv04_timer_new, 374 .disp = nv04_disp_new, 375 .dma = nv04_dma_new, 376 .fifo = nv17_fifo_new, 377 .gr = nv30_gr_new, 378 .sw = nv10_sw_new, 379 }; 380 381 static const struct nvkm_device_chip 382 nv31_chipset = { 383 .name = "NV31", 384 .bios = nvkm_bios_new, 385 .bus = nv31_bus_new, 386 .clk = nv04_clk_new, 387 .devinit = nv20_devinit_new, 388 .fb = nv30_fb_new, 389 .gpio = nv10_gpio_new, 390 .i2c = nv04_i2c_new, 391 .imem = nv04_instmem_new, 392 .mc = nv17_mc_new, 393 .mmu = nv04_mmu_new, 394 .pci = nv04_pci_new, 395 .timer = nv04_timer_new, 396 .disp = nv04_disp_new, 397 .dma = nv04_dma_new, 398 .fifo = nv17_fifo_new, 399 .gr = nv30_gr_new, 400 .mpeg = nv31_mpeg_new, 401 .sw = nv10_sw_new, 402 }; 403 404 static const struct nvkm_device_chip 405 nv34_chipset = { 406 .name = "NV34", 407 .bios = nvkm_bios_new, 408 .bus = nv31_bus_new, 409 .clk = nv04_clk_new, 410 .devinit = nv10_devinit_new, 411 .fb = nv10_fb_new, 412 .gpio = nv10_gpio_new, 413 .i2c = nv04_i2c_new, 414 .imem = nv04_instmem_new, 415 .mc = nv17_mc_new, 416 .mmu = nv04_mmu_new, 417 .pci = nv04_pci_new, 418 .timer = nv04_timer_new, 419 .disp = nv04_disp_new, 420 .dma = nv04_dma_new, 421 .fifo = nv17_fifo_new, 422 .gr = nv34_gr_new, 423 .mpeg = nv31_mpeg_new, 424 .sw = nv10_sw_new, 425 }; 426 427 static const struct nvkm_device_chip 428 nv35_chipset = { 429 .name = "NV35", 430 .bios = nvkm_bios_new, 431 .bus = nv04_bus_new, 432 .clk = nv04_clk_new, 433 .devinit = nv20_devinit_new, 434 .fb = nv35_fb_new, 435 .gpio = nv10_gpio_new, 436 .i2c = nv04_i2c_new, 437 .imem = nv04_instmem_new, 438 .mc = nv17_mc_new, 439 .mmu = nv04_mmu_new, 440 .pci = nv04_pci_new, 441 .timer = nv04_timer_new, 442 .disp = nv04_disp_new, 443 .dma = nv04_dma_new, 444 .fifo = nv17_fifo_new, 445 .gr = nv35_gr_new, 446 .sw = nv10_sw_new, 447 }; 448 449 static const struct nvkm_device_chip 450 nv36_chipset = { 451 .name = "NV36", 452 .bios = nvkm_bios_new, 453 .bus = nv31_bus_new, 454 .clk = nv04_clk_new, 455 .devinit = nv20_devinit_new, 456 .fb = nv36_fb_new, 457 .gpio = nv10_gpio_new, 458 .i2c = nv04_i2c_new, 459 .imem = nv04_instmem_new, 460 .mc = nv17_mc_new, 461 .mmu = nv04_mmu_new, 462 .pci = nv04_pci_new, 463 .timer = nv04_timer_new, 464 .disp = nv04_disp_new, 465 .dma = nv04_dma_new, 466 .fifo = nv17_fifo_new, 467 .gr = nv35_gr_new, 468 .mpeg = nv31_mpeg_new, 469 .sw = nv10_sw_new, 470 }; 471 472 static const struct nvkm_device_chip 473 nv40_chipset = { 474 .name = "NV40", 475 .bios = nvkm_bios_new, 476 .bus = nv31_bus_new, 477 .clk = nv40_clk_new, 478 .devinit = nv1a_devinit_new, 479 .fb = nv40_fb_new, 480 .gpio = nv10_gpio_new, 481 .i2c = nv04_i2c_new, 482 .imem = nv40_instmem_new, 483 .mc = nv17_mc_new, 484 .mmu = nv04_mmu_new, 485 .pci = nv40_pci_new, 486 .therm = nv40_therm_new, 487 .timer = nv40_timer_new, 488 .volt = nv40_volt_new, 489 .disp = nv04_disp_new, 490 .dma = nv04_dma_new, 491 .fifo = nv40_fifo_new, 492 .gr = nv40_gr_new, 493 .mpeg = nv40_mpeg_new, 494 .pm = nv40_pm_new, 495 .sw = nv10_sw_new, 496 }; 497 498 static const struct nvkm_device_chip 499 nv41_chipset = { 500 .name = "NV41", 501 .bios = nvkm_bios_new, 502 .bus = nv31_bus_new, 503 .clk = nv40_clk_new, 504 .devinit = nv1a_devinit_new, 505 .fb = nv41_fb_new, 506 .gpio = nv10_gpio_new, 507 .i2c = nv04_i2c_new, 508 .imem = nv40_instmem_new, 509 .mc = nv17_mc_new, 510 .mmu = nv41_mmu_new, 511 .pci = nv40_pci_new, 512 .therm = nv40_therm_new, 513 .timer = nv41_timer_new, 514 .volt = nv40_volt_new, 515 .disp = nv04_disp_new, 516 .dma = nv04_dma_new, 517 .fifo = nv40_fifo_new, 518 .gr = nv40_gr_new, 519 .mpeg = nv40_mpeg_new, 520 .pm = nv40_pm_new, 521 .sw = nv10_sw_new, 522 }; 523 524 static const struct nvkm_device_chip 525 nv42_chipset = { 526 .name = "NV42", 527 .bios = nvkm_bios_new, 528 .bus = nv31_bus_new, 529 .clk = nv40_clk_new, 530 .devinit = nv1a_devinit_new, 531 .fb = nv41_fb_new, 532 .gpio = nv10_gpio_new, 533 .i2c = nv04_i2c_new, 534 .imem = nv40_instmem_new, 535 .mc = nv17_mc_new, 536 .mmu = nv41_mmu_new, 537 .pci = nv40_pci_new, 538 .therm = nv40_therm_new, 539 .timer = nv41_timer_new, 540 .volt = nv40_volt_new, 541 .disp = nv04_disp_new, 542 .dma = nv04_dma_new, 543 .fifo = nv40_fifo_new, 544 .gr = nv40_gr_new, 545 .mpeg = nv40_mpeg_new, 546 .pm = nv40_pm_new, 547 .sw = nv10_sw_new, 548 }; 549 550 static const struct nvkm_device_chip 551 nv43_chipset = { 552 .name = "NV43", 553 .bios = nvkm_bios_new, 554 .bus = nv31_bus_new, 555 .clk = nv40_clk_new, 556 .devinit = nv1a_devinit_new, 557 .fb = nv41_fb_new, 558 .gpio = nv10_gpio_new, 559 .i2c = nv04_i2c_new, 560 .imem = nv40_instmem_new, 561 .mc = nv17_mc_new, 562 .mmu = nv41_mmu_new, 563 .pci = nv40_pci_new, 564 .therm = nv40_therm_new, 565 .timer = nv41_timer_new, 566 .volt = nv40_volt_new, 567 .disp = nv04_disp_new, 568 .dma = nv04_dma_new, 569 .fifo = nv40_fifo_new, 570 .gr = nv40_gr_new, 571 .mpeg = nv40_mpeg_new, 572 .pm = nv40_pm_new, 573 .sw = nv10_sw_new, 574 }; 575 576 static const struct nvkm_device_chip 577 nv44_chipset = { 578 .name = "NV44", 579 .bios = nvkm_bios_new, 580 .bus = nv31_bus_new, 581 .clk = nv40_clk_new, 582 .devinit = nv1a_devinit_new, 583 .fb = nv44_fb_new, 584 .gpio = nv10_gpio_new, 585 .i2c = nv04_i2c_new, 586 .imem = nv40_instmem_new, 587 .mc = nv44_mc_new, 588 .mmu = nv44_mmu_new, 589 .pci = nv40_pci_new, 590 .therm = nv40_therm_new, 591 .timer = nv41_timer_new, 592 .volt = nv40_volt_new, 593 .disp = nv04_disp_new, 594 .dma = nv04_dma_new, 595 .fifo = nv40_fifo_new, 596 .gr = nv44_gr_new, 597 .mpeg = nv44_mpeg_new, 598 .pm = nv40_pm_new, 599 .sw = nv10_sw_new, 600 }; 601 602 static const struct nvkm_device_chip 603 nv45_chipset = { 604 .name = "NV45", 605 .bios = nvkm_bios_new, 606 .bus = nv31_bus_new, 607 .clk = nv40_clk_new, 608 .devinit = nv1a_devinit_new, 609 .fb = nv40_fb_new, 610 .gpio = nv10_gpio_new, 611 .i2c = nv04_i2c_new, 612 .imem = nv40_instmem_new, 613 .mc = nv17_mc_new, 614 .mmu = nv04_mmu_new, 615 .pci = nv40_pci_new, 616 .therm = nv40_therm_new, 617 .timer = nv41_timer_new, 618 .volt = nv40_volt_new, 619 .disp = nv04_disp_new, 620 .dma = nv04_dma_new, 621 .fifo = nv40_fifo_new, 622 .gr = nv40_gr_new, 623 .mpeg = nv44_mpeg_new, 624 .pm = nv40_pm_new, 625 .sw = nv10_sw_new, 626 }; 627 628 static const struct nvkm_device_chip 629 nv46_chipset = { 630 .name = "G72", 631 .bios = nvkm_bios_new, 632 .bus = nv31_bus_new, 633 .clk = nv40_clk_new, 634 .devinit = nv1a_devinit_new, 635 .fb = nv46_fb_new, 636 .gpio = nv10_gpio_new, 637 .i2c = nv04_i2c_new, 638 .imem = nv40_instmem_new, 639 .mc = nv44_mc_new, 640 .mmu = nv44_mmu_new, 641 .pci = nv46_pci_new, 642 .therm = nv40_therm_new, 643 .timer = nv41_timer_new, 644 .volt = nv40_volt_new, 645 .disp = nv04_disp_new, 646 .dma = nv04_dma_new, 647 .fifo = nv40_fifo_new, 648 .gr = nv44_gr_new, 649 .mpeg = nv44_mpeg_new, 650 .pm = nv40_pm_new, 651 .sw = nv10_sw_new, 652 }; 653 654 static const struct nvkm_device_chip 655 nv47_chipset = { 656 .name = "G70", 657 .bios = nvkm_bios_new, 658 .bus = nv31_bus_new, 659 .clk = nv40_clk_new, 660 .devinit = nv1a_devinit_new, 661 .fb = nv47_fb_new, 662 .gpio = nv10_gpio_new, 663 .i2c = nv04_i2c_new, 664 .imem = nv40_instmem_new, 665 .mc = nv17_mc_new, 666 .mmu = nv41_mmu_new, 667 .pci = nv40_pci_new, 668 .therm = nv40_therm_new, 669 .timer = nv41_timer_new, 670 .volt = nv40_volt_new, 671 .disp = nv04_disp_new, 672 .dma = nv04_dma_new, 673 .fifo = nv40_fifo_new, 674 .gr = nv40_gr_new, 675 .mpeg = nv44_mpeg_new, 676 .pm = nv40_pm_new, 677 .sw = nv10_sw_new, 678 }; 679 680 static const struct nvkm_device_chip 681 nv49_chipset = { 682 .name = "G71", 683 .bios = nvkm_bios_new, 684 .bus = nv31_bus_new, 685 .clk = nv40_clk_new, 686 .devinit = nv1a_devinit_new, 687 .fb = nv49_fb_new, 688 .gpio = nv10_gpio_new, 689 .i2c = nv04_i2c_new, 690 .imem = nv40_instmem_new, 691 .mc = nv17_mc_new, 692 .mmu = nv41_mmu_new, 693 .pci = nv40_pci_new, 694 .therm = nv40_therm_new, 695 .timer = nv41_timer_new, 696 .volt = nv40_volt_new, 697 .disp = nv04_disp_new, 698 .dma = nv04_dma_new, 699 .fifo = nv40_fifo_new, 700 .gr = nv40_gr_new, 701 .mpeg = nv44_mpeg_new, 702 .pm = nv40_pm_new, 703 .sw = nv10_sw_new, 704 }; 705 706 static const struct nvkm_device_chip 707 nv4a_chipset = { 708 .name = "NV44A", 709 .bios = nvkm_bios_new, 710 .bus = nv31_bus_new, 711 .clk = nv40_clk_new, 712 .devinit = nv1a_devinit_new, 713 .fb = nv44_fb_new, 714 .gpio = nv10_gpio_new, 715 .i2c = nv04_i2c_new, 716 .imem = nv40_instmem_new, 717 .mc = nv44_mc_new, 718 .mmu = nv04_mmu_new, 719 .pci = nv40_pci_new, 720 .therm = nv40_therm_new, 721 .timer = nv41_timer_new, 722 .volt = nv40_volt_new, 723 .disp = nv04_disp_new, 724 .dma = nv04_dma_new, 725 .fifo = nv40_fifo_new, 726 .gr = nv44_gr_new, 727 .mpeg = nv44_mpeg_new, 728 .pm = nv40_pm_new, 729 .sw = nv10_sw_new, 730 }; 731 732 static const struct nvkm_device_chip 733 nv4b_chipset = { 734 .name = "G73", 735 .bios = nvkm_bios_new, 736 .bus = nv31_bus_new, 737 .clk = nv40_clk_new, 738 .devinit = nv1a_devinit_new, 739 .fb = nv49_fb_new, 740 .gpio = nv10_gpio_new, 741 .i2c = nv04_i2c_new, 742 .imem = nv40_instmem_new, 743 .mc = nv17_mc_new, 744 .mmu = nv41_mmu_new, 745 .pci = nv40_pci_new, 746 .therm = nv40_therm_new, 747 .timer = nv41_timer_new, 748 .volt = nv40_volt_new, 749 .disp = nv04_disp_new, 750 .dma = nv04_dma_new, 751 .fifo = nv40_fifo_new, 752 .gr = nv40_gr_new, 753 .mpeg = nv44_mpeg_new, 754 .pm = nv40_pm_new, 755 .sw = nv10_sw_new, 756 }; 757 758 static const struct nvkm_device_chip 759 nv4c_chipset = { 760 .name = "C61", 761 .bios = nvkm_bios_new, 762 .bus = nv31_bus_new, 763 .clk = nv40_clk_new, 764 .devinit = nv1a_devinit_new, 765 .fb = nv46_fb_new, 766 .gpio = nv10_gpio_new, 767 .i2c = nv04_i2c_new, 768 .imem = nv40_instmem_new, 769 .mc = nv44_mc_new, 770 .mmu = nv44_mmu_new, 771 .pci = nv4c_pci_new, 772 .therm = nv40_therm_new, 773 .timer = nv41_timer_new, 774 .volt = nv40_volt_new, 775 .disp = nv04_disp_new, 776 .dma = nv04_dma_new, 777 .fifo = nv40_fifo_new, 778 .gr = nv44_gr_new, 779 .mpeg = nv44_mpeg_new, 780 .pm = nv40_pm_new, 781 .sw = nv10_sw_new, 782 }; 783 784 static const struct nvkm_device_chip 785 nv4e_chipset = { 786 .name = "C51", 787 .bios = nvkm_bios_new, 788 .bus = nv31_bus_new, 789 .clk = nv40_clk_new, 790 .devinit = nv1a_devinit_new, 791 .fb = nv4e_fb_new, 792 .gpio = nv10_gpio_new, 793 .i2c = nv4e_i2c_new, 794 .imem = nv40_instmem_new, 795 .mc = nv44_mc_new, 796 .mmu = nv44_mmu_new, 797 .pci = nv4c_pci_new, 798 .therm = nv40_therm_new, 799 .timer = nv41_timer_new, 800 .volt = nv40_volt_new, 801 .disp = nv04_disp_new, 802 .dma = nv04_dma_new, 803 .fifo = nv40_fifo_new, 804 .gr = nv44_gr_new, 805 .mpeg = nv44_mpeg_new, 806 .pm = nv40_pm_new, 807 .sw = nv10_sw_new, 808 }; 809 810 static const struct nvkm_device_chip 811 nv50_chipset = { 812 .name = "G80", 813 .bar = nv50_bar_new, 814 .bios = nvkm_bios_new, 815 .bus = nv50_bus_new, 816 .clk = nv50_clk_new, 817 .devinit = nv50_devinit_new, 818 .fb = nv50_fb_new, 819 .fuse = nv50_fuse_new, 820 .gpio = nv50_gpio_new, 821 .i2c = nv50_i2c_new, 822 .imem = nv50_instmem_new, 823 .mc = nv50_mc_new, 824 .mmu = nv50_mmu_new, 825 .mxm = nv50_mxm_new, 826 .pci = nv46_pci_new, 827 .therm = nv50_therm_new, 828 .timer = nv41_timer_new, 829 .volt = nv40_volt_new, 830 .disp = nv50_disp_new, 831 .dma = nv50_dma_new, 832 .fifo = nv50_fifo_new, 833 .gr = nv50_gr_new, 834 .mpeg = nv50_mpeg_new, 835 .pm = nv50_pm_new, 836 .sw = nv50_sw_new, 837 }; 838 839 static const struct nvkm_device_chip 840 nv63_chipset = { 841 .name = "C73", 842 .bios = nvkm_bios_new, 843 .bus = nv31_bus_new, 844 .clk = nv40_clk_new, 845 .devinit = nv1a_devinit_new, 846 .fb = nv46_fb_new, 847 .gpio = nv10_gpio_new, 848 .i2c = nv04_i2c_new, 849 .imem = nv40_instmem_new, 850 .mc = nv44_mc_new, 851 .mmu = nv44_mmu_new, 852 .pci = nv4c_pci_new, 853 .therm = nv40_therm_new, 854 .timer = nv41_timer_new, 855 .volt = nv40_volt_new, 856 .disp = nv04_disp_new, 857 .dma = nv04_dma_new, 858 .fifo = nv40_fifo_new, 859 .gr = nv44_gr_new, 860 .mpeg = nv44_mpeg_new, 861 .pm = nv40_pm_new, 862 .sw = nv10_sw_new, 863 }; 864 865 static const struct nvkm_device_chip 866 nv67_chipset = { 867 .name = "C67", 868 .bios = nvkm_bios_new, 869 .bus = nv31_bus_new, 870 .clk = nv40_clk_new, 871 .devinit = nv1a_devinit_new, 872 .fb = nv46_fb_new, 873 .gpio = nv10_gpio_new, 874 .i2c = nv04_i2c_new, 875 .imem = nv40_instmem_new, 876 .mc = nv44_mc_new, 877 .mmu = nv44_mmu_new, 878 .pci = nv4c_pci_new, 879 .therm = nv40_therm_new, 880 .timer = nv41_timer_new, 881 .volt = nv40_volt_new, 882 .disp = nv04_disp_new, 883 .dma = nv04_dma_new, 884 .fifo = nv40_fifo_new, 885 .gr = nv44_gr_new, 886 .mpeg = nv44_mpeg_new, 887 .pm = nv40_pm_new, 888 .sw = nv10_sw_new, 889 }; 890 891 static const struct nvkm_device_chip 892 nv68_chipset = { 893 .name = "C68", 894 .bios = nvkm_bios_new, 895 .bus = nv31_bus_new, 896 .clk = nv40_clk_new, 897 .devinit = nv1a_devinit_new, 898 .fb = nv46_fb_new, 899 .gpio = nv10_gpio_new, 900 .i2c = nv04_i2c_new, 901 .imem = nv40_instmem_new, 902 .mc = nv44_mc_new, 903 .mmu = nv44_mmu_new, 904 .pci = nv4c_pci_new, 905 .therm = nv40_therm_new, 906 .timer = nv41_timer_new, 907 .volt = nv40_volt_new, 908 .disp = nv04_disp_new, 909 .dma = nv04_dma_new, 910 .fifo = nv40_fifo_new, 911 .gr = nv44_gr_new, 912 .mpeg = nv44_mpeg_new, 913 .pm = nv40_pm_new, 914 .sw = nv10_sw_new, 915 }; 916 917 static const struct nvkm_device_chip 918 nv84_chipset = { 919 .name = "G84", 920 .bar = g84_bar_new, 921 .bios = nvkm_bios_new, 922 .bus = nv50_bus_new, 923 .clk = g84_clk_new, 924 .devinit = g84_devinit_new, 925 .fb = g84_fb_new, 926 .fuse = nv50_fuse_new, 927 .gpio = nv50_gpio_new, 928 .i2c = nv50_i2c_new, 929 .imem = nv50_instmem_new, 930 .mc = g84_mc_new, 931 .mmu = g84_mmu_new, 932 .mxm = nv50_mxm_new, 933 .pci = g84_pci_new, 934 .therm = g84_therm_new, 935 .timer = nv41_timer_new, 936 .volt = nv40_volt_new, 937 .bsp = g84_bsp_new, 938 .cipher = g84_cipher_new, 939 .disp = g84_disp_new, 940 .dma = nv50_dma_new, 941 .fifo = g84_fifo_new, 942 .gr = g84_gr_new, 943 .mpeg = g84_mpeg_new, 944 .pm = g84_pm_new, 945 .sw = nv50_sw_new, 946 .vp = g84_vp_new, 947 }; 948 949 static const struct nvkm_device_chip 950 nv86_chipset = { 951 .name = "G86", 952 .bar = g84_bar_new, 953 .bios = nvkm_bios_new, 954 .bus = nv50_bus_new, 955 .clk = g84_clk_new, 956 .devinit = g84_devinit_new, 957 .fb = g84_fb_new, 958 .fuse = nv50_fuse_new, 959 .gpio = nv50_gpio_new, 960 .i2c = nv50_i2c_new, 961 .imem = nv50_instmem_new, 962 .mc = g84_mc_new, 963 .mmu = g84_mmu_new, 964 .mxm = nv50_mxm_new, 965 .pci = g84_pci_new, 966 .therm = g84_therm_new, 967 .timer = nv41_timer_new, 968 .volt = nv40_volt_new, 969 .bsp = g84_bsp_new, 970 .cipher = g84_cipher_new, 971 .disp = g84_disp_new, 972 .dma = nv50_dma_new, 973 .fifo = g84_fifo_new, 974 .gr = g84_gr_new, 975 .mpeg = g84_mpeg_new, 976 .pm = g84_pm_new, 977 .sw = nv50_sw_new, 978 .vp = g84_vp_new, 979 }; 980 981 static const struct nvkm_device_chip 982 nv92_chipset = { 983 .name = "G92", 984 .bar = g84_bar_new, 985 .bios = nvkm_bios_new, 986 .bus = nv50_bus_new, 987 .clk = g84_clk_new, 988 .devinit = g84_devinit_new, 989 .fb = g84_fb_new, 990 .fuse = nv50_fuse_new, 991 .gpio = nv50_gpio_new, 992 .i2c = nv50_i2c_new, 993 .imem = nv50_instmem_new, 994 .mc = g84_mc_new, 995 .mmu = g84_mmu_new, 996 .mxm = nv50_mxm_new, 997 .pci = g92_pci_new, 998 .therm = g84_therm_new, 999 .timer = nv41_timer_new, 1000 .volt = nv40_volt_new, 1001 .bsp = g84_bsp_new, 1002 .cipher = g84_cipher_new, 1003 .disp = g84_disp_new, 1004 .dma = nv50_dma_new, 1005 .fifo = g84_fifo_new, 1006 .gr = g84_gr_new, 1007 .mpeg = g84_mpeg_new, 1008 .pm = g84_pm_new, 1009 .sw = nv50_sw_new, 1010 .vp = g84_vp_new, 1011 }; 1012 1013 static const struct nvkm_device_chip 1014 nv94_chipset = { 1015 .name = "G94", 1016 .bar = g84_bar_new, 1017 .bios = nvkm_bios_new, 1018 .bus = g94_bus_new, 1019 .clk = g84_clk_new, 1020 .devinit = g84_devinit_new, 1021 .fb = g84_fb_new, 1022 .fuse = nv50_fuse_new, 1023 .gpio = g94_gpio_new, 1024 .i2c = g94_i2c_new, 1025 .imem = nv50_instmem_new, 1026 .mc = g84_mc_new, 1027 .mmu = g84_mmu_new, 1028 .mxm = nv50_mxm_new, 1029 .pci = g94_pci_new, 1030 .therm = g84_therm_new, 1031 .timer = nv41_timer_new, 1032 .volt = nv40_volt_new, 1033 .bsp = g84_bsp_new, 1034 .cipher = g84_cipher_new, 1035 .disp = g94_disp_new, 1036 .dma = nv50_dma_new, 1037 .fifo = g84_fifo_new, 1038 .gr = g84_gr_new, 1039 .mpeg = g84_mpeg_new, 1040 .pm = g84_pm_new, 1041 .sw = nv50_sw_new, 1042 .vp = g84_vp_new, 1043 }; 1044 1045 static const struct nvkm_device_chip 1046 nv96_chipset = { 1047 .name = "G96", 1048 .bar = g84_bar_new, 1049 .bios = nvkm_bios_new, 1050 .bus = g94_bus_new, 1051 .clk = g84_clk_new, 1052 .devinit = g84_devinit_new, 1053 .fb = g84_fb_new, 1054 .fuse = nv50_fuse_new, 1055 .gpio = g94_gpio_new, 1056 .i2c = g94_i2c_new, 1057 .imem = nv50_instmem_new, 1058 .mc = g84_mc_new, 1059 .mmu = g84_mmu_new, 1060 .mxm = nv50_mxm_new, 1061 .pci = g94_pci_new, 1062 .therm = g84_therm_new, 1063 .timer = nv41_timer_new, 1064 .volt = nv40_volt_new, 1065 .bsp = g84_bsp_new, 1066 .cipher = g84_cipher_new, 1067 .disp = g94_disp_new, 1068 .dma = nv50_dma_new, 1069 .fifo = g84_fifo_new, 1070 .gr = g84_gr_new, 1071 .mpeg = g84_mpeg_new, 1072 .pm = g84_pm_new, 1073 .sw = nv50_sw_new, 1074 .vp = g84_vp_new, 1075 }; 1076 1077 static const struct nvkm_device_chip 1078 nv98_chipset = { 1079 .name = "G98", 1080 .bar = g84_bar_new, 1081 .bios = nvkm_bios_new, 1082 .bus = g94_bus_new, 1083 .clk = g84_clk_new, 1084 .devinit = g98_devinit_new, 1085 .fb = g84_fb_new, 1086 .fuse = nv50_fuse_new, 1087 .gpio = g94_gpio_new, 1088 .i2c = g94_i2c_new, 1089 .imem = nv50_instmem_new, 1090 .mc = g98_mc_new, 1091 .mmu = g84_mmu_new, 1092 .mxm = nv50_mxm_new, 1093 .pci = g94_pci_new, 1094 .therm = g84_therm_new, 1095 .timer = nv41_timer_new, 1096 .volt = nv40_volt_new, 1097 .disp = g94_disp_new, 1098 .dma = nv50_dma_new, 1099 .fifo = g84_fifo_new, 1100 .gr = g84_gr_new, 1101 .mspdec = g98_mspdec_new, 1102 .msppp = g98_msppp_new, 1103 .msvld = g98_msvld_new, 1104 .pm = g84_pm_new, 1105 .sec = g98_sec_new, 1106 .sw = nv50_sw_new, 1107 }; 1108 1109 static const struct nvkm_device_chip 1110 nva0_chipset = { 1111 .name = "GT200", 1112 .bar = g84_bar_new, 1113 .bios = nvkm_bios_new, 1114 .bus = g94_bus_new, 1115 .clk = g84_clk_new, 1116 .devinit = g84_devinit_new, 1117 .fb = g84_fb_new, 1118 .fuse = nv50_fuse_new, 1119 .gpio = g94_gpio_new, 1120 .i2c = nv50_i2c_new, 1121 .imem = nv50_instmem_new, 1122 .mc = g84_mc_new, 1123 .mmu = g84_mmu_new, 1124 .mxm = nv50_mxm_new, 1125 .pci = g94_pci_new, 1126 .therm = g84_therm_new, 1127 .timer = nv41_timer_new, 1128 .volt = nv40_volt_new, 1129 .bsp = g84_bsp_new, 1130 .cipher = g84_cipher_new, 1131 .disp = gt200_disp_new, 1132 .dma = nv50_dma_new, 1133 .fifo = g84_fifo_new, 1134 .gr = gt200_gr_new, 1135 .mpeg = g84_mpeg_new, 1136 .pm = gt200_pm_new, 1137 .sw = nv50_sw_new, 1138 .vp = g84_vp_new, 1139 }; 1140 1141 static const struct nvkm_device_chip 1142 nva3_chipset = { 1143 .name = "GT215", 1144 .bar = g84_bar_new, 1145 .bios = nvkm_bios_new, 1146 .bus = g94_bus_new, 1147 .clk = gt215_clk_new, 1148 .devinit = gt215_devinit_new, 1149 .fb = gt215_fb_new, 1150 .fuse = nv50_fuse_new, 1151 .gpio = g94_gpio_new, 1152 .i2c = g94_i2c_new, 1153 .imem = nv50_instmem_new, 1154 .mc = gt215_mc_new, 1155 .mmu = g84_mmu_new, 1156 .mxm = nv50_mxm_new, 1157 .pci = g94_pci_new, 1158 .pmu = gt215_pmu_new, 1159 .therm = gt215_therm_new, 1160 .timer = nv41_timer_new, 1161 .volt = nv40_volt_new, 1162 .ce[0] = gt215_ce_new, 1163 .disp = gt215_disp_new, 1164 .dma = nv50_dma_new, 1165 .fifo = g84_fifo_new, 1166 .gr = gt215_gr_new, 1167 .mpeg = g84_mpeg_new, 1168 .mspdec = gt215_mspdec_new, 1169 .msppp = gt215_msppp_new, 1170 .msvld = gt215_msvld_new, 1171 .pm = gt215_pm_new, 1172 .sw = nv50_sw_new, 1173 }; 1174 1175 static const struct nvkm_device_chip 1176 nva5_chipset = { 1177 .name = "GT216", 1178 .bar = g84_bar_new, 1179 .bios = nvkm_bios_new, 1180 .bus = g94_bus_new, 1181 .clk = gt215_clk_new, 1182 .devinit = gt215_devinit_new, 1183 .fb = gt215_fb_new, 1184 .fuse = nv50_fuse_new, 1185 .gpio = g94_gpio_new, 1186 .i2c = g94_i2c_new, 1187 .imem = nv50_instmem_new, 1188 .mc = gt215_mc_new, 1189 .mmu = g84_mmu_new, 1190 .mxm = nv50_mxm_new, 1191 .pci = g94_pci_new, 1192 .pmu = gt215_pmu_new, 1193 .therm = gt215_therm_new, 1194 .timer = nv41_timer_new, 1195 .volt = nv40_volt_new, 1196 .ce[0] = gt215_ce_new, 1197 .disp = gt215_disp_new, 1198 .dma = nv50_dma_new, 1199 .fifo = g84_fifo_new, 1200 .gr = gt215_gr_new, 1201 .mspdec = gt215_mspdec_new, 1202 .msppp = gt215_msppp_new, 1203 .msvld = gt215_msvld_new, 1204 .pm = gt215_pm_new, 1205 .sw = nv50_sw_new, 1206 }; 1207 1208 static const struct nvkm_device_chip 1209 nva8_chipset = { 1210 .name = "GT218", 1211 .bar = g84_bar_new, 1212 .bios = nvkm_bios_new, 1213 .bus = g94_bus_new, 1214 .clk = gt215_clk_new, 1215 .devinit = gt215_devinit_new, 1216 .fb = gt215_fb_new, 1217 .fuse = nv50_fuse_new, 1218 .gpio = g94_gpio_new, 1219 .i2c = g94_i2c_new, 1220 .imem = nv50_instmem_new, 1221 .mc = gt215_mc_new, 1222 .mmu = g84_mmu_new, 1223 .mxm = nv50_mxm_new, 1224 .pci = g94_pci_new, 1225 .pmu = gt215_pmu_new, 1226 .therm = gt215_therm_new, 1227 .timer = nv41_timer_new, 1228 .volt = nv40_volt_new, 1229 .ce[0] = gt215_ce_new, 1230 .disp = gt215_disp_new, 1231 .dma = nv50_dma_new, 1232 .fifo = g84_fifo_new, 1233 .gr = gt215_gr_new, 1234 .mspdec = gt215_mspdec_new, 1235 .msppp = gt215_msppp_new, 1236 .msvld = gt215_msvld_new, 1237 .pm = gt215_pm_new, 1238 .sw = nv50_sw_new, 1239 }; 1240 1241 static const struct nvkm_device_chip 1242 nvaa_chipset = { 1243 .name = "MCP77/MCP78", 1244 .bar = g84_bar_new, 1245 .bios = nvkm_bios_new, 1246 .bus = g94_bus_new, 1247 .clk = mcp77_clk_new, 1248 .devinit = g98_devinit_new, 1249 .fb = mcp77_fb_new, 1250 .fuse = nv50_fuse_new, 1251 .gpio = g94_gpio_new, 1252 .i2c = g94_i2c_new, 1253 .imem = nv50_instmem_new, 1254 .mc = g98_mc_new, 1255 .mmu = mcp77_mmu_new, 1256 .mxm = nv50_mxm_new, 1257 .pci = g94_pci_new, 1258 .therm = g84_therm_new, 1259 .timer = nv41_timer_new, 1260 .volt = nv40_volt_new, 1261 .disp = mcp77_disp_new, 1262 .dma = nv50_dma_new, 1263 .fifo = g84_fifo_new, 1264 .gr = gt200_gr_new, 1265 .mspdec = g98_mspdec_new, 1266 .msppp = g98_msppp_new, 1267 .msvld = g98_msvld_new, 1268 .pm = g84_pm_new, 1269 .sec = g98_sec_new, 1270 .sw = nv50_sw_new, 1271 }; 1272 1273 static const struct nvkm_device_chip 1274 nvac_chipset = { 1275 .name = "MCP79/MCP7A", 1276 .bar = g84_bar_new, 1277 .bios = nvkm_bios_new, 1278 .bus = g94_bus_new, 1279 .clk = mcp77_clk_new, 1280 .devinit = g98_devinit_new, 1281 .fb = mcp77_fb_new, 1282 .fuse = nv50_fuse_new, 1283 .gpio = g94_gpio_new, 1284 .i2c = g94_i2c_new, 1285 .imem = nv50_instmem_new, 1286 .mc = g98_mc_new, 1287 .mmu = mcp77_mmu_new, 1288 .mxm = nv50_mxm_new, 1289 .pci = g94_pci_new, 1290 .therm = g84_therm_new, 1291 .timer = nv41_timer_new, 1292 .volt = nv40_volt_new, 1293 .disp = mcp77_disp_new, 1294 .dma = nv50_dma_new, 1295 .fifo = g84_fifo_new, 1296 .gr = mcp79_gr_new, 1297 .mspdec = g98_mspdec_new, 1298 .msppp = g98_msppp_new, 1299 .msvld = g98_msvld_new, 1300 .pm = g84_pm_new, 1301 .sec = g98_sec_new, 1302 .sw = nv50_sw_new, 1303 }; 1304 1305 static const struct nvkm_device_chip 1306 nvaf_chipset = { 1307 .name = "MCP89", 1308 .bar = g84_bar_new, 1309 .bios = nvkm_bios_new, 1310 .bus = g94_bus_new, 1311 .clk = gt215_clk_new, 1312 .devinit = mcp89_devinit_new, 1313 .fb = mcp89_fb_new, 1314 .fuse = nv50_fuse_new, 1315 .gpio = g94_gpio_new, 1316 .i2c = g94_i2c_new, 1317 .imem = nv50_instmem_new, 1318 .mc = gt215_mc_new, 1319 .mmu = mcp77_mmu_new, 1320 .mxm = nv50_mxm_new, 1321 .pci = g94_pci_new, 1322 .pmu = gt215_pmu_new, 1323 .therm = gt215_therm_new, 1324 .timer = nv41_timer_new, 1325 .volt = nv40_volt_new, 1326 .ce[0] = gt215_ce_new, 1327 .disp = mcp89_disp_new, 1328 .dma = nv50_dma_new, 1329 .fifo = g84_fifo_new, 1330 .gr = mcp89_gr_new, 1331 .mspdec = gt215_mspdec_new, 1332 .msppp = gt215_msppp_new, 1333 .msvld = mcp89_msvld_new, 1334 .pm = gt215_pm_new, 1335 .sw = nv50_sw_new, 1336 }; 1337 1338 static const struct nvkm_device_chip 1339 nvc0_chipset = { 1340 .name = "GF100", 1341 .bar = gf100_bar_new, 1342 .bios = nvkm_bios_new, 1343 .bus = gf100_bus_new, 1344 .clk = gf100_clk_new, 1345 .devinit = gf100_devinit_new, 1346 .fb = gf100_fb_new, 1347 .fuse = gf100_fuse_new, 1348 .gpio = g94_gpio_new, 1349 .i2c = g94_i2c_new, 1350 .ibus = gf100_ibus_new, 1351 .iccsense = gf100_iccsense_new, 1352 .imem = nv50_instmem_new, 1353 .ltc = gf100_ltc_new, 1354 .mc = gf100_mc_new, 1355 .mmu = gf100_mmu_new, 1356 .mxm = nv50_mxm_new, 1357 .pci = gf100_pci_new, 1358 .pmu = gf100_pmu_new, 1359 .therm = gt215_therm_new, 1360 .timer = nv41_timer_new, 1361 .volt = gf100_volt_new, 1362 .ce[0] = gf100_ce_new, 1363 .ce[1] = gf100_ce_new, 1364 .disp = gt215_disp_new, 1365 .dma = gf100_dma_new, 1366 .fifo = gf100_fifo_new, 1367 .gr = gf100_gr_new, 1368 .mspdec = gf100_mspdec_new, 1369 .msppp = gf100_msppp_new, 1370 .msvld = gf100_msvld_new, 1371 .pm = gf100_pm_new, 1372 .sw = gf100_sw_new, 1373 }; 1374 1375 static const struct nvkm_device_chip 1376 nvc1_chipset = { 1377 .name = "GF108", 1378 .bar = gf100_bar_new, 1379 .bios = nvkm_bios_new, 1380 .bus = gf100_bus_new, 1381 .clk = gf100_clk_new, 1382 .devinit = gf100_devinit_new, 1383 .fb = gf108_fb_new, 1384 .fuse = gf100_fuse_new, 1385 .gpio = g94_gpio_new, 1386 .i2c = g94_i2c_new, 1387 .ibus = gf100_ibus_new, 1388 .iccsense = gf100_iccsense_new, 1389 .imem = nv50_instmem_new, 1390 .ltc = gf100_ltc_new, 1391 .mc = gf100_mc_new, 1392 .mmu = gf100_mmu_new, 1393 .mxm = nv50_mxm_new, 1394 .pci = gf106_pci_new, 1395 .pmu = gf100_pmu_new, 1396 .therm = gt215_therm_new, 1397 .timer = nv41_timer_new, 1398 .volt = gf100_volt_new, 1399 .ce[0] = gf100_ce_new, 1400 .disp = gt215_disp_new, 1401 .dma = gf100_dma_new, 1402 .fifo = gf100_fifo_new, 1403 .gr = gf108_gr_new, 1404 .mspdec = gf100_mspdec_new, 1405 .msppp = gf100_msppp_new, 1406 .msvld = gf100_msvld_new, 1407 .pm = gf108_pm_new, 1408 .sw = gf100_sw_new, 1409 }; 1410 1411 static const struct nvkm_device_chip 1412 nvc3_chipset = { 1413 .name = "GF106", 1414 .bar = gf100_bar_new, 1415 .bios = nvkm_bios_new, 1416 .bus = gf100_bus_new, 1417 .clk = gf100_clk_new, 1418 .devinit = gf100_devinit_new, 1419 .fb = gf100_fb_new, 1420 .fuse = gf100_fuse_new, 1421 .gpio = g94_gpio_new, 1422 .i2c = g94_i2c_new, 1423 .ibus = gf100_ibus_new, 1424 .iccsense = gf100_iccsense_new, 1425 .imem = nv50_instmem_new, 1426 .ltc = gf100_ltc_new, 1427 .mc = gf100_mc_new, 1428 .mmu = gf100_mmu_new, 1429 .mxm = nv50_mxm_new, 1430 .pci = gf106_pci_new, 1431 .pmu = gf100_pmu_new, 1432 .therm = gt215_therm_new, 1433 .timer = nv41_timer_new, 1434 .volt = gf100_volt_new, 1435 .ce[0] = gf100_ce_new, 1436 .disp = gt215_disp_new, 1437 .dma = gf100_dma_new, 1438 .fifo = gf100_fifo_new, 1439 .gr = gf104_gr_new, 1440 .mspdec = gf100_mspdec_new, 1441 .msppp = gf100_msppp_new, 1442 .msvld = gf100_msvld_new, 1443 .pm = gf100_pm_new, 1444 .sw = gf100_sw_new, 1445 }; 1446 1447 static const struct nvkm_device_chip 1448 nvc4_chipset = { 1449 .name = "GF104", 1450 .bar = gf100_bar_new, 1451 .bios = nvkm_bios_new, 1452 .bus = gf100_bus_new, 1453 .clk = gf100_clk_new, 1454 .devinit = gf100_devinit_new, 1455 .fb = gf100_fb_new, 1456 .fuse = gf100_fuse_new, 1457 .gpio = g94_gpio_new, 1458 .i2c = g94_i2c_new, 1459 .ibus = gf100_ibus_new, 1460 .iccsense = gf100_iccsense_new, 1461 .imem = nv50_instmem_new, 1462 .ltc = gf100_ltc_new, 1463 .mc = gf100_mc_new, 1464 .mmu = gf100_mmu_new, 1465 .mxm = nv50_mxm_new, 1466 .pci = gf100_pci_new, 1467 .pmu = gf100_pmu_new, 1468 .therm = gt215_therm_new, 1469 .timer = nv41_timer_new, 1470 .volt = gf100_volt_new, 1471 .ce[0] = gf100_ce_new, 1472 .ce[1] = gf100_ce_new, 1473 .disp = gt215_disp_new, 1474 .dma = gf100_dma_new, 1475 .fifo = gf100_fifo_new, 1476 .gr = gf104_gr_new, 1477 .mspdec = gf100_mspdec_new, 1478 .msppp = gf100_msppp_new, 1479 .msvld = gf100_msvld_new, 1480 .pm = gf100_pm_new, 1481 .sw = gf100_sw_new, 1482 }; 1483 1484 static const struct nvkm_device_chip 1485 nvc8_chipset = { 1486 .name = "GF110", 1487 .bar = gf100_bar_new, 1488 .bios = nvkm_bios_new, 1489 .bus = gf100_bus_new, 1490 .clk = gf100_clk_new, 1491 .devinit = gf100_devinit_new, 1492 .fb = gf100_fb_new, 1493 .fuse = gf100_fuse_new, 1494 .gpio = g94_gpio_new, 1495 .i2c = g94_i2c_new, 1496 .ibus = gf100_ibus_new, 1497 .iccsense = gf100_iccsense_new, 1498 .imem = nv50_instmem_new, 1499 .ltc = gf100_ltc_new, 1500 .mc = gf100_mc_new, 1501 .mmu = gf100_mmu_new, 1502 .mxm = nv50_mxm_new, 1503 .pci = gf100_pci_new, 1504 .pmu = gf100_pmu_new, 1505 .therm = gt215_therm_new, 1506 .timer = nv41_timer_new, 1507 .volt = gf100_volt_new, 1508 .ce[0] = gf100_ce_new, 1509 .ce[1] = gf100_ce_new, 1510 .disp = gt215_disp_new, 1511 .dma = gf100_dma_new, 1512 .fifo = gf100_fifo_new, 1513 .gr = gf110_gr_new, 1514 .mspdec = gf100_mspdec_new, 1515 .msppp = gf100_msppp_new, 1516 .msvld = gf100_msvld_new, 1517 .pm = gf100_pm_new, 1518 .sw = gf100_sw_new, 1519 }; 1520 1521 static const struct nvkm_device_chip 1522 nvce_chipset = { 1523 .name = "GF114", 1524 .bar = gf100_bar_new, 1525 .bios = nvkm_bios_new, 1526 .bus = gf100_bus_new, 1527 .clk = gf100_clk_new, 1528 .devinit = gf100_devinit_new, 1529 .fb = gf100_fb_new, 1530 .fuse = gf100_fuse_new, 1531 .gpio = g94_gpio_new, 1532 .i2c = g94_i2c_new, 1533 .ibus = gf100_ibus_new, 1534 .iccsense = gf100_iccsense_new, 1535 .imem = nv50_instmem_new, 1536 .ltc = gf100_ltc_new, 1537 .mc = gf100_mc_new, 1538 .mmu = gf100_mmu_new, 1539 .mxm = nv50_mxm_new, 1540 .pci = gf100_pci_new, 1541 .pmu = gf100_pmu_new, 1542 .therm = gt215_therm_new, 1543 .timer = nv41_timer_new, 1544 .volt = gf100_volt_new, 1545 .ce[0] = gf100_ce_new, 1546 .ce[1] = gf100_ce_new, 1547 .disp = gt215_disp_new, 1548 .dma = gf100_dma_new, 1549 .fifo = gf100_fifo_new, 1550 .gr = gf104_gr_new, 1551 .mspdec = gf100_mspdec_new, 1552 .msppp = gf100_msppp_new, 1553 .msvld = gf100_msvld_new, 1554 .pm = gf100_pm_new, 1555 .sw = gf100_sw_new, 1556 }; 1557 1558 static const struct nvkm_device_chip 1559 nvcf_chipset = { 1560 .name = "GF116", 1561 .bar = gf100_bar_new, 1562 .bios = nvkm_bios_new, 1563 .bus = gf100_bus_new, 1564 .clk = gf100_clk_new, 1565 .devinit = gf100_devinit_new, 1566 .fb = gf100_fb_new, 1567 .fuse = gf100_fuse_new, 1568 .gpio = g94_gpio_new, 1569 .i2c = g94_i2c_new, 1570 .ibus = gf100_ibus_new, 1571 .iccsense = gf100_iccsense_new, 1572 .imem = nv50_instmem_new, 1573 .ltc = gf100_ltc_new, 1574 .mc = gf100_mc_new, 1575 .mmu = gf100_mmu_new, 1576 .mxm = nv50_mxm_new, 1577 .pci = gf106_pci_new, 1578 .pmu = gf100_pmu_new, 1579 .therm = gt215_therm_new, 1580 .timer = nv41_timer_new, 1581 .volt = gf100_volt_new, 1582 .ce[0] = gf100_ce_new, 1583 .disp = gt215_disp_new, 1584 .dma = gf100_dma_new, 1585 .fifo = gf100_fifo_new, 1586 .gr = gf104_gr_new, 1587 .mspdec = gf100_mspdec_new, 1588 .msppp = gf100_msppp_new, 1589 .msvld = gf100_msvld_new, 1590 .pm = gf100_pm_new, 1591 .sw = gf100_sw_new, 1592 }; 1593 1594 static const struct nvkm_device_chip 1595 nvd7_chipset = { 1596 .name = "GF117", 1597 .bar = gf100_bar_new, 1598 .bios = nvkm_bios_new, 1599 .bus = gf100_bus_new, 1600 .clk = gf100_clk_new, 1601 .devinit = gf100_devinit_new, 1602 .fb = gf100_fb_new, 1603 .fuse = gf100_fuse_new, 1604 .gpio = gf119_gpio_new, 1605 .i2c = gf117_i2c_new, 1606 .ibus = gf117_ibus_new, 1607 .iccsense = gf100_iccsense_new, 1608 .imem = nv50_instmem_new, 1609 .ltc = gf100_ltc_new, 1610 .mc = gf100_mc_new, 1611 .mmu = gf100_mmu_new, 1612 .mxm = nv50_mxm_new, 1613 .pci = gf106_pci_new, 1614 .therm = gf119_therm_new, 1615 .timer = nv41_timer_new, 1616 .volt = gf117_volt_new, 1617 .ce[0] = gf100_ce_new, 1618 .disp = gf119_disp_new, 1619 .dma = gf119_dma_new, 1620 .fifo = gf100_fifo_new, 1621 .gr = gf117_gr_new, 1622 .mspdec = gf100_mspdec_new, 1623 .msppp = gf100_msppp_new, 1624 .msvld = gf100_msvld_new, 1625 .pm = gf117_pm_new, 1626 .sw = gf100_sw_new, 1627 }; 1628 1629 static const struct nvkm_device_chip 1630 nvd9_chipset = { 1631 .name = "GF119", 1632 .bar = gf100_bar_new, 1633 .bios = nvkm_bios_new, 1634 .bus = gf100_bus_new, 1635 .clk = gf100_clk_new, 1636 .devinit = gf100_devinit_new, 1637 .fb = gf100_fb_new, 1638 .fuse = gf100_fuse_new, 1639 .gpio = gf119_gpio_new, 1640 .i2c = gf119_i2c_new, 1641 .ibus = gf117_ibus_new, 1642 .iccsense = gf100_iccsense_new, 1643 .imem = nv50_instmem_new, 1644 .ltc = gf100_ltc_new, 1645 .mc = gf100_mc_new, 1646 .mmu = gf100_mmu_new, 1647 .mxm = nv50_mxm_new, 1648 .pci = gf106_pci_new, 1649 .pmu = gf119_pmu_new, 1650 .therm = gf119_therm_new, 1651 .timer = nv41_timer_new, 1652 .volt = gf100_volt_new, 1653 .ce[0] = gf100_ce_new, 1654 .disp = gf119_disp_new, 1655 .dma = gf119_dma_new, 1656 .fifo = gf100_fifo_new, 1657 .gr = gf119_gr_new, 1658 .mspdec = gf100_mspdec_new, 1659 .msppp = gf100_msppp_new, 1660 .msvld = gf100_msvld_new, 1661 .pm = gf117_pm_new, 1662 .sw = gf100_sw_new, 1663 }; 1664 1665 static const struct nvkm_device_chip 1666 nve4_chipset = { 1667 .name = "GK104", 1668 .bar = gf100_bar_new, 1669 .bios = nvkm_bios_new, 1670 .bus = gf100_bus_new, 1671 .clk = gk104_clk_new, 1672 .devinit = gf100_devinit_new, 1673 .fb = gk104_fb_new, 1674 .fuse = gf100_fuse_new, 1675 .gpio = gk104_gpio_new, 1676 .i2c = gk104_i2c_new, 1677 .ibus = gk104_ibus_new, 1678 .iccsense = gf100_iccsense_new, 1679 .imem = nv50_instmem_new, 1680 .ltc = gk104_ltc_new, 1681 .mc = gk104_mc_new, 1682 .mmu = gk104_mmu_new, 1683 .mxm = nv50_mxm_new, 1684 .pci = gk104_pci_new, 1685 .pmu = gk104_pmu_new, 1686 .therm = gk104_therm_new, 1687 .timer = nv41_timer_new, 1688 .top = gk104_top_new, 1689 .volt = gk104_volt_new, 1690 .ce[0] = gk104_ce_new, 1691 .ce[1] = gk104_ce_new, 1692 .ce[2] = gk104_ce_new, 1693 .disp = gk104_disp_new, 1694 .dma = gf119_dma_new, 1695 .fifo = gk104_fifo_new, 1696 .gr = gk104_gr_new, 1697 .mspdec = gk104_mspdec_new, 1698 .msppp = gf100_msppp_new, 1699 .msvld = gk104_msvld_new, 1700 .pm = gk104_pm_new, 1701 .sw = gf100_sw_new, 1702 }; 1703 1704 static const struct nvkm_device_chip 1705 nve6_chipset = { 1706 .name = "GK106", 1707 .bar = gf100_bar_new, 1708 .bios = nvkm_bios_new, 1709 .bus = gf100_bus_new, 1710 .clk = gk104_clk_new, 1711 .devinit = gf100_devinit_new, 1712 .fb = gk104_fb_new, 1713 .fuse = gf100_fuse_new, 1714 .gpio = gk104_gpio_new, 1715 .i2c = gk104_i2c_new, 1716 .ibus = gk104_ibus_new, 1717 .iccsense = gf100_iccsense_new, 1718 .imem = nv50_instmem_new, 1719 .ltc = gk104_ltc_new, 1720 .mc = gk104_mc_new, 1721 .mmu = gk104_mmu_new, 1722 .mxm = nv50_mxm_new, 1723 .pci = gk104_pci_new, 1724 .pmu = gk104_pmu_new, 1725 .therm = gk104_therm_new, 1726 .timer = nv41_timer_new, 1727 .top = gk104_top_new, 1728 .volt = gk104_volt_new, 1729 .ce[0] = gk104_ce_new, 1730 .ce[1] = gk104_ce_new, 1731 .ce[2] = gk104_ce_new, 1732 .disp = gk104_disp_new, 1733 .dma = gf119_dma_new, 1734 .fifo = gk104_fifo_new, 1735 .gr = gk104_gr_new, 1736 .mspdec = gk104_mspdec_new, 1737 .msppp = gf100_msppp_new, 1738 .msvld = gk104_msvld_new, 1739 .pm = gk104_pm_new, 1740 .sw = gf100_sw_new, 1741 }; 1742 1743 static const struct nvkm_device_chip 1744 nve7_chipset = { 1745 .name = "GK107", 1746 .bar = gf100_bar_new, 1747 .bios = nvkm_bios_new, 1748 .bus = gf100_bus_new, 1749 .clk = gk104_clk_new, 1750 .devinit = gf100_devinit_new, 1751 .fb = gk104_fb_new, 1752 .fuse = gf100_fuse_new, 1753 .gpio = gk104_gpio_new, 1754 .i2c = gk104_i2c_new, 1755 .ibus = gk104_ibus_new, 1756 .iccsense = gf100_iccsense_new, 1757 .imem = nv50_instmem_new, 1758 .ltc = gk104_ltc_new, 1759 .mc = gk104_mc_new, 1760 .mmu = gk104_mmu_new, 1761 .mxm = nv50_mxm_new, 1762 .pci = gk104_pci_new, 1763 .pmu = gk104_pmu_new, 1764 .therm = gk104_therm_new, 1765 .timer = nv41_timer_new, 1766 .top = gk104_top_new, 1767 .volt = gk104_volt_new, 1768 .ce[0] = gk104_ce_new, 1769 .ce[1] = gk104_ce_new, 1770 .ce[2] = gk104_ce_new, 1771 .disp = gk104_disp_new, 1772 .dma = gf119_dma_new, 1773 .fifo = gk104_fifo_new, 1774 .gr = gk104_gr_new, 1775 .mspdec = gk104_mspdec_new, 1776 .msppp = gf100_msppp_new, 1777 .msvld = gk104_msvld_new, 1778 .pm = gk104_pm_new, 1779 .sw = gf100_sw_new, 1780 }; 1781 1782 static const struct nvkm_device_chip 1783 nvea_chipset = { 1784 .name = "GK20A", 1785 .bar = gk20a_bar_new, 1786 .bus = gf100_bus_new, 1787 .clk = gk20a_clk_new, 1788 .fb = gk20a_fb_new, 1789 .fuse = gf100_fuse_new, 1790 .ibus = gk20a_ibus_new, 1791 .imem = gk20a_instmem_new, 1792 .ltc = gk104_ltc_new, 1793 .mc = gk20a_mc_new, 1794 .mmu = gk20a_mmu_new, 1795 .pmu = gk20a_pmu_new, 1796 .timer = gk20a_timer_new, 1797 .top = gk104_top_new, 1798 .volt = gk20a_volt_new, 1799 .ce[2] = gk104_ce_new, 1800 .dma = gf119_dma_new, 1801 .fifo = gk20a_fifo_new, 1802 .gr = gk20a_gr_new, 1803 .pm = gk104_pm_new, 1804 .sw = gf100_sw_new, 1805 }; 1806 1807 static const struct nvkm_device_chip 1808 nvf0_chipset = { 1809 .name = "GK110", 1810 .bar = gf100_bar_new, 1811 .bios = nvkm_bios_new, 1812 .bus = gf100_bus_new, 1813 .clk = gk104_clk_new, 1814 .devinit = gf100_devinit_new, 1815 .fb = gk110_fb_new, 1816 .fuse = gf100_fuse_new, 1817 .gpio = gk104_gpio_new, 1818 .i2c = gk110_i2c_new, 1819 .ibus = gk104_ibus_new, 1820 .iccsense = gf100_iccsense_new, 1821 .imem = nv50_instmem_new, 1822 .ltc = gk104_ltc_new, 1823 .mc = gk104_mc_new, 1824 .mmu = gk104_mmu_new, 1825 .mxm = nv50_mxm_new, 1826 .pci = gk104_pci_new, 1827 .pmu = gk110_pmu_new, 1828 .therm = gk104_therm_new, 1829 .timer = nv41_timer_new, 1830 .top = gk104_top_new, 1831 .volt = gk104_volt_new, 1832 .ce[0] = gk104_ce_new, 1833 .ce[1] = gk104_ce_new, 1834 .ce[2] = gk104_ce_new, 1835 .disp = gk110_disp_new, 1836 .dma = gf119_dma_new, 1837 .fifo = gk110_fifo_new, 1838 .gr = gk110_gr_new, 1839 .mspdec = gk104_mspdec_new, 1840 .msppp = gf100_msppp_new, 1841 .msvld = gk104_msvld_new, 1842 .sw = gf100_sw_new, 1843 }; 1844 1845 static const struct nvkm_device_chip 1846 nvf1_chipset = { 1847 .name = "GK110B", 1848 .bar = gf100_bar_new, 1849 .bios = nvkm_bios_new, 1850 .bus = gf100_bus_new, 1851 .clk = gk104_clk_new, 1852 .devinit = gf100_devinit_new, 1853 .fb = gk110_fb_new, 1854 .fuse = gf100_fuse_new, 1855 .gpio = gk104_gpio_new, 1856 .i2c = gk110_i2c_new, 1857 .ibus = gk104_ibus_new, 1858 .iccsense = gf100_iccsense_new, 1859 .imem = nv50_instmem_new, 1860 .ltc = gk104_ltc_new, 1861 .mc = gk104_mc_new, 1862 .mmu = gk104_mmu_new, 1863 .mxm = nv50_mxm_new, 1864 .pci = gk104_pci_new, 1865 .pmu = gk110_pmu_new, 1866 .therm = gk104_therm_new, 1867 .timer = nv41_timer_new, 1868 .top = gk104_top_new, 1869 .volt = gk104_volt_new, 1870 .ce[0] = gk104_ce_new, 1871 .ce[1] = gk104_ce_new, 1872 .ce[2] = gk104_ce_new, 1873 .disp = gk110_disp_new, 1874 .dma = gf119_dma_new, 1875 .fifo = gk110_fifo_new, 1876 .gr = gk110b_gr_new, 1877 .mspdec = gk104_mspdec_new, 1878 .msppp = gf100_msppp_new, 1879 .msvld = gk104_msvld_new, 1880 .sw = gf100_sw_new, 1881 }; 1882 1883 static const struct nvkm_device_chip 1884 nv106_chipset = { 1885 .name = "GK208B", 1886 .bar = gf100_bar_new, 1887 .bios = nvkm_bios_new, 1888 .bus = gf100_bus_new, 1889 .clk = gk104_clk_new, 1890 .devinit = gf100_devinit_new, 1891 .fb = gk110_fb_new, 1892 .fuse = gf100_fuse_new, 1893 .gpio = gk104_gpio_new, 1894 .i2c = gk110_i2c_new, 1895 .ibus = gk104_ibus_new, 1896 .iccsense = gf100_iccsense_new, 1897 .imem = nv50_instmem_new, 1898 .ltc = gk104_ltc_new, 1899 .mc = gk20a_mc_new, 1900 .mmu = gk104_mmu_new, 1901 .mxm = nv50_mxm_new, 1902 .pci = gk104_pci_new, 1903 .pmu = gk208_pmu_new, 1904 .therm = gk104_therm_new, 1905 .timer = nv41_timer_new, 1906 .top = gk104_top_new, 1907 .volt = gk104_volt_new, 1908 .ce[0] = gk104_ce_new, 1909 .ce[1] = gk104_ce_new, 1910 .ce[2] = gk104_ce_new, 1911 .disp = gk110_disp_new, 1912 .dma = gf119_dma_new, 1913 .fifo = gk208_fifo_new, 1914 .gr = gk208_gr_new, 1915 .mspdec = gk104_mspdec_new, 1916 .msppp = gf100_msppp_new, 1917 .msvld = gk104_msvld_new, 1918 .sw = gf100_sw_new, 1919 }; 1920 1921 static const struct nvkm_device_chip 1922 nv108_chipset = { 1923 .name = "GK208", 1924 .bar = gf100_bar_new, 1925 .bios = nvkm_bios_new, 1926 .bus = gf100_bus_new, 1927 .clk = gk104_clk_new, 1928 .devinit = gf100_devinit_new, 1929 .fb = gk110_fb_new, 1930 .fuse = gf100_fuse_new, 1931 .gpio = gk104_gpio_new, 1932 .i2c = gk110_i2c_new, 1933 .ibus = gk104_ibus_new, 1934 .iccsense = gf100_iccsense_new, 1935 .imem = nv50_instmem_new, 1936 .ltc = gk104_ltc_new, 1937 .mc = gk20a_mc_new, 1938 .mmu = gk104_mmu_new, 1939 .mxm = nv50_mxm_new, 1940 .pci = gk104_pci_new, 1941 .pmu = gk208_pmu_new, 1942 .therm = gk104_therm_new, 1943 .timer = nv41_timer_new, 1944 .top = gk104_top_new, 1945 .volt = gk104_volt_new, 1946 .ce[0] = gk104_ce_new, 1947 .ce[1] = gk104_ce_new, 1948 .ce[2] = gk104_ce_new, 1949 .disp = gk110_disp_new, 1950 .dma = gf119_dma_new, 1951 .fifo = gk208_fifo_new, 1952 .gr = gk208_gr_new, 1953 .mspdec = gk104_mspdec_new, 1954 .msppp = gf100_msppp_new, 1955 .msvld = gk104_msvld_new, 1956 .sw = gf100_sw_new, 1957 }; 1958 1959 static const struct nvkm_device_chip 1960 nv117_chipset = { 1961 .name = "GM107", 1962 .bar = gm107_bar_new, 1963 .bios = nvkm_bios_new, 1964 .bus = gf100_bus_new, 1965 .clk = gk104_clk_new, 1966 .devinit = gm107_devinit_new, 1967 .fb = gm107_fb_new, 1968 .fuse = gm107_fuse_new, 1969 .gpio = gk104_gpio_new, 1970 .i2c = gk110_i2c_new, 1971 .ibus = gk104_ibus_new, 1972 .iccsense = gf100_iccsense_new, 1973 .imem = nv50_instmem_new, 1974 .ltc = gm107_ltc_new, 1975 .mc = gk20a_mc_new, 1976 .mmu = gk104_mmu_new, 1977 .mxm = nv50_mxm_new, 1978 .pci = gk104_pci_new, 1979 .pmu = gm107_pmu_new, 1980 .therm = gm107_therm_new, 1981 .timer = gk20a_timer_new, 1982 .top = gk104_top_new, 1983 .volt = gk104_volt_new, 1984 .ce[0] = gm107_ce_new, 1985 .ce[2] = gm107_ce_new, 1986 .disp = gm107_disp_new, 1987 .dma = gf119_dma_new, 1988 .fifo = gm107_fifo_new, 1989 .gr = gm107_gr_new, 1990 .nvdec[0] = gm107_nvdec_new, 1991 .nvenc[0] = gm107_nvenc_new, 1992 .sw = gf100_sw_new, 1993 }; 1994 1995 static const struct nvkm_device_chip 1996 nv118_chipset = { 1997 .name = "GM108", 1998 .bar = gm107_bar_new, 1999 .bios = nvkm_bios_new, 2000 .bus = gf100_bus_new, 2001 .clk = gk104_clk_new, 2002 .devinit = gm107_devinit_new, 2003 .fb = gm107_fb_new, 2004 .fuse = gm107_fuse_new, 2005 .gpio = gk104_gpio_new, 2006 .i2c = gk110_i2c_new, 2007 .ibus = gk104_ibus_new, 2008 .iccsense = gf100_iccsense_new, 2009 .imem = nv50_instmem_new, 2010 .ltc = gm107_ltc_new, 2011 .mc = gk20a_mc_new, 2012 .mmu = gk104_mmu_new, 2013 .mxm = nv50_mxm_new, 2014 .pci = gk104_pci_new, 2015 .pmu = gm107_pmu_new, 2016 .therm = gm107_therm_new, 2017 .timer = gk20a_timer_new, 2018 .top = gk104_top_new, 2019 .volt = gk104_volt_new, 2020 .ce[0] = gm107_ce_new, 2021 .ce[2] = gm107_ce_new, 2022 .disp = gm107_disp_new, 2023 .dma = gf119_dma_new, 2024 .fifo = gm107_fifo_new, 2025 .gr = gm107_gr_new, 2026 .sw = gf100_sw_new, 2027 }; 2028 2029 static const struct nvkm_device_chip 2030 nv120_chipset = { 2031 .name = "GM200", 2032 .acr = gm200_acr_new, 2033 .bar = gm107_bar_new, 2034 .bios = nvkm_bios_new, 2035 .bus = gf100_bus_new, 2036 .devinit = gm200_devinit_new, 2037 .fb = gm200_fb_new, 2038 .fuse = gm107_fuse_new, 2039 .gpio = gk104_gpio_new, 2040 .i2c = gm200_i2c_new, 2041 .ibus = gm200_ibus_new, 2042 .iccsense = gf100_iccsense_new, 2043 .imem = nv50_instmem_new, 2044 .ltc = gm200_ltc_new, 2045 .mc = gk20a_mc_new, 2046 .mmu = gm200_mmu_new, 2047 .mxm = nv50_mxm_new, 2048 .pci = gk104_pci_new, 2049 .pmu = gm200_pmu_new, 2050 .therm = gm200_therm_new, 2051 .timer = gk20a_timer_new, 2052 .top = gk104_top_new, 2053 .volt = gk104_volt_new, 2054 .ce[0] = gm200_ce_new, 2055 .ce[1] = gm200_ce_new, 2056 .ce[2] = gm200_ce_new, 2057 .disp = gm200_disp_new, 2058 .dma = gf119_dma_new, 2059 .fifo = gm200_fifo_new, 2060 .gr = gm200_gr_new, 2061 .nvdec[0] = gm107_nvdec_new, 2062 .nvenc[0] = gm107_nvenc_new, 2063 .nvenc[1] = gm107_nvenc_new, 2064 .sw = gf100_sw_new, 2065 }; 2066 2067 static const struct nvkm_device_chip 2068 nv124_chipset = { 2069 .name = "GM204", 2070 .acr = gm200_acr_new, 2071 .bar = gm107_bar_new, 2072 .bios = nvkm_bios_new, 2073 .bus = gf100_bus_new, 2074 .devinit = gm200_devinit_new, 2075 .fb = gm200_fb_new, 2076 .fuse = gm107_fuse_new, 2077 .gpio = gk104_gpio_new, 2078 .i2c = gm200_i2c_new, 2079 .ibus = gm200_ibus_new, 2080 .iccsense = gf100_iccsense_new, 2081 .imem = nv50_instmem_new, 2082 .ltc = gm200_ltc_new, 2083 .mc = gk20a_mc_new, 2084 .mmu = gm200_mmu_new, 2085 .mxm = nv50_mxm_new, 2086 .pci = gk104_pci_new, 2087 .pmu = gm200_pmu_new, 2088 .therm = gm200_therm_new, 2089 .timer = gk20a_timer_new, 2090 .top = gk104_top_new, 2091 .volt = gk104_volt_new, 2092 .ce[0] = gm200_ce_new, 2093 .ce[1] = gm200_ce_new, 2094 .ce[2] = gm200_ce_new, 2095 .disp = gm200_disp_new, 2096 .dma = gf119_dma_new, 2097 .fifo = gm200_fifo_new, 2098 .gr = gm200_gr_new, 2099 .nvdec[0] = gm107_nvdec_new, 2100 .nvenc[0] = gm107_nvenc_new, 2101 .nvenc[1] = gm107_nvenc_new, 2102 .sw = gf100_sw_new, 2103 }; 2104 2105 static const struct nvkm_device_chip 2106 nv126_chipset = { 2107 .name = "GM206", 2108 .acr = gm200_acr_new, 2109 .bar = gm107_bar_new, 2110 .bios = nvkm_bios_new, 2111 .bus = gf100_bus_new, 2112 .devinit = gm200_devinit_new, 2113 .fb = gm200_fb_new, 2114 .fuse = gm107_fuse_new, 2115 .gpio = gk104_gpio_new, 2116 .i2c = gm200_i2c_new, 2117 .ibus = gm200_ibus_new, 2118 .iccsense = gf100_iccsense_new, 2119 .imem = nv50_instmem_new, 2120 .ltc = gm200_ltc_new, 2121 .mc = gk20a_mc_new, 2122 .mmu = gm200_mmu_new, 2123 .mxm = nv50_mxm_new, 2124 .pci = gk104_pci_new, 2125 .pmu = gm200_pmu_new, 2126 .therm = gm200_therm_new, 2127 .timer = gk20a_timer_new, 2128 .top = gk104_top_new, 2129 .volt = gk104_volt_new, 2130 .ce[0] = gm200_ce_new, 2131 .ce[1] = gm200_ce_new, 2132 .ce[2] = gm200_ce_new, 2133 .disp = gm200_disp_new, 2134 .dma = gf119_dma_new, 2135 .fifo = gm200_fifo_new, 2136 .gr = gm200_gr_new, 2137 .nvdec[0] = gm107_nvdec_new, 2138 .nvenc[0] = gm107_nvenc_new, 2139 .sw = gf100_sw_new, 2140 }; 2141 2142 static const struct nvkm_device_chip 2143 nv12b_chipset = { 2144 .name = "GM20B", 2145 .acr = gm20b_acr_new, 2146 .bar = gm20b_bar_new, 2147 .bus = gf100_bus_new, 2148 .clk = gm20b_clk_new, 2149 .fb = gm20b_fb_new, 2150 .fuse = gm107_fuse_new, 2151 .ibus = gk20a_ibus_new, 2152 .imem = gk20a_instmem_new, 2153 .ltc = gm200_ltc_new, 2154 .mc = gk20a_mc_new, 2155 .mmu = gm20b_mmu_new, 2156 .pmu = gm20b_pmu_new, 2157 .timer = gk20a_timer_new, 2158 .top = gk104_top_new, 2159 .ce[2] = gm200_ce_new, 2160 .volt = gm20b_volt_new, 2161 .dma = gf119_dma_new, 2162 .fifo = gm20b_fifo_new, 2163 .gr = gm20b_gr_new, 2164 .sw = gf100_sw_new, 2165 }; 2166 2167 static const struct nvkm_device_chip 2168 nv130_chipset = { 2169 .name = "GP100", 2170 .acr = gm200_acr_new, 2171 .bar = gm107_bar_new, 2172 .bios = nvkm_bios_new, 2173 .bus = gf100_bus_new, 2174 .devinit = gm200_devinit_new, 2175 .fault = gp100_fault_new, 2176 .fb = gp100_fb_new, 2177 .fuse = gm107_fuse_new, 2178 .gpio = gk104_gpio_new, 2179 .i2c = gm200_i2c_new, 2180 .ibus = gm200_ibus_new, 2181 .imem = nv50_instmem_new, 2182 .ltc = gp100_ltc_new, 2183 .mc = gp100_mc_new, 2184 .mmu = gp100_mmu_new, 2185 .therm = gp100_therm_new, 2186 .pci = gp100_pci_new, 2187 .pmu = gm200_pmu_new, 2188 .timer = gk20a_timer_new, 2189 .top = gk104_top_new, 2190 .ce[0] = gp100_ce_new, 2191 .ce[1] = gp100_ce_new, 2192 .ce[2] = gp100_ce_new, 2193 .ce[3] = gp100_ce_new, 2194 .ce[4] = gp100_ce_new, 2195 .ce[5] = gp100_ce_new, 2196 .dma = gf119_dma_new, 2197 .disp = gp100_disp_new, 2198 .fifo = gp100_fifo_new, 2199 .gr = gp100_gr_new, 2200 .nvdec[0] = gm107_nvdec_new, 2201 .nvenc[0] = gm107_nvenc_new, 2202 .nvenc[1] = gm107_nvenc_new, 2203 .nvenc[2] = gm107_nvenc_new, 2204 .sw = gf100_sw_new, 2205 }; 2206 2207 static const struct nvkm_device_chip 2208 nv132_chipset = { 2209 .name = "GP102", 2210 .acr = gp102_acr_new, 2211 .bar = gm107_bar_new, 2212 .bios = nvkm_bios_new, 2213 .bus = gf100_bus_new, 2214 .devinit = gm200_devinit_new, 2215 .fault = gp100_fault_new, 2216 .fb = gp102_fb_new, 2217 .fuse = gm107_fuse_new, 2218 .gpio = gk104_gpio_new, 2219 .i2c = gm200_i2c_new, 2220 .ibus = gm200_ibus_new, 2221 .imem = nv50_instmem_new, 2222 .ltc = gp102_ltc_new, 2223 .mc = gp100_mc_new, 2224 .mmu = gp100_mmu_new, 2225 .therm = gp100_therm_new, 2226 .pci = gp100_pci_new, 2227 .pmu = gp102_pmu_new, 2228 .timer = gk20a_timer_new, 2229 .top = gk104_top_new, 2230 .ce[0] = gp102_ce_new, 2231 .ce[1] = gp102_ce_new, 2232 .ce[2] = gp102_ce_new, 2233 .ce[3] = gp102_ce_new, 2234 .disp = gp102_disp_new, 2235 .dma = gf119_dma_new, 2236 .fifo = gp100_fifo_new, 2237 .gr = gp102_gr_new, 2238 .nvdec[0] = gm107_nvdec_new, 2239 .nvenc[0] = gm107_nvenc_new, 2240 .nvenc[1] = gm107_nvenc_new, 2241 .sec2 = gp102_sec2_new, 2242 .sw = gf100_sw_new, 2243 }; 2244 2245 static const struct nvkm_device_chip 2246 nv134_chipset = { 2247 .name = "GP104", 2248 .acr = gp102_acr_new, 2249 .bar = gm107_bar_new, 2250 .bios = nvkm_bios_new, 2251 .bus = gf100_bus_new, 2252 .devinit = gm200_devinit_new, 2253 .fault = gp100_fault_new, 2254 .fb = gp102_fb_new, 2255 .fuse = gm107_fuse_new, 2256 .gpio = gk104_gpio_new, 2257 .i2c = gm200_i2c_new, 2258 .ibus = gm200_ibus_new, 2259 .imem = nv50_instmem_new, 2260 .ltc = gp102_ltc_new, 2261 .mc = gp100_mc_new, 2262 .mmu = gp100_mmu_new, 2263 .therm = gp100_therm_new, 2264 .pci = gp100_pci_new, 2265 .pmu = gp102_pmu_new, 2266 .timer = gk20a_timer_new, 2267 .top = gk104_top_new, 2268 .ce[0] = gp102_ce_new, 2269 .ce[1] = gp102_ce_new, 2270 .ce[2] = gp102_ce_new, 2271 .ce[3] = gp102_ce_new, 2272 .disp = gp102_disp_new, 2273 .dma = gf119_dma_new, 2274 .fifo = gp100_fifo_new, 2275 .gr = gp104_gr_new, 2276 .nvdec[0] = gm107_nvdec_new, 2277 .nvenc[0] = gm107_nvenc_new, 2278 .nvenc[1] = gm107_nvenc_new, 2279 .sec2 = gp102_sec2_new, 2280 .sw = gf100_sw_new, 2281 }; 2282 2283 static const struct nvkm_device_chip 2284 nv136_chipset = { 2285 .name = "GP106", 2286 .acr = gp102_acr_new, 2287 .bar = gm107_bar_new, 2288 .bios = nvkm_bios_new, 2289 .bus = gf100_bus_new, 2290 .devinit = gm200_devinit_new, 2291 .fault = gp100_fault_new, 2292 .fb = gp102_fb_new, 2293 .fuse = gm107_fuse_new, 2294 .gpio = gk104_gpio_new, 2295 .i2c = gm200_i2c_new, 2296 .ibus = gm200_ibus_new, 2297 .imem = nv50_instmem_new, 2298 .ltc = gp102_ltc_new, 2299 .mc = gp100_mc_new, 2300 .mmu = gp100_mmu_new, 2301 .therm = gp100_therm_new, 2302 .pci = gp100_pci_new, 2303 .pmu = gp102_pmu_new, 2304 .timer = gk20a_timer_new, 2305 .top = gk104_top_new, 2306 .ce[0] = gp102_ce_new, 2307 .ce[1] = gp102_ce_new, 2308 .ce[2] = gp102_ce_new, 2309 .ce[3] = gp102_ce_new, 2310 .disp = gp102_disp_new, 2311 .dma = gf119_dma_new, 2312 .fifo = gp100_fifo_new, 2313 .gr = gp104_gr_new, 2314 .nvdec[0] = gm107_nvdec_new, 2315 .nvenc[0] = gm107_nvenc_new, 2316 .sec2 = gp102_sec2_new, 2317 .sw = gf100_sw_new, 2318 }; 2319 2320 static const struct nvkm_device_chip 2321 nv137_chipset = { 2322 .name = "GP107", 2323 .acr = gp102_acr_new, 2324 .bar = gm107_bar_new, 2325 .bios = nvkm_bios_new, 2326 .bus = gf100_bus_new, 2327 .devinit = gm200_devinit_new, 2328 .fault = gp100_fault_new, 2329 .fb = gp102_fb_new, 2330 .fuse = gm107_fuse_new, 2331 .gpio = gk104_gpio_new, 2332 .i2c = gm200_i2c_new, 2333 .ibus = gm200_ibus_new, 2334 .imem = nv50_instmem_new, 2335 .ltc = gp102_ltc_new, 2336 .mc = gp100_mc_new, 2337 .mmu = gp100_mmu_new, 2338 .therm = gp100_therm_new, 2339 .pci = gp100_pci_new, 2340 .pmu = gp102_pmu_new, 2341 .timer = gk20a_timer_new, 2342 .top = gk104_top_new, 2343 .ce[0] = gp102_ce_new, 2344 .ce[1] = gp102_ce_new, 2345 .ce[2] = gp102_ce_new, 2346 .ce[3] = gp102_ce_new, 2347 .disp = gp102_disp_new, 2348 .dma = gf119_dma_new, 2349 .fifo = gp100_fifo_new, 2350 .gr = gp107_gr_new, 2351 .nvdec[0] = gm107_nvdec_new, 2352 .nvenc[0] = gm107_nvenc_new, 2353 .nvenc[1] = gm107_nvenc_new, 2354 .sec2 = gp102_sec2_new, 2355 .sw = gf100_sw_new, 2356 }; 2357 2358 static const struct nvkm_device_chip 2359 nv138_chipset = { 2360 .name = "GP108", 2361 .acr = gp108_acr_new, 2362 .bar = gm107_bar_new, 2363 .bios = nvkm_bios_new, 2364 .bus = gf100_bus_new, 2365 .devinit = gm200_devinit_new, 2366 .fault = gp100_fault_new, 2367 .fb = gp102_fb_new, 2368 .fuse = gm107_fuse_new, 2369 .gpio = gk104_gpio_new, 2370 .i2c = gm200_i2c_new, 2371 .ibus = gm200_ibus_new, 2372 .imem = nv50_instmem_new, 2373 .ltc = gp102_ltc_new, 2374 .mc = gp100_mc_new, 2375 .mmu = gp100_mmu_new, 2376 .therm = gp100_therm_new, 2377 .pci = gp100_pci_new, 2378 .pmu = gp102_pmu_new, 2379 .timer = gk20a_timer_new, 2380 .top = gk104_top_new, 2381 .ce[0] = gp102_ce_new, 2382 .ce[1] = gp102_ce_new, 2383 .ce[2] = gp102_ce_new, 2384 .ce[3] = gp102_ce_new, 2385 .disp = gp102_disp_new, 2386 .dma = gf119_dma_new, 2387 .fifo = gp100_fifo_new, 2388 .gr = gp108_gr_new, 2389 .nvdec[0] = gm107_nvdec_new, 2390 .sec2 = gp108_sec2_new, 2391 .sw = gf100_sw_new, 2392 }; 2393 2394 static const struct nvkm_device_chip 2395 nv13b_chipset = { 2396 .name = "GP10B", 2397 .acr = gp10b_acr_new, 2398 .bar = gm20b_bar_new, 2399 .bus = gf100_bus_new, 2400 .fault = gp10b_fault_new, 2401 .fb = gp10b_fb_new, 2402 .fuse = gm107_fuse_new, 2403 .ibus = gp10b_ibus_new, 2404 .imem = gk20a_instmem_new, 2405 .ltc = gp10b_ltc_new, 2406 .mc = gp10b_mc_new, 2407 .mmu = gp10b_mmu_new, 2408 .pmu = gp10b_pmu_new, 2409 .timer = gk20a_timer_new, 2410 .top = gk104_top_new, 2411 .ce[0] = gp100_ce_new, 2412 .dma = gf119_dma_new, 2413 .fifo = gp10b_fifo_new, 2414 .gr = gp10b_gr_new, 2415 .sw = gf100_sw_new, 2416 }; 2417 2418 static const struct nvkm_device_chip 2419 nv140_chipset = { 2420 .name = "GV100", 2421 .acr = gp108_acr_new, 2422 .bar = gm107_bar_new, 2423 .bios = nvkm_bios_new, 2424 .bus = gf100_bus_new, 2425 .devinit = gv100_devinit_new, 2426 .fault = gv100_fault_new, 2427 .fb = gv100_fb_new, 2428 .fuse = gm107_fuse_new, 2429 .gpio = gk104_gpio_new, 2430 .gsp = gv100_gsp_new, 2431 .i2c = gm200_i2c_new, 2432 .ibus = gm200_ibus_new, 2433 .imem = nv50_instmem_new, 2434 .ltc = gp102_ltc_new, 2435 .mc = gp100_mc_new, 2436 .mmu = gv100_mmu_new, 2437 .pci = gp100_pci_new, 2438 .pmu = gp102_pmu_new, 2439 .therm = gp100_therm_new, 2440 .timer = gk20a_timer_new, 2441 .top = gk104_top_new, 2442 .disp = gv100_disp_new, 2443 .ce[0] = gv100_ce_new, 2444 .ce[1] = gv100_ce_new, 2445 .ce[2] = gv100_ce_new, 2446 .ce[3] = gv100_ce_new, 2447 .ce[4] = gv100_ce_new, 2448 .ce[5] = gv100_ce_new, 2449 .ce[6] = gv100_ce_new, 2450 .ce[7] = gv100_ce_new, 2451 .ce[8] = gv100_ce_new, 2452 .dma = gv100_dma_new, 2453 .fifo = gv100_fifo_new, 2454 .gr = gv100_gr_new, 2455 .nvdec[0] = gm107_nvdec_new, 2456 .nvenc[0] = gm107_nvenc_new, 2457 .nvenc[1] = gm107_nvenc_new, 2458 .nvenc[2] = gm107_nvenc_new, 2459 .sec2 = gp108_sec2_new, 2460 }; 2461 2462 static const struct nvkm_device_chip 2463 nv162_chipset = { 2464 .name = "TU102", 2465 .acr = tu102_acr_new, 2466 .bar = tu102_bar_new, 2467 .bios = nvkm_bios_new, 2468 .bus = gf100_bus_new, 2469 .devinit = tu102_devinit_new, 2470 .fault = tu102_fault_new, 2471 .fb = gv100_fb_new, 2472 .fuse = gm107_fuse_new, 2473 .gpio = gk104_gpio_new, 2474 .gsp = gv100_gsp_new, 2475 .i2c = gm200_i2c_new, 2476 .ibus = gm200_ibus_new, 2477 .imem = nv50_instmem_new, 2478 .ltc = gp102_ltc_new, 2479 .mc = tu102_mc_new, 2480 .mmu = tu102_mmu_new, 2481 .pci = gp100_pci_new, 2482 .pmu = gp102_pmu_new, 2483 .therm = gp100_therm_new, 2484 .timer = gk20a_timer_new, 2485 .top = gk104_top_new, 2486 .ce[0] = tu102_ce_new, 2487 .ce[1] = tu102_ce_new, 2488 .ce[2] = tu102_ce_new, 2489 .ce[3] = tu102_ce_new, 2490 .ce[4] = tu102_ce_new, 2491 .disp = tu102_disp_new, 2492 .dma = gv100_dma_new, 2493 .fifo = tu102_fifo_new, 2494 .gr = tu102_gr_new, 2495 .nvdec[0] = gm107_nvdec_new, 2496 .nvenc[0] = gm107_nvenc_new, 2497 .sec2 = tu102_sec2_new, 2498 }; 2499 2500 static const struct nvkm_device_chip 2501 nv164_chipset = { 2502 .name = "TU104", 2503 .acr = tu102_acr_new, 2504 .bar = tu102_bar_new, 2505 .bios = nvkm_bios_new, 2506 .bus = gf100_bus_new, 2507 .devinit = tu102_devinit_new, 2508 .fault = tu102_fault_new, 2509 .fb = gv100_fb_new, 2510 .fuse = gm107_fuse_new, 2511 .gpio = gk104_gpio_new, 2512 .gsp = gv100_gsp_new, 2513 .i2c = gm200_i2c_new, 2514 .ibus = gm200_ibus_new, 2515 .imem = nv50_instmem_new, 2516 .ltc = gp102_ltc_new, 2517 .mc = tu102_mc_new, 2518 .mmu = tu102_mmu_new, 2519 .pci = gp100_pci_new, 2520 .pmu = gp102_pmu_new, 2521 .therm = gp100_therm_new, 2522 .timer = gk20a_timer_new, 2523 .top = gk104_top_new, 2524 .ce[0] = tu102_ce_new, 2525 .ce[1] = tu102_ce_new, 2526 .ce[2] = tu102_ce_new, 2527 .ce[3] = tu102_ce_new, 2528 .ce[4] = tu102_ce_new, 2529 .disp = tu102_disp_new, 2530 .dma = gv100_dma_new, 2531 .fifo = tu102_fifo_new, 2532 .gr = tu102_gr_new, 2533 .nvdec[0] = gm107_nvdec_new, 2534 .nvdec[1] = gm107_nvdec_new, 2535 .nvenc[0] = gm107_nvenc_new, 2536 .sec2 = tu102_sec2_new, 2537 }; 2538 2539 static const struct nvkm_device_chip 2540 nv166_chipset = { 2541 .name = "TU106", 2542 .acr = tu102_acr_new, 2543 .bar = tu102_bar_new, 2544 .bios = nvkm_bios_new, 2545 .bus = gf100_bus_new, 2546 .devinit = tu102_devinit_new, 2547 .fault = tu102_fault_new, 2548 .fb = gv100_fb_new, 2549 .fuse = gm107_fuse_new, 2550 .gpio = gk104_gpio_new, 2551 .gsp = gv100_gsp_new, 2552 .i2c = gm200_i2c_new, 2553 .ibus = gm200_ibus_new, 2554 .imem = nv50_instmem_new, 2555 .ltc = gp102_ltc_new, 2556 .mc = tu102_mc_new, 2557 .mmu = tu102_mmu_new, 2558 .pci = gp100_pci_new, 2559 .pmu = gp102_pmu_new, 2560 .therm = gp100_therm_new, 2561 .timer = gk20a_timer_new, 2562 .top = gk104_top_new, 2563 .ce[0] = tu102_ce_new, 2564 .ce[1] = tu102_ce_new, 2565 .ce[2] = tu102_ce_new, 2566 .ce[3] = tu102_ce_new, 2567 .ce[4] = tu102_ce_new, 2568 .disp = tu102_disp_new, 2569 .dma = gv100_dma_new, 2570 .fifo = tu102_fifo_new, 2571 .gr = tu102_gr_new, 2572 .nvdec[0] = gm107_nvdec_new, 2573 .nvdec[1] = gm107_nvdec_new, 2574 .nvdec[2] = gm107_nvdec_new, 2575 .nvenc[0] = gm107_nvenc_new, 2576 .sec2 = tu102_sec2_new, 2577 }; 2578 2579 static const struct nvkm_device_chip 2580 nv167_chipset = { 2581 .name = "TU117", 2582 .acr = tu102_acr_new, 2583 .bar = tu102_bar_new, 2584 .bios = nvkm_bios_new, 2585 .bus = gf100_bus_new, 2586 .devinit = tu102_devinit_new, 2587 .fault = tu102_fault_new, 2588 .fb = gv100_fb_new, 2589 .fuse = gm107_fuse_new, 2590 .gpio = gk104_gpio_new, 2591 .gsp = gv100_gsp_new, 2592 .i2c = gm200_i2c_new, 2593 .ibus = gm200_ibus_new, 2594 .imem = nv50_instmem_new, 2595 .ltc = gp102_ltc_new, 2596 .mc = tu102_mc_new, 2597 .mmu = tu102_mmu_new, 2598 .pci = gp100_pci_new, 2599 .pmu = gp102_pmu_new, 2600 .therm = gp100_therm_new, 2601 .timer = gk20a_timer_new, 2602 .top = gk104_top_new, 2603 .ce[0] = tu102_ce_new, 2604 .ce[1] = tu102_ce_new, 2605 .ce[2] = tu102_ce_new, 2606 .ce[3] = tu102_ce_new, 2607 .ce[4] = tu102_ce_new, 2608 .disp = tu102_disp_new, 2609 .dma = gv100_dma_new, 2610 .fifo = tu102_fifo_new, 2611 .gr = tu102_gr_new, 2612 .nvdec[0] = gm107_nvdec_new, 2613 .nvenc[0] = gm107_nvenc_new, 2614 .sec2 = tu102_sec2_new, 2615 }; 2616 2617 static const struct nvkm_device_chip 2618 nv168_chipset = { 2619 .name = "TU116", 2620 .acr = tu102_acr_new, 2621 .bar = tu102_bar_new, 2622 .bios = nvkm_bios_new, 2623 .bus = gf100_bus_new, 2624 .devinit = tu102_devinit_new, 2625 .fault = tu102_fault_new, 2626 .fb = gv100_fb_new, 2627 .fuse = gm107_fuse_new, 2628 .gpio = gk104_gpio_new, 2629 .gsp = gv100_gsp_new, 2630 .i2c = gm200_i2c_new, 2631 .ibus = gm200_ibus_new, 2632 .imem = nv50_instmem_new, 2633 .ltc = gp102_ltc_new, 2634 .mc = tu102_mc_new, 2635 .mmu = tu102_mmu_new, 2636 .pci = gp100_pci_new, 2637 .pmu = gp102_pmu_new, 2638 .therm = gp100_therm_new, 2639 .timer = gk20a_timer_new, 2640 .top = gk104_top_new, 2641 .ce[0] = tu102_ce_new, 2642 .ce[1] = tu102_ce_new, 2643 .ce[2] = tu102_ce_new, 2644 .ce[3] = tu102_ce_new, 2645 .ce[4] = tu102_ce_new, 2646 .disp = tu102_disp_new, 2647 .dma = gv100_dma_new, 2648 .fifo = tu102_fifo_new, 2649 .gr = tu102_gr_new, 2650 .nvdec[0] = gm107_nvdec_new, 2651 .nvenc[0] = gm107_nvenc_new, 2652 .sec2 = tu102_sec2_new, 2653 }; 2654 2655 static const struct nvkm_device_chip 2656 nv170_chipset = { 2657 .name = "GA100", 2658 .bar = tu102_bar_new, 2659 .bios = nvkm_bios_new, 2660 .devinit = ga100_devinit_new, 2661 .fb = ga100_fb_new, 2662 .gpio = gk104_gpio_new, 2663 .i2c = gm200_i2c_new, 2664 .ibus = gm200_ibus_new, 2665 .imem = nv50_instmem_new, 2666 .mc = ga100_mc_new, 2667 .mmu = tu102_mmu_new, 2668 .pci = gp100_pci_new, 2669 .timer = gk20a_timer_new, 2670 }; 2671 2672 static const struct nvkm_device_chip 2673 nv172_chipset = { 2674 .name = "GA102", 2675 .bar = tu102_bar_new, 2676 .bios = nvkm_bios_new, 2677 .devinit = ga100_devinit_new, 2678 .fb = ga102_fb_new, 2679 .gpio = ga102_gpio_new, 2680 .i2c = gm200_i2c_new, 2681 .ibus = gm200_ibus_new, 2682 .imem = nv50_instmem_new, 2683 .mc = ga100_mc_new, 2684 .mmu = tu102_mmu_new, 2685 .pci = gp100_pci_new, 2686 .timer = gk20a_timer_new, 2687 .disp = ga102_disp_new, 2688 .dma = gv100_dma_new, 2689 }; 2690 2691 static const struct nvkm_device_chip 2692 nv174_chipset = { 2693 .name = "GA104", 2694 .bar = tu102_bar_new, 2695 .bios = nvkm_bios_new, 2696 .devinit = ga100_devinit_new, 2697 .fb = ga102_fb_new, 2698 .gpio = ga102_gpio_new, 2699 .i2c = gm200_i2c_new, 2700 .ibus = gm200_ibus_new, 2701 .imem = nv50_instmem_new, 2702 .mc = ga100_mc_new, 2703 .mmu = tu102_mmu_new, 2704 .pci = gp100_pci_new, 2705 .timer = gk20a_timer_new, 2706 .disp = ga102_disp_new, 2707 .dma = gv100_dma_new, 2708 }; 2709 2710 static int 2711 nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size, 2712 struct nvkm_notify *notify) 2713 { 2714 if (!WARN_ON(size != 0)) { 2715 notify->size = 0; 2716 notify->types = 1; 2717 notify->index = 0; 2718 return 0; 2719 } 2720 return -EINVAL; 2721 } 2722 2723 static const struct nvkm_event_func 2724 nvkm_device_event_func = { 2725 .ctor = nvkm_device_event_ctor, 2726 }; 2727 2728 struct nvkm_subdev * 2729 nvkm_device_subdev(struct nvkm_device *device, int index) 2730 { 2731 struct nvkm_engine *engine; 2732 2733 if (device->disable_mask & (1ULL << index)) 2734 return NULL; 2735 2736 switch (index) { 2737 #define _(n,p,m) case NVKM_SUBDEV_##n: if (p) return (m); break 2738 _(ACR , device->acr , &device->acr->subdev); 2739 _(BAR , device->bar , &device->bar->subdev); 2740 _(VBIOS , device->bios , &device->bios->subdev); 2741 _(BUS , device->bus , &device->bus->subdev); 2742 _(CLK , device->clk , &device->clk->subdev); 2743 _(DEVINIT , device->devinit , &device->devinit->subdev); 2744 _(FAULT , device->fault , &device->fault->subdev); 2745 _(FB , device->fb , &device->fb->subdev); 2746 _(FUSE , device->fuse , &device->fuse->subdev); 2747 _(GPIO , device->gpio , &device->gpio->subdev); 2748 _(GSP , device->gsp , &device->gsp->subdev); 2749 _(I2C , device->i2c , &device->i2c->subdev); 2750 _(IBUS , device->ibus , device->ibus); 2751 _(ICCSENSE, device->iccsense, &device->iccsense->subdev); 2752 _(INSTMEM , device->imem , &device->imem->subdev); 2753 _(LTC , device->ltc , &device->ltc->subdev); 2754 _(MC , device->mc , &device->mc->subdev); 2755 _(MMU , device->mmu , &device->mmu->subdev); 2756 _(MXM , device->mxm , device->mxm); 2757 _(PCI , device->pci , &device->pci->subdev); 2758 _(PMU , device->pmu , &device->pmu->subdev); 2759 _(THERM , device->therm , &device->therm->subdev); 2760 _(TIMER , device->timer , &device->timer->subdev); 2761 _(TOP , device->top , &device->top->subdev); 2762 _(VOLT , device->volt , &device->volt->subdev); 2763 #undef _ 2764 default: 2765 engine = nvkm_device_engine(device, index); 2766 if (engine) 2767 return &engine->subdev; 2768 break; 2769 } 2770 return NULL; 2771 } 2772 2773 struct nvkm_engine * 2774 nvkm_device_engine(struct nvkm_device *device, int index) 2775 { 2776 if (device->disable_mask & (1ULL << index)) 2777 return NULL; 2778 2779 switch (index) { 2780 #define _(n,p,m) case NVKM_ENGINE_##n: if (p) return (m); break 2781 _(BSP , device->bsp , device->bsp); 2782 _(CE0 , device->ce[0] , device->ce[0]); 2783 _(CE1 , device->ce[1] , device->ce[1]); 2784 _(CE2 , device->ce[2] , device->ce[2]); 2785 _(CE3 , device->ce[3] , device->ce[3]); 2786 _(CE4 , device->ce[4] , device->ce[4]); 2787 _(CE5 , device->ce[5] , device->ce[5]); 2788 _(CE6 , device->ce[6] , device->ce[6]); 2789 _(CE7 , device->ce[7] , device->ce[7]); 2790 _(CE8 , device->ce[8] , device->ce[8]); 2791 _(CIPHER , device->cipher , device->cipher); 2792 _(DISP , device->disp , &device->disp->engine); 2793 _(DMAOBJ , device->dma , &device->dma->engine); 2794 _(FIFO , device->fifo , &device->fifo->engine); 2795 _(GR , device->gr , &device->gr->engine); 2796 _(IFB , device->ifb , device->ifb); 2797 _(ME , device->me , device->me); 2798 _(MPEG , device->mpeg , device->mpeg); 2799 _(MSENC , device->msenc , device->msenc); 2800 _(MSPDEC , device->mspdec , device->mspdec); 2801 _(MSPPP , device->msppp , device->msppp); 2802 _(MSVLD , device->msvld , device->msvld); 2803 _(NVENC0 , device->nvenc[0], &device->nvenc[0]->engine); 2804 _(NVENC1 , device->nvenc[1], &device->nvenc[1]->engine); 2805 _(NVENC2 , device->nvenc[2], &device->nvenc[2]->engine); 2806 _(NVDEC0 , device->nvdec[0], &device->nvdec[0]->engine); 2807 _(NVDEC1 , device->nvdec[1], &device->nvdec[1]->engine); 2808 _(NVDEC2 , device->nvdec[2], &device->nvdec[2]->engine); 2809 _(PM , device->pm , &device->pm->engine); 2810 _(SEC , device->sec , device->sec); 2811 _(SEC2 , device->sec2 , &device->sec2->engine); 2812 _(SW , device->sw , &device->sw->engine); 2813 _(VIC , device->vic , device->vic); 2814 _(VP , device->vp , device->vp); 2815 #undef _ 2816 default: 2817 WARN_ON(1); 2818 break; 2819 } 2820 return NULL; 2821 } 2822 2823 int 2824 nvkm_device_fini(struct nvkm_device *device, bool suspend) 2825 { 2826 const char *action = suspend ? "suspend" : "fini"; 2827 struct nvkm_subdev *subdev; 2828 int ret, i; 2829 s64 time; 2830 2831 nvdev_trace(device, "%s running...\n", action); 2832 time = ktime_to_us(ktime_get()); 2833 2834 nvkm_acpi_fini(device); 2835 2836 for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { 2837 if ((subdev = nvkm_device_subdev(device, i))) { 2838 ret = nvkm_subdev_fini(subdev, suspend); 2839 if (ret && suspend) 2840 goto fail; 2841 } 2842 } 2843 2844 nvkm_therm_clkgate_fini(device->therm, suspend); 2845 2846 if (device->func->fini) 2847 device->func->fini(device, suspend); 2848 2849 time = ktime_to_us(ktime_get()) - time; 2850 nvdev_trace(device, "%s completed in %lldus...\n", action, time); 2851 return 0; 2852 2853 fail: 2854 do { 2855 if ((subdev = nvkm_device_subdev(device, i))) { 2856 int rret = nvkm_subdev_init(subdev); 2857 if (rret) 2858 nvkm_fatal(subdev, "failed restart, %d\n", ret); 2859 } 2860 } while (++i < NVKM_SUBDEV_NR); 2861 2862 nvdev_trace(device, "%s failed with %d\n", action, ret); 2863 return ret; 2864 } 2865 2866 static int 2867 nvkm_device_preinit(struct nvkm_device *device) 2868 { 2869 struct nvkm_subdev *subdev; 2870 int ret, i; 2871 s64 time; 2872 2873 nvdev_trace(device, "preinit running...\n"); 2874 time = ktime_to_us(ktime_get()); 2875 2876 if (device->func->preinit) { 2877 ret = device->func->preinit(device); 2878 if (ret) 2879 goto fail; 2880 } 2881 2882 for (i = 0; i < NVKM_SUBDEV_NR; i++) { 2883 if ((subdev = nvkm_device_subdev(device, i))) { 2884 ret = nvkm_subdev_preinit(subdev); 2885 if (ret) 2886 goto fail; 2887 } 2888 } 2889 2890 ret = nvkm_devinit_post(device->devinit, &device->disable_mask); 2891 if (ret) 2892 goto fail; 2893 2894 time = ktime_to_us(ktime_get()) - time; 2895 nvdev_trace(device, "preinit completed in %lldus\n", time); 2896 return 0; 2897 2898 fail: 2899 nvdev_error(device, "preinit failed with %d\n", ret); 2900 return ret; 2901 } 2902 2903 int 2904 nvkm_device_init(struct nvkm_device *device) 2905 { 2906 struct nvkm_subdev *subdev; 2907 int ret, i; 2908 s64 time; 2909 2910 ret = nvkm_device_preinit(device); 2911 if (ret) 2912 return ret; 2913 2914 nvkm_device_fini(device, false); 2915 2916 nvdev_trace(device, "init running...\n"); 2917 time = ktime_to_us(ktime_get()); 2918 2919 if (device->func->init) { 2920 ret = device->func->init(device); 2921 if (ret) 2922 goto fail; 2923 } 2924 2925 for (i = 0; i < NVKM_SUBDEV_NR; i++) { 2926 if ((subdev = nvkm_device_subdev(device, i))) { 2927 ret = nvkm_subdev_init(subdev); 2928 if (ret) 2929 goto fail_subdev; 2930 } 2931 } 2932 2933 nvkm_acpi_init(device); 2934 nvkm_therm_clkgate_enable(device->therm); 2935 2936 time = ktime_to_us(ktime_get()) - time; 2937 nvdev_trace(device, "init completed in %lldus\n", time); 2938 return 0; 2939 2940 fail_subdev: 2941 do { 2942 if ((subdev = nvkm_device_subdev(device, i))) 2943 nvkm_subdev_fini(subdev, false); 2944 } while (--i >= 0); 2945 2946 fail: 2947 nvkm_device_fini(device, false); 2948 2949 nvdev_error(device, "init failed with %d\n", ret); 2950 return ret; 2951 } 2952 2953 void 2954 nvkm_device_del(struct nvkm_device **pdevice) 2955 { 2956 struct nvkm_device *device = *pdevice; 2957 int i; 2958 if (device) { 2959 mutex_lock(&nv_devices_mutex); 2960 device->disable_mask = 0; 2961 for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { 2962 struct nvkm_subdev *subdev = 2963 nvkm_device_subdev(device, i); 2964 nvkm_subdev_del(&subdev); 2965 } 2966 2967 nvkm_event_fini(&device->event); 2968 2969 if (device->pri) 2970 iounmap(device->pri); 2971 list_del(&device->head); 2972 2973 if (device->func->dtor) 2974 *pdevice = device->func->dtor(device); 2975 mutex_unlock(&nv_devices_mutex); 2976 2977 kfree(*pdevice); 2978 *pdevice = NULL; 2979 } 2980 } 2981 2982 /* returns true if the GPU is in the CPU native byte order */ 2983 static inline bool 2984 nvkm_device_endianness(struct nvkm_device *device) 2985 { 2986 #ifdef __BIG_ENDIAN 2987 const bool big_endian = true; 2988 #else 2989 const bool big_endian = false; 2990 #endif 2991 2992 /* Read NV_PMC_BOOT_1, and assume non-functional endian switch if it 2993 * doesn't contain the expected values. 2994 */ 2995 u32 pmc_boot_1 = nvkm_rd32(device, 0x000004); 2996 if (pmc_boot_1 && pmc_boot_1 != 0x01000001) 2997 return !big_endian; /* Assume GPU is LE in this case. */ 2998 2999 /* 0 means LE and 0x01000001 means BE GPU. Condition is true when 3000 * GPU/CPU endianness don't match. 3001 */ 3002 if (big_endian == !pmc_boot_1) { 3003 nvkm_wr32(device, 0x000004, 0x01000001); 3004 nvkm_rd32(device, 0x000000); 3005 if (nvkm_rd32(device, 0x000004) != (big_endian ? 0x01000001 : 0x00000000)) 3006 return !big_endian; /* Assume GPU is LE on any unexpected read-back. */ 3007 } 3008 3009 /* CPU/GPU endianness should (hopefully) match. */ 3010 return true; 3011 } 3012 3013 int 3014 nvkm_device_ctor(const struct nvkm_device_func *func, 3015 const struct nvkm_device_quirk *quirk, 3016 struct device *dev, enum nvkm_device_type type, u64 handle, 3017 const char *name, const char *cfg, const char *dbg, 3018 bool detect, bool mmio, u64 subdev_mask, 3019 struct nvkm_device *device) 3020 { 3021 struct nvkm_subdev *subdev; 3022 u64 mmio_base, mmio_size; 3023 u32 boot0, boot1, strap; 3024 int ret = -EEXIST, i; 3025 unsigned chipset; 3026 3027 mutex_lock(&nv_devices_mutex); 3028 if (nvkm_device_find_locked(handle)) 3029 goto done; 3030 3031 device->func = func; 3032 device->quirk = quirk; 3033 device->dev = dev; 3034 device->type = type; 3035 device->handle = handle; 3036 device->cfgopt = cfg; 3037 device->dbgopt = dbg; 3038 device->name = name; 3039 list_add_tail(&device->head, &nv_devices); 3040 device->debug = nvkm_dbgopt(device->dbgopt, "device"); 3041 3042 ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event); 3043 if (ret) 3044 goto done; 3045 3046 mmio_base = device->func->resource_addr(device, 0); 3047 mmio_size = device->func->resource_size(device, 0); 3048 3049 if (detect || mmio) { 3050 device->pri = ioremap(mmio_base, mmio_size); 3051 if (device->pri == NULL) { 3052 nvdev_error(device, "unable to map PRI\n"); 3053 ret = -ENOMEM; 3054 goto done; 3055 } 3056 } 3057 3058 /* identify the chipset, and determine classes of subdev/engines */ 3059 if (detect) { 3060 /* switch mmio to cpu's native endianness */ 3061 if (!nvkm_device_endianness(device)) { 3062 nvdev_error(device, 3063 "Couldn't switch GPU to CPUs endianess\n"); 3064 ret = -ENOSYS; 3065 goto done; 3066 } 3067 3068 boot0 = nvkm_rd32(device, 0x000000); 3069 3070 /* chipset can be overridden for devel/testing purposes */ 3071 chipset = nvkm_longopt(device->cfgopt, "NvChipset", 0); 3072 if (chipset) { 3073 u32 override_boot0; 3074 3075 if (chipset >= 0x10) { 3076 override_boot0 = ((chipset & 0x1ff) << 20); 3077 override_boot0 |= 0x000000a1; 3078 } else { 3079 if (chipset != 0x04) 3080 override_boot0 = 0x20104000; 3081 else 3082 override_boot0 = 0x20004000; 3083 } 3084 3085 nvdev_warn(device, "CHIPSET OVERRIDE: %08x -> %08x\n", 3086 boot0, override_boot0); 3087 boot0 = override_boot0; 3088 } 3089 3090 /* determine chipset and derive architecture from it */ 3091 if ((boot0 & 0x1f000000) > 0) { 3092 device->chipset = (boot0 & 0x1ff00000) >> 20; 3093 device->chiprev = (boot0 & 0x000000ff); 3094 switch (device->chipset & 0x1f0) { 3095 case 0x010: { 3096 if (0x461 & (1 << (device->chipset & 0xf))) 3097 device->card_type = NV_10; 3098 else 3099 device->card_type = NV_11; 3100 device->chiprev = 0x00; 3101 break; 3102 } 3103 case 0x020: device->card_type = NV_20; break; 3104 case 0x030: device->card_type = NV_30; break; 3105 case 0x040: 3106 case 0x060: device->card_type = NV_40; break; 3107 case 0x050: 3108 case 0x080: 3109 case 0x090: 3110 case 0x0a0: device->card_type = NV_50; break; 3111 case 0x0c0: 3112 case 0x0d0: device->card_type = NV_C0; break; 3113 case 0x0e0: 3114 case 0x0f0: 3115 case 0x100: device->card_type = NV_E0; break; 3116 case 0x110: 3117 case 0x120: device->card_type = GM100; break; 3118 case 0x130: device->card_type = GP100; break; 3119 case 0x140: device->card_type = GV100; break; 3120 case 0x160: device->card_type = TU100; break; 3121 case 0x170: device->card_type = GA100; break; 3122 default: 3123 break; 3124 } 3125 } else 3126 if ((boot0 & 0xff00fff0) == 0x20004000) { 3127 if (boot0 & 0x00f00000) 3128 device->chipset = 0x05; 3129 else 3130 device->chipset = 0x04; 3131 device->card_type = NV_04; 3132 } 3133 3134 switch (device->chipset) { 3135 case 0x004: device->chip = &nv4_chipset; break; 3136 case 0x005: device->chip = &nv5_chipset; break; 3137 case 0x010: device->chip = &nv10_chipset; break; 3138 case 0x011: device->chip = &nv11_chipset; break; 3139 case 0x015: device->chip = &nv15_chipset; break; 3140 case 0x017: device->chip = &nv17_chipset; break; 3141 case 0x018: device->chip = &nv18_chipset; break; 3142 case 0x01a: device->chip = &nv1a_chipset; break; 3143 case 0x01f: device->chip = &nv1f_chipset; break; 3144 case 0x020: device->chip = &nv20_chipset; break; 3145 case 0x025: device->chip = &nv25_chipset; break; 3146 case 0x028: device->chip = &nv28_chipset; break; 3147 case 0x02a: device->chip = &nv2a_chipset; break; 3148 case 0x030: device->chip = &nv30_chipset; break; 3149 case 0x031: device->chip = &nv31_chipset; break; 3150 case 0x034: device->chip = &nv34_chipset; break; 3151 case 0x035: device->chip = &nv35_chipset; break; 3152 case 0x036: device->chip = &nv36_chipset; break; 3153 case 0x040: device->chip = &nv40_chipset; break; 3154 case 0x041: device->chip = &nv41_chipset; break; 3155 case 0x042: device->chip = &nv42_chipset; break; 3156 case 0x043: device->chip = &nv43_chipset; break; 3157 case 0x044: device->chip = &nv44_chipset; break; 3158 case 0x045: device->chip = &nv45_chipset; break; 3159 case 0x046: device->chip = &nv46_chipset; break; 3160 case 0x047: device->chip = &nv47_chipset; break; 3161 case 0x049: device->chip = &nv49_chipset; break; 3162 case 0x04a: device->chip = &nv4a_chipset; break; 3163 case 0x04b: device->chip = &nv4b_chipset; break; 3164 case 0x04c: device->chip = &nv4c_chipset; break; 3165 case 0x04e: device->chip = &nv4e_chipset; break; 3166 case 0x050: device->chip = &nv50_chipset; break; 3167 case 0x063: device->chip = &nv63_chipset; break; 3168 case 0x067: device->chip = &nv67_chipset; break; 3169 case 0x068: device->chip = &nv68_chipset; break; 3170 case 0x084: device->chip = &nv84_chipset; break; 3171 case 0x086: device->chip = &nv86_chipset; break; 3172 case 0x092: device->chip = &nv92_chipset; break; 3173 case 0x094: device->chip = &nv94_chipset; break; 3174 case 0x096: device->chip = &nv96_chipset; break; 3175 case 0x098: device->chip = &nv98_chipset; break; 3176 case 0x0a0: device->chip = &nva0_chipset; break; 3177 case 0x0a3: device->chip = &nva3_chipset; break; 3178 case 0x0a5: device->chip = &nva5_chipset; break; 3179 case 0x0a8: device->chip = &nva8_chipset; break; 3180 case 0x0aa: device->chip = &nvaa_chipset; break; 3181 case 0x0ac: device->chip = &nvac_chipset; break; 3182 case 0x0af: device->chip = &nvaf_chipset; break; 3183 case 0x0c0: device->chip = &nvc0_chipset; break; 3184 case 0x0c1: device->chip = &nvc1_chipset; break; 3185 case 0x0c3: device->chip = &nvc3_chipset; break; 3186 case 0x0c4: device->chip = &nvc4_chipset; break; 3187 case 0x0c8: device->chip = &nvc8_chipset; break; 3188 case 0x0ce: device->chip = &nvce_chipset; break; 3189 case 0x0cf: device->chip = &nvcf_chipset; break; 3190 case 0x0d7: device->chip = &nvd7_chipset; break; 3191 case 0x0d9: device->chip = &nvd9_chipset; break; 3192 case 0x0e4: device->chip = &nve4_chipset; break; 3193 case 0x0e6: device->chip = &nve6_chipset; break; 3194 case 0x0e7: device->chip = &nve7_chipset; break; 3195 case 0x0ea: device->chip = &nvea_chipset; break; 3196 case 0x0f0: device->chip = &nvf0_chipset; break; 3197 case 0x0f1: device->chip = &nvf1_chipset; break; 3198 case 0x106: device->chip = &nv106_chipset; break; 3199 case 0x108: device->chip = &nv108_chipset; break; 3200 case 0x117: device->chip = &nv117_chipset; break; 3201 case 0x118: device->chip = &nv118_chipset; break; 3202 case 0x120: device->chip = &nv120_chipset; break; 3203 case 0x124: device->chip = &nv124_chipset; break; 3204 case 0x126: device->chip = &nv126_chipset; break; 3205 case 0x12b: device->chip = &nv12b_chipset; break; 3206 case 0x130: device->chip = &nv130_chipset; break; 3207 case 0x132: device->chip = &nv132_chipset; break; 3208 case 0x134: device->chip = &nv134_chipset; break; 3209 case 0x136: device->chip = &nv136_chipset; break; 3210 case 0x137: device->chip = &nv137_chipset; break; 3211 case 0x138: device->chip = &nv138_chipset; break; 3212 case 0x13b: device->chip = &nv13b_chipset; break; 3213 case 0x140: device->chip = &nv140_chipset; break; 3214 case 0x162: device->chip = &nv162_chipset; break; 3215 case 0x164: device->chip = &nv164_chipset; break; 3216 case 0x166: device->chip = &nv166_chipset; break; 3217 case 0x167: device->chip = &nv167_chipset; break; 3218 case 0x168: device->chip = &nv168_chipset; break; 3219 case 0x172: device->chip = &nv172_chipset; break; 3220 case 0x174: device->chip = &nv174_chipset; break; 3221 default: 3222 if (nvkm_boolopt(device->cfgopt, "NvEnableUnsupportedChipsets", false)) { 3223 switch (device->chipset) { 3224 case 0x170: device->chip = &nv170_chipset; break; 3225 default: 3226 break; 3227 } 3228 } 3229 3230 if (!device->chip) { 3231 nvdev_error(device, "unknown chipset (%08x)\n", boot0); 3232 ret = -ENODEV; 3233 goto done; 3234 } 3235 break; 3236 } 3237 3238 nvdev_info(device, "NVIDIA %s (%08x)\n", 3239 device->chip->name, boot0); 3240 3241 /* vGPU detection */ 3242 boot1 = nvkm_rd32(device, 0x0000004); 3243 if (device->card_type >= TU100 && (boot1 & 0x00030000)) { 3244 nvdev_info(device, "vGPUs are not supported\n"); 3245 ret = -ENODEV; 3246 goto done; 3247 } 3248 3249 /* read strapping information */ 3250 strap = nvkm_rd32(device, 0x101000); 3251 3252 /* determine frequency of timing crystal */ 3253 if ( device->card_type <= NV_10 || device->chipset < 0x17 || 3254 (device->chipset >= 0x20 && device->chipset < 0x25)) 3255 strap &= 0x00000040; 3256 else 3257 strap &= 0x00400040; 3258 3259 switch (strap) { 3260 case 0x00000000: device->crystal = 13500; break; 3261 case 0x00000040: device->crystal = 14318; break; 3262 case 0x00400000: device->crystal = 27000; break; 3263 case 0x00400040: device->crystal = 25000; break; 3264 } 3265 } else { 3266 device->chip = &null_chipset; 3267 } 3268 3269 if (!device->name) 3270 device->name = device->chip->name; 3271 3272 mutex_init(&device->mutex); 3273 3274 for (i = 0; i < NVKM_SUBDEV_NR; i++) { 3275 #define _(s,m) case s: \ 3276 if (device->chip->m && (subdev_mask & (1ULL << (s)))) { \ 3277 ret = device->chip->m(device, (s), &device->m); \ 3278 if (ret) { \ 3279 subdev = nvkm_device_subdev(device, (s)); \ 3280 nvkm_subdev_del(&subdev); \ 3281 device->m = NULL; \ 3282 if (ret != -ENODEV) { \ 3283 nvdev_error(device, "%s ctor failed, %d\n", \ 3284 nvkm_subdev_name[s], ret); \ 3285 goto done; \ 3286 } \ 3287 } \ 3288 } \ 3289 break 3290 switch (i) { 3291 _(NVKM_SUBDEV_ACR , acr); 3292 _(NVKM_SUBDEV_BAR , bar); 3293 _(NVKM_SUBDEV_VBIOS , bios); 3294 _(NVKM_SUBDEV_BUS , bus); 3295 _(NVKM_SUBDEV_CLK , clk); 3296 _(NVKM_SUBDEV_DEVINIT , devinit); 3297 _(NVKM_SUBDEV_FAULT , fault); 3298 _(NVKM_SUBDEV_FB , fb); 3299 _(NVKM_SUBDEV_FUSE , fuse); 3300 _(NVKM_SUBDEV_GPIO , gpio); 3301 _(NVKM_SUBDEV_GSP , gsp); 3302 _(NVKM_SUBDEV_I2C , i2c); 3303 _(NVKM_SUBDEV_IBUS , ibus); 3304 _(NVKM_SUBDEV_ICCSENSE, iccsense); 3305 _(NVKM_SUBDEV_INSTMEM , imem); 3306 _(NVKM_SUBDEV_LTC , ltc); 3307 _(NVKM_SUBDEV_MC , mc); 3308 _(NVKM_SUBDEV_MMU , mmu); 3309 _(NVKM_SUBDEV_MXM , mxm); 3310 _(NVKM_SUBDEV_PCI , pci); 3311 _(NVKM_SUBDEV_PMU , pmu); 3312 _(NVKM_SUBDEV_THERM , therm); 3313 _(NVKM_SUBDEV_TIMER , timer); 3314 _(NVKM_SUBDEV_TOP , top); 3315 _(NVKM_SUBDEV_VOLT , volt); 3316 _(NVKM_ENGINE_BSP , bsp); 3317 _(NVKM_ENGINE_CE0 , ce[0]); 3318 _(NVKM_ENGINE_CE1 , ce[1]); 3319 _(NVKM_ENGINE_CE2 , ce[2]); 3320 _(NVKM_ENGINE_CE3 , ce[3]); 3321 _(NVKM_ENGINE_CE4 , ce[4]); 3322 _(NVKM_ENGINE_CE5 , ce[5]); 3323 _(NVKM_ENGINE_CE6 , ce[6]); 3324 _(NVKM_ENGINE_CE7 , ce[7]); 3325 _(NVKM_ENGINE_CE8 , ce[8]); 3326 _(NVKM_ENGINE_CIPHER , cipher); 3327 _(NVKM_ENGINE_DISP , disp); 3328 _(NVKM_ENGINE_DMAOBJ , dma); 3329 _(NVKM_ENGINE_FIFO , fifo); 3330 _(NVKM_ENGINE_GR , gr); 3331 _(NVKM_ENGINE_IFB , ifb); 3332 _(NVKM_ENGINE_ME , me); 3333 _(NVKM_ENGINE_MPEG , mpeg); 3334 _(NVKM_ENGINE_MSENC , msenc); 3335 _(NVKM_ENGINE_MSPDEC , mspdec); 3336 _(NVKM_ENGINE_MSPPP , msppp); 3337 _(NVKM_ENGINE_MSVLD , msvld); 3338 _(NVKM_ENGINE_NVENC0 , nvenc[0]); 3339 _(NVKM_ENGINE_NVENC1 , nvenc[1]); 3340 _(NVKM_ENGINE_NVENC2 , nvenc[2]); 3341 _(NVKM_ENGINE_NVDEC0 , nvdec[0]); 3342 _(NVKM_ENGINE_NVDEC1 , nvdec[1]); 3343 _(NVKM_ENGINE_NVDEC2 , nvdec[2]); 3344 _(NVKM_ENGINE_PM , pm); 3345 _(NVKM_ENGINE_SEC , sec); 3346 _(NVKM_ENGINE_SEC2 , sec2); 3347 _(NVKM_ENGINE_SW , sw); 3348 _(NVKM_ENGINE_VIC , vic); 3349 _(NVKM_ENGINE_VP , vp); 3350 default: 3351 WARN_ON(1); 3352 continue; 3353 } 3354 #undef _ 3355 } 3356 3357 ret = 0; 3358 done: 3359 if (device->pri && (!mmio || ret)) { 3360 iounmap(device->pri); 3361 device->pri = NULL; 3362 } 3363 mutex_unlock(&nv_devices_mutex); 3364 return ret; 3365 } 3366