1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include <engine/ce.h>
25 #include <engine/fifo.h>
26 #include "fuc/gt215.fuc3.h"
27 
28 #include <core/client.h>
29 #include <core/enum.h>
30 
31 #include <nvif/class.h>
32 
33 static const struct nvkm_enum
34 gt215_ce_isr_error_name[] = {
35 	{ 0x0001, "ILLEGAL_MTHD" },
36 	{ 0x0002, "INVALID_ENUM" },
37 	{ 0x0003, "INVALID_BITFIELD" },
38 	{}
39 };
40 
41 void
42 gt215_ce_intr(struct nvkm_falcon *ce, struct nvkm_fifo_chan *chan)
43 {
44 	struct nvkm_subdev *subdev = &ce->engine.subdev;
45 	struct nvkm_device *device = subdev->device;
46 	const u32 base = (nv_subidx(subdev) - NVDEV_ENGINE_CE0) * 0x1000;
47 	u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff;
48 	u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16;
49 	u32 mthd = (addr & 0x07ff) << 2;
50 	u32 subc = (addr & 0x3800) >> 11;
51 	u32 data = nvkm_rd32(device, 0x104044 + base);
52 	const struct nvkm_enum *en =
53 		nvkm_enum_find(gt215_ce_isr_error_name, ssta);
54 
55 	nvkm_error(subdev, "DISPATCH_ERROR %04x [%s] ch %d [%010llx %s] "
56 			   "subc %d mthd %04x data %08x\n", ssta,
57 		   en ? en->name : "", chan ? chan->chid : -1,
58 		   chan ? chan->inst->addr : 0,
59 		   chan ? chan->object.client->name : "unknown",
60 		   subc, mthd, data);
61 }
62 
63 static const struct nvkm_falcon_func
64 gt215_ce_func = {
65 	.intr = gt215_ce_intr,
66 	.sclass = {
67 		{ -1, -1, GT212_DMA },
68 		{}
69 	}
70 };
71 
72 static int
73 gt215_ce_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
74 	      struct nvkm_oclass *oclass, void *data, u32 size,
75 	      struct nvkm_object **pobject)
76 {
77 	bool enable = (nv_device(parent)->chipset != 0xaf);
78 	struct nvkm_falcon *ce;
79 	int ret;
80 
81 	ret = nvkm_falcon_create(&gt215_ce_func, parent, engine, oclass,
82 				 0x104000, enable, "PCE0", "ce0", &ce);
83 	*pobject = nv_object(ce);
84 	if (ret)
85 		return ret;
86 
87 	nv_subdev(ce)->unit = 0x00802000;
88 	nv_falcon(ce)->code.data = gt215_ce_code;
89 	nv_falcon(ce)->code.size = sizeof(gt215_ce_code);
90 	nv_falcon(ce)->data.data = gt215_ce_data;
91 	nv_falcon(ce)->data.size = sizeof(gt215_ce_data);
92 	return 0;
93 }
94 
95 struct nvkm_oclass
96 gt215_ce_oclass = {
97 	.handle = NV_ENGINE(CE0, 0xa3),
98 	.ofuncs = &(struct nvkm_ofuncs) {
99 		.ctor = gt215_ce_ctor,
100 		.dtor = _nvkm_falcon_dtor,
101 		.init = _nvkm_falcon_init,
102 		.fini = _nvkm_falcon_fini,
103 	},
104 };
105