1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include <engine/ce.h>
25 #include <engine/falcon.h>
26 #include <engine/fifo.h>
27 #include "fuc/gt215.fuc3.h"
28 
29 #include <core/client.h>
30 #include <core/enum.h>
31 
32 /*******************************************************************************
33  * Copy object classes
34  ******************************************************************************/
35 
36 static struct nvkm_oclass
37 gt215_ce_sclass[] = {
38 	{ 0x85b5, &nvkm_object_ofuncs },
39 	{}
40 };
41 
42 /*******************************************************************************
43  * PCE context
44  ******************************************************************************/
45 
46 static struct nvkm_oclass
47 gt215_ce_cclass = {
48 	.handle = NV_ENGCTX(CE0, 0xa3),
49 	.ofuncs = &(struct nvkm_ofuncs) {
50 		.ctor = _nvkm_falcon_context_ctor,
51 		.dtor = _nvkm_falcon_context_dtor,
52 		.init = _nvkm_falcon_context_init,
53 		.fini = _nvkm_falcon_context_fini,
54 		.rd32 = _nvkm_falcon_context_rd32,
55 		.wr32 = _nvkm_falcon_context_wr32,
56 
57 	},
58 };
59 
60 /*******************************************************************************
61  * PCE engine/subdev functions
62  ******************************************************************************/
63 
64 static const struct nvkm_enum
65 gt215_ce_isr_error_name[] = {
66 	{ 0x0001, "ILLEGAL_MTHD" },
67 	{ 0x0002, "INVALID_ENUM" },
68 	{ 0x0003, "INVALID_BITFIELD" },
69 	{}
70 };
71 
72 void
73 gt215_ce_intr(struct nvkm_subdev *subdev)
74 {
75 	struct nvkm_falcon *ce = (void *)subdev;
76 	struct nvkm_engine *engine = &ce->engine;
77 	struct nvkm_device *device = engine->subdev.device;
78 	struct nvkm_fifo *fifo = device->fifo;
79 	struct nvkm_object *engctx;
80 	const struct nvkm_enum *en;
81 	const u32 base = (nv_subidx(subdev) - NVDEV_ENGINE_CE0) * 0x1000;
82 	u32 dispatch = nvkm_rd32(device, 0x10401c + base);
83 	u32 stat = nvkm_rd32(device, 0x104008 + base) & dispatch & ~(dispatch >> 16);
84 	u64 inst = nvkm_rd32(device, 0x104050 + base) & 0x3fffffff;
85 	u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff;
86 	u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16;
87 	u32 mthd = (addr & 0x07ff) << 2;
88 	u32 subc = (addr & 0x3800) >> 11;
89 	u32 data = nvkm_rd32(device, 0x104044 + base);
90 	int chid;
91 
92 	engctx = nvkm_engctx_get(engine, inst);
93 	chid   = fifo->chid(fifo, engctx);
94 
95 	if (stat & 0x00000040) {
96 		en = nvkm_enum_find(gt215_ce_isr_error_name, ssta);
97 		nvkm_error(subdev, "DISPATCH_ERROR %04x [%s] "
98 				   "ch %d [%010llx %s] subc %d "
99 				   "mthd %04x data %08x\n",
100 			   ssta, en ? en->name : "", chid, inst << 12,
101 			   nvkm_client_name(engctx), subc, mthd, data);
102 		nvkm_wr32(device, 0x104004 + base, 0x00000040);
103 		stat &= ~0x00000040;
104 	}
105 
106 	if (stat) {
107 		nvkm_error(subdev, "intr %08x\n", stat);
108 		nvkm_wr32(device, 0x104004 + base, stat);
109 	}
110 
111 	nvkm_engctx_put(engctx);
112 }
113 
114 static int
115 gt215_ce_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
116 	      struct nvkm_oclass *oclass, void *data, u32 size,
117 	      struct nvkm_object **pobject)
118 {
119 	bool enable = (nv_device(parent)->chipset != 0xaf);
120 	struct nvkm_falcon *ce;
121 	int ret;
122 
123 	ret = nvkm_falcon_create(parent, engine, oclass, 0x104000, enable,
124 				 "PCE0", "ce0", &ce);
125 	*pobject = nv_object(ce);
126 	if (ret)
127 		return ret;
128 
129 	nv_subdev(ce)->unit = 0x00802000;
130 	nv_subdev(ce)->intr = gt215_ce_intr;
131 	nv_engine(ce)->cclass = &gt215_ce_cclass;
132 	nv_engine(ce)->sclass = gt215_ce_sclass;
133 	nv_falcon(ce)->code.data = gt215_ce_code;
134 	nv_falcon(ce)->code.size = sizeof(gt215_ce_code);
135 	nv_falcon(ce)->data.data = gt215_ce_data;
136 	nv_falcon(ce)->data.size = sizeof(gt215_ce_data);
137 	return 0;
138 }
139 
140 struct nvkm_oclass
141 gt215_ce_oclass = {
142 	.handle = NV_ENGINE(CE0, 0xa3),
143 	.ofuncs = &(struct nvkm_ofuncs) {
144 		.ctor = gt215_ce_ctor,
145 		.dtor = _nvkm_falcon_dtor,
146 		.init = _nvkm_falcon_init,
147 		.fini = _nvkm_falcon_fini,
148 	},
149 };
150