1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <engine/ce.h> 25 #include <engine/falcon.h> 26 #include "fuc/gf100.fuc3.h" 27 28 struct gf100_ce_priv { 29 struct nvkm_falcon base; 30 }; 31 32 /******************************************************************************* 33 * Copy object classes 34 ******************************************************************************/ 35 36 static struct nvkm_oclass 37 gf100_ce0_sclass[] = { 38 { 0x90b5, &nvkm_object_ofuncs }, 39 {}, 40 }; 41 42 static struct nvkm_oclass 43 gf100_ce1_sclass[] = { 44 { 0x90b8, &nvkm_object_ofuncs }, 45 {}, 46 }; 47 48 /******************************************************************************* 49 * PCE context 50 ******************************************************************************/ 51 52 static struct nvkm_ofuncs 53 gf100_ce_context_ofuncs = { 54 .ctor = _nvkm_falcon_context_ctor, 55 .dtor = _nvkm_falcon_context_dtor, 56 .init = _nvkm_falcon_context_init, 57 .fini = _nvkm_falcon_context_fini, 58 .rd32 = _nvkm_falcon_context_rd32, 59 .wr32 = _nvkm_falcon_context_wr32, 60 }; 61 62 static struct nvkm_oclass 63 gf100_ce0_cclass = { 64 .handle = NV_ENGCTX(CE0, 0xc0), 65 .ofuncs = &gf100_ce_context_ofuncs, 66 }; 67 68 static struct nvkm_oclass 69 gf100_ce1_cclass = { 70 .handle = NV_ENGCTX(CE1, 0xc0), 71 .ofuncs = &gf100_ce_context_ofuncs, 72 }; 73 74 /******************************************************************************* 75 * PCE engine/subdev functions 76 ******************************************************************************/ 77 78 static int 79 gf100_ce_init(struct nvkm_object *object) 80 { 81 struct gf100_ce_priv *priv = (void *)object; 82 int ret; 83 84 ret = nvkm_falcon_init(&priv->base); 85 if (ret) 86 return ret; 87 88 nv_wo32(priv, 0x084, nv_engidx(&priv->base.base) - NVDEV_ENGINE_CE0); 89 return 0; 90 } 91 92 static int 93 gf100_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 94 struct nvkm_oclass *oclass, void *data, u32 size, 95 struct nvkm_object **pobject) 96 { 97 struct gf100_ce_priv *priv; 98 int ret; 99 100 ret = nvkm_falcon_create(parent, engine, oclass, 0x104000, true, 101 "PCE0", "ce0", &priv); 102 *pobject = nv_object(priv); 103 if (ret) 104 return ret; 105 106 nv_subdev(priv)->unit = 0x00000040; 107 nv_subdev(priv)->intr = gt215_ce_intr; 108 nv_engine(priv)->cclass = &gf100_ce0_cclass; 109 nv_engine(priv)->sclass = gf100_ce0_sclass; 110 nv_falcon(priv)->code.data = gf100_pce_code; 111 nv_falcon(priv)->code.size = sizeof(gf100_pce_code); 112 nv_falcon(priv)->data.data = gf100_pce_data; 113 nv_falcon(priv)->data.size = sizeof(gf100_pce_data); 114 return 0; 115 } 116 117 static int 118 gf100_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 119 struct nvkm_oclass *oclass, void *data, u32 size, 120 struct nvkm_object **pobject) 121 { 122 struct gf100_ce_priv *priv; 123 int ret; 124 125 ret = nvkm_falcon_create(parent, engine, oclass, 0x105000, true, 126 "PCE1", "ce1", &priv); 127 *pobject = nv_object(priv); 128 if (ret) 129 return ret; 130 131 nv_subdev(priv)->unit = 0x00000080; 132 nv_subdev(priv)->intr = gt215_ce_intr; 133 nv_engine(priv)->cclass = &gf100_ce1_cclass; 134 nv_engine(priv)->sclass = gf100_ce1_sclass; 135 nv_falcon(priv)->code.data = gf100_pce_code; 136 nv_falcon(priv)->code.size = sizeof(gf100_pce_code); 137 nv_falcon(priv)->data.data = gf100_pce_data; 138 nv_falcon(priv)->data.size = sizeof(gf100_pce_data); 139 return 0; 140 } 141 142 struct nvkm_oclass 143 gf100_ce0_oclass = { 144 .handle = NV_ENGINE(CE0, 0xc0), 145 .ofuncs = &(struct nvkm_ofuncs) { 146 .ctor = gf100_ce0_ctor, 147 .dtor = _nvkm_falcon_dtor, 148 .init = gf100_ce_init, 149 .fini = _nvkm_falcon_fini, 150 .rd32 = _nvkm_falcon_rd32, 151 .wr32 = _nvkm_falcon_wr32, 152 }, 153 }; 154 155 struct nvkm_oclass 156 gf100_ce1_oclass = { 157 .handle = NV_ENGINE(CE1, 0xc0), 158 .ofuncs = &(struct nvkm_ofuncs) { 159 .ctor = gf100_ce1_ctor, 160 .dtor = _nvkm_falcon_dtor, 161 .init = gf100_ce_init, 162 .fini = _nvkm_falcon_fini, 163 .rd32 = _nvkm_falcon_rd32, 164 .wr32 = _nvkm_falcon_wr32, 165 }, 166 }; 167