1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25 #include "nouveau_drv.h" 26 #include "nouveau_dma.h" 27 #include "nouveau_fence.h" 28 #include "nouveau_vmm.h" 29 30 #include "nv50_display.h" 31 32 static int 33 nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) 34 { 35 int ret = RING_SPACE(chan, 8); 36 if (ret == 0) { 37 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); 38 OUT_RING (chan, chan->vram.handle); 39 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5); 40 OUT_RING (chan, upper_32_bits(virtual)); 41 OUT_RING (chan, lower_32_bits(virtual)); 42 OUT_RING (chan, sequence); 43 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); 44 OUT_RING (chan, 0x00000000); 45 FIRE_RING (chan); 46 } 47 return ret; 48 } 49 50 static int 51 nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence) 52 { 53 int ret = RING_SPACE(chan, 7); 54 if (ret == 0) { 55 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); 56 OUT_RING (chan, chan->vram.handle); 57 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); 58 OUT_RING (chan, upper_32_bits(virtual)); 59 OUT_RING (chan, lower_32_bits(virtual)); 60 OUT_RING (chan, sequence); 61 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL); 62 FIRE_RING (chan); 63 } 64 return ret; 65 } 66 67 static int 68 nv84_fence_emit(struct nouveau_fence *fence) 69 { 70 struct nouveau_channel *chan = fence->channel; 71 struct nv84_fence_chan *fctx = chan->fence; 72 u64 addr = fctx->vma->addr + chan->chid * 16; 73 74 return fctx->base.emit32(chan, addr, fence->base.seqno); 75 } 76 77 static int 78 nv84_fence_sync(struct nouveau_fence *fence, 79 struct nouveau_channel *prev, struct nouveau_channel *chan) 80 { 81 struct nv84_fence_chan *fctx = chan->fence; 82 u64 addr = fctx->vma->addr + prev->chid * 16; 83 84 return fctx->base.sync32(chan, addr, fence->base.seqno); 85 } 86 87 static u32 88 nv84_fence_read(struct nouveau_channel *chan) 89 { 90 struct nv84_fence_priv *priv = chan->drm->fence; 91 return nouveau_bo_rd32(priv->bo, chan->chid * 16/4); 92 } 93 94 static void 95 nv84_fence_context_del(struct nouveau_channel *chan) 96 { 97 struct nv84_fence_priv *priv = chan->drm->fence; 98 struct nv84_fence_chan *fctx = chan->fence; 99 100 nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence); 101 mutex_lock(&priv->mutex); 102 nouveau_vma_del(&fctx->vma); 103 mutex_unlock(&priv->mutex); 104 nouveau_fence_context_del(&fctx->base); 105 chan->fence = NULL; 106 nouveau_fence_context_free(&fctx->base); 107 } 108 109 int 110 nv84_fence_context_new(struct nouveau_channel *chan) 111 { 112 struct nv84_fence_priv *priv = chan->drm->fence; 113 struct nv84_fence_chan *fctx; 114 int ret; 115 116 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); 117 if (!fctx) 118 return -ENOMEM; 119 120 nouveau_fence_context_new(chan, &fctx->base); 121 fctx->base.emit = nv84_fence_emit; 122 fctx->base.sync = nv84_fence_sync; 123 fctx->base.read = nv84_fence_read; 124 fctx->base.emit32 = nv84_fence_emit32; 125 fctx->base.sync32 = nv84_fence_sync32; 126 fctx->base.sequence = nv84_fence_read(chan); 127 128 mutex_lock(&priv->mutex); 129 ret = nouveau_vma_new(priv->bo, chan->vmm, &fctx->vma); 130 mutex_unlock(&priv->mutex); 131 132 if (ret) 133 nv84_fence_context_del(chan); 134 return ret; 135 } 136 137 static bool 138 nv84_fence_suspend(struct nouveau_drm *drm) 139 { 140 struct nv84_fence_priv *priv = drm->fence; 141 int i; 142 143 priv->suspend = vmalloc(array_size(sizeof(u32), drm->chan.nr)); 144 if (priv->suspend) { 145 for (i = 0; i < drm->chan.nr; i++) 146 priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4); 147 } 148 149 return priv->suspend != NULL; 150 } 151 152 static void 153 nv84_fence_resume(struct nouveau_drm *drm) 154 { 155 struct nv84_fence_priv *priv = drm->fence; 156 int i; 157 158 if (priv->suspend) { 159 for (i = 0; i < drm->chan.nr; i++) 160 nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]); 161 vfree(priv->suspend); 162 priv->suspend = NULL; 163 } 164 } 165 166 static void 167 nv84_fence_destroy(struct nouveau_drm *drm) 168 { 169 struct nv84_fence_priv *priv = drm->fence; 170 nouveau_bo_unmap(priv->bo); 171 if (priv->bo) 172 nouveau_bo_unpin(priv->bo); 173 nouveau_bo_ref(NULL, &priv->bo); 174 drm->fence = NULL; 175 kfree(priv); 176 } 177 178 int 179 nv84_fence_create(struct nouveau_drm *drm) 180 { 181 struct nv84_fence_priv *priv; 182 u32 domain; 183 int ret; 184 185 priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); 186 if (!priv) 187 return -ENOMEM; 188 189 priv->base.dtor = nv84_fence_destroy; 190 priv->base.suspend = nv84_fence_suspend; 191 priv->base.resume = nv84_fence_resume; 192 priv->base.context_new = nv84_fence_context_new; 193 priv->base.context_del = nv84_fence_context_del; 194 195 priv->base.uevent = true; 196 197 mutex_init(&priv->mutex); 198 199 /* Use VRAM if there is any ; otherwise fallback to system memory */ 200 domain = drm->client.device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM : 201 /* 202 * fences created in sysmem must be non-cached or we 203 * will lose CPU/GPU coherency! 204 */ 205 TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; 206 ret = nouveau_bo_new(&drm->client, 16 * drm->chan.nr, 0, 207 domain, 0, 0, NULL, NULL, &priv->bo); 208 if (ret == 0) { 209 ret = nouveau_bo_pin(priv->bo, domain, false); 210 if (ret == 0) { 211 ret = nouveau_bo_map(priv->bo); 212 if (ret) 213 nouveau_bo_unpin(priv->bo); 214 } 215 if (ret) 216 nouveau_bo_ref(NULL, &priv->bo); 217 } 218 219 if (ret) 220 nv84_fence_destroy(drm); 221 return ret; 222 } 223